bhyve: convert NVMe logging statements
Convert the debug and warning logging macros to be parameterized and correctly use bhyve's PRINTLN macro. Reviewed by: imp Tested by: Jason Tubnor MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D24878
This commit is contained in:
Chuck Tuffli
parent
f36e950b9b
commit
0220a2aeed
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=362744
@ -83,8 +83,8 @@ __FBSDID("$FreeBSD$");
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static int nvme_debug = 0;
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#define DPRINTF(params) if (nvme_debug) PRINTLN params
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#define WPRINTF(params) PRINTLN params
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#define DPRINTF(fmt, args...) if (nvme_debug) PRINTLN(fmt, ##args)
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#define WPRINTF(fmt, args...) PRINTLN(fmt, ##args)
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/* defaults; can be overridden */
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#define NVME_MSIX_BAR 4
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@ -495,7 +495,7 @@ pci_nvme_init_logpages(struct pci_nvme_softc *sc)
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static void
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pci_nvme_reset_locked(struct pci_nvme_softc *sc)
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{
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DPRINTF(("%s", __func__));
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DPRINTF("%s", __func__);
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sc->regs.cap_lo = (ZERO_BASED(sc->max_qentries) & NVME_CAP_LO_REG_MQES_MASK) |
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(1 << NVME_CAP_LO_REG_CQR_SHIFT) |
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@ -562,23 +562,23 @@ pci_nvme_init_controller(struct vmctx *ctx, struct pci_nvme_softc *sc)
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{
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uint16_t acqs, asqs;
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DPRINTF(("%s", __func__));
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DPRINTF("%s", __func__);
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asqs = (sc->regs.aqa & NVME_AQA_REG_ASQS_MASK) + 1;
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sc->submit_queues[0].size = asqs;
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sc->submit_queues[0].qbase = vm_map_gpa(ctx, sc->regs.asq,
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sizeof(struct nvme_command) * asqs);
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DPRINTF(("%s mapping Admin-SQ guest 0x%lx, host: %p",
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__func__, sc->regs.asq, sc->submit_queues[0].qbase));
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DPRINTF("%s mapping Admin-SQ guest 0x%lx, host: %p",
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__func__, sc->regs.asq, sc->submit_queues[0].qbase);
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acqs = ((sc->regs.aqa >> NVME_AQA_REG_ACQS_SHIFT) &
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NVME_AQA_REG_ACQS_MASK) + 1;
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sc->compl_queues[0].size = acqs;
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sc->compl_queues[0].qbase = vm_map_gpa(ctx, sc->regs.acq,
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sizeof(struct nvme_completion) * acqs);
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DPRINTF(("%s mapping Admin-CQ guest 0x%lx, host: %p",
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__func__, sc->regs.acq, sc->compl_queues[0].qbase));
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DPRINTF("%s mapping Admin-CQ guest 0x%lx, host: %p",
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__func__, sc->regs.acq, sc->compl_queues[0].qbase);
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}
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static int
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@ -634,10 +634,10 @@ nvme_opc_delete_io_sq(struct pci_nvme_softc* sc, struct nvme_command* command,
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{
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uint16_t qid = command->cdw10 & 0xffff;
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DPRINTF(("%s DELETE_IO_SQ %u", __func__, qid));
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DPRINTF("%s DELETE_IO_SQ %u", __func__, qid);
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if (qid == 0 || qid > sc->num_squeues) {
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WPRINTF(("%s NOT PERMITTED queue id %u / num_squeues %u",
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__func__, qid, sc->num_squeues));
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WPRINTF("%s NOT PERMITTED queue id %u / num_squeues %u",
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__func__, qid, sc->num_squeues);
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pci_nvme_status_tc(&compl->status, NVME_SCT_COMMAND_SPECIFIC,
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NVME_SC_INVALID_QUEUE_IDENTIFIER);
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return (1);
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@ -657,8 +657,8 @@ nvme_opc_create_io_sq(struct pci_nvme_softc* sc, struct nvme_command* command,
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struct nvme_submission_queue *nsq;
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if ((qid == 0) || (qid > sc->num_squeues)) {
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WPRINTF(("%s queue index %u > num_squeues %u",
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__func__, qid, sc->num_squeues));
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WPRINTF("%s queue index %u > num_squeues %u",
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__func__, qid, sc->num_squeues);
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pci_nvme_status_tc(&compl->status,
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NVME_SCT_COMMAND_SPECIFIC,
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NVME_SC_INVALID_QUEUE_IDENTIFIER);
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@ -673,20 +673,20 @@ nvme_opc_create_io_sq(struct pci_nvme_softc* sc, struct nvme_command* command,
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nsq->cqid = (command->cdw11 >> 16) & 0xffff;
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nsq->qpriority = (command->cdw11 >> 1) & 0x03;
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DPRINTF(("%s sq %u size %u gaddr %p cqid %u", __func__,
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qid, nsq->size, nsq->qbase, nsq->cqid));
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DPRINTF("%s sq %u size %u gaddr %p cqid %u", __func__,
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qid, nsq->size, nsq->qbase, nsq->cqid);
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pci_nvme_status_genc(&compl->status, NVME_SC_SUCCESS);
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DPRINTF(("%s completed creating IOSQ qid %u",
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__func__, qid));
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DPRINTF("%s completed creating IOSQ qid %u",
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__func__, qid);
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} else {
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/*
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* Guest sent non-cont submission queue request.
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* This setting is unsupported by this emulation.
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*/
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WPRINTF(("%s unsupported non-contig (list-based) "
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"create i/o submission queue", __func__));
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WPRINTF("%s unsupported non-contig (list-based) "
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"create i/o submission queue", __func__);
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pci_nvme_status_genc(&compl->status, NVME_SC_INVALID_FIELD);
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}
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@ -699,10 +699,10 @@ nvme_opc_delete_io_cq(struct pci_nvme_softc* sc, struct nvme_command* command,
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{
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uint16_t qid = command->cdw10 & 0xffff;
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DPRINTF(("%s DELETE_IO_CQ %u", __func__, qid));
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DPRINTF("%s DELETE_IO_CQ %u", __func__, qid);
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if (qid == 0 || qid > sc->num_cqueues) {
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WPRINTF(("%s queue index %u / num_cqueues %u",
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__func__, qid, sc->num_cqueues));
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WPRINTF("%s queue index %u / num_cqueues %u",
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__func__, qid, sc->num_cqueues);
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pci_nvme_status_tc(&compl->status, NVME_SCT_COMMAND_SPECIFIC,
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NVME_SC_INVALID_QUEUE_IDENTIFIER);
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return (1);
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@ -722,8 +722,8 @@ nvme_opc_create_io_cq(struct pci_nvme_softc* sc, struct nvme_command* command,
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struct nvme_completion_queue *ncq;
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if ((qid == 0) || (qid > sc->num_cqueues)) {
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WPRINTF(("%s queue index %u > num_cqueues %u",
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__func__, qid, sc->num_cqueues));
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WPRINTF("%s queue index %u > num_cqueues %u",
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__func__, qid, sc->num_cqueues);
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pci_nvme_status_tc(&compl->status,
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NVME_SCT_COMMAND_SPECIFIC,
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NVME_SC_INVALID_QUEUE_IDENTIFIER);
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@ -744,9 +744,9 @@ nvme_opc_create_io_cq(struct pci_nvme_softc* sc, struct nvme_command* command,
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/*
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* Non-contig completion queue unsupported.
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*/
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WPRINTF(("%s unsupported non-contig (list-based) "
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WPRINTF("%s unsupported non-contig (list-based) "
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"create i/o completion queue",
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__func__));
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__func__);
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/* 0x12 = Invalid Use of Controller Memory Buffer */
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pci_nvme_status_genc(&compl->status, 0x12);
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@ -762,7 +762,7 @@ nvme_opc_get_log_page(struct pci_nvme_softc* sc, struct nvme_command* command,
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uint32_t logsize = (1 + ((command->cdw10 >> 16) & 0xFFF)) * 2;
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uint8_t logpage = command->cdw10 & 0xFF;
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DPRINTF(("%s log page %u len %u", __func__, logpage, logsize));
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DPRINTF("%s log page %u len %u", __func__, logpage, logsize);
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pci_nvme_status_genc(&compl->status, NVME_SC_SUCCESS);
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@ -784,8 +784,8 @@ nvme_opc_get_log_page(struct pci_nvme_softc* sc, struct nvme_command* command,
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NVME_COPY_TO_PRP);
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break;
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default:
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WPRINTF(("%s get log page %x command not supported",
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__func__, logpage));
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WPRINTF("%s get log page %x command not supported",
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__func__, logpage);
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pci_nvme_status_tc(&compl->status, NVME_SCT_COMMAND_SPECIFIC,
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NVME_SC_INVALID_LOG_PAGE);
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@ -800,8 +800,8 @@ nvme_opc_identify(struct pci_nvme_softc* sc, struct nvme_command* command,
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{
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void *dest;
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DPRINTF(("%s identify 0x%x nsid 0x%x", __func__,
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command->cdw10 & 0xFF, command->nsid));
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DPRINTF("%s identify 0x%x nsid 0x%x", __func__,
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command->cdw10 & 0xFF, command->nsid);
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switch (command->cdw10 & 0xFF) {
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case 0x00: /* return Identify Namespace data structure */
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@ -832,8 +832,8 @@ nvme_opc_identify(struct pci_nvme_softc* sc, struct nvme_command* command,
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case 0x14:
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case 0x15:
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default:
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DPRINTF(("%s unsupported identify command requested 0x%x",
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__func__, command->cdw10 & 0xFF));
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DPRINTF("%s unsupported identify command requested 0x%x",
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__func__, command->cdw10 & 0xFF);
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pci_nvme_status_genc(&compl->status, NVME_SC_INVALID_FIELD);
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return (1);
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}
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@ -850,29 +850,29 @@ nvme_set_feature_queues(struct pci_nvme_softc* sc, struct nvme_command* command,
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nqr = command->cdw11 & 0xFFFF;
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if (nqr == 0xffff) {
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WPRINTF(("%s: Illegal NSQR value %#x", __func__, nqr));
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WPRINTF("%s: Illegal NSQR value %#x", __func__, nqr);
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pci_nvme_status_genc(&compl->status, NVME_SC_INVALID_FIELD);
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return (-1);
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}
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sc->num_squeues = ONE_BASED(nqr);
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if (sc->num_squeues > sc->max_queues) {
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DPRINTF(("NSQR=%u is greater than max %u", sc->num_squeues,
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sc->max_queues));
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DPRINTF("NSQR=%u is greater than max %u", sc->num_squeues,
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sc->max_queues);
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sc->num_squeues = sc->max_queues;
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}
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nqr = (command->cdw11 >> 16) & 0xFFFF;
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if (nqr == 0xffff) {
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WPRINTF(("%s: Illegal NCQR value %#x", __func__, nqr));
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WPRINTF("%s: Illegal NCQR value %#x", __func__, nqr);
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pci_nvme_status_genc(&compl->status, NVME_SC_INVALID_FIELD);
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return (-1);
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}
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sc->num_cqueues = ONE_BASED(nqr);
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if (sc->num_cqueues > sc->max_queues) {
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DPRINTF(("NCQR=%u is greater than max %u", sc->num_cqueues,
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sc->max_queues));
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DPRINTF("NCQR=%u is greater than max %u", sc->num_cqueues,
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sc->max_queues);
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sc->num_cqueues = sc->max_queues;
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}
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@ -888,33 +888,33 @@ nvme_opc_set_features(struct pci_nvme_softc* sc, struct nvme_command* command,
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int feature = command->cdw10 & 0xFF;
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uint32_t iv;
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DPRINTF(("%s feature 0x%x", __func__, feature));
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DPRINTF("%s feature 0x%x", __func__, feature);
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compl->cdw0 = 0;
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switch (feature) {
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case NVME_FEAT_ARBITRATION:
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DPRINTF((" arbitration 0x%x", command->cdw11));
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DPRINTF(" arbitration 0x%x", command->cdw11);
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break;
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case NVME_FEAT_POWER_MANAGEMENT:
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DPRINTF((" power management 0x%x", command->cdw11));
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DPRINTF(" power management 0x%x", command->cdw11);
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break;
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case NVME_FEAT_LBA_RANGE_TYPE:
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DPRINTF((" lba range 0x%x", command->cdw11));
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DPRINTF(" lba range 0x%x", command->cdw11);
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break;
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case NVME_FEAT_TEMPERATURE_THRESHOLD:
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DPRINTF((" temperature threshold 0x%x", command->cdw11));
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DPRINTF(" temperature threshold 0x%x", command->cdw11);
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break;
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case NVME_FEAT_ERROR_RECOVERY:
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DPRINTF((" error recovery 0x%x", command->cdw11));
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DPRINTF(" error recovery 0x%x", command->cdw11);
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break;
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case NVME_FEAT_VOLATILE_WRITE_CACHE:
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DPRINTF((" volatile write cache 0x%x", command->cdw11));
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DPRINTF(" volatile write cache 0x%x", command->cdw11);
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break;
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case NVME_FEAT_NUMBER_OF_QUEUES:
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nvme_set_feature_queues(sc, command, compl);
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break;
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case NVME_FEAT_INTERRUPT_COALESCING:
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DPRINTF((" interrupt coalescing 0x%x", command->cdw11));
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DPRINTF(" interrupt coalescing 0x%x", command->cdw11);
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/* in uS */
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sc->intr_coales_aggr_time = ((command->cdw11 >> 8) & 0xFF)*100;
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@ -924,8 +924,8 @@ nvme_opc_set_features(struct pci_nvme_softc* sc, struct nvme_command* command,
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case NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION:
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iv = command->cdw11 & 0xFFFF;
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DPRINTF((" interrupt vector configuration 0x%x",
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command->cdw11));
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DPRINTF(" interrupt vector configuration 0x%x",
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command->cdw11);
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for (uint32_t i = 0; i < sc->num_cqueues + 1; i++) {
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if (sc->compl_queues[i].intr_vec == iv) {
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@ -939,23 +939,23 @@ nvme_opc_set_features(struct pci_nvme_softc* sc, struct nvme_command* command,
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}
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break;
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case NVME_FEAT_WRITE_ATOMICITY:
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DPRINTF((" write atomicity 0x%x", command->cdw11));
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DPRINTF(" write atomicity 0x%x", command->cdw11);
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break;
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case NVME_FEAT_ASYNC_EVENT_CONFIGURATION:
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DPRINTF((" async event configuration 0x%x",
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command->cdw11));
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DPRINTF(" async event configuration 0x%x",
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command->cdw11);
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sc->async_ev_config = command->cdw11;
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break;
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case NVME_FEAT_SOFTWARE_PROGRESS_MARKER:
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DPRINTF((" software progress marker 0x%x",
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command->cdw11));
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DPRINTF(" software progress marker 0x%x",
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command->cdw11);
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break;
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case 0x0C:
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DPRINTF((" autonomous power state transition 0x%x",
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command->cdw11));
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DPRINTF(" autonomous power state transition 0x%x",
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command->cdw11);
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break;
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default:
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WPRINTF(("%s invalid feature", __func__));
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WPRINTF("%s invalid feature", __func__);
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pci_nvme_status_genc(&compl->status, NVME_SC_INVALID_FIELD);
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return (1);
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}
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@ -970,22 +970,22 @@ nvme_opc_get_features(struct pci_nvme_softc* sc, struct nvme_command* command,
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{
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int feature = command->cdw10 & 0xFF;
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DPRINTF(("%s feature 0x%x", __func__, feature));
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DPRINTF("%s feature 0x%x", __func__, feature);
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compl->cdw0 = 0;
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switch (feature) {
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case NVME_FEAT_ARBITRATION:
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DPRINTF((" arbitration"));
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DPRINTF(" arbitration");
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break;
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case NVME_FEAT_POWER_MANAGEMENT:
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DPRINTF((" power management"));
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DPRINTF(" power management");
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break;
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case NVME_FEAT_LBA_RANGE_TYPE:
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DPRINTF((" lba range"));
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DPRINTF(" lba range");
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break;
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case NVME_FEAT_TEMPERATURE_THRESHOLD:
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DPRINTF((" temperature threshold"));
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DPRINTF(" temperature threshold");
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switch ((command->cdw11 >> 20) & 0x3) {
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case 0:
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/* Over temp threshold */
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@ -996,47 +996,47 @@ nvme_opc_get_features(struct pci_nvme_softc* sc, struct nvme_command* command,
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compl->cdw0 = 0;
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break;
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default:
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WPRINTF((" invalid threshold type select"));
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WPRINTF(" invalid threshold type select");
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pci_nvme_status_genc(&compl->status,
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NVME_SC_INVALID_FIELD);
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return (1);
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}
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break;
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case NVME_FEAT_ERROR_RECOVERY:
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DPRINTF((" error recovery"));
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DPRINTF(" error recovery");
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break;
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case NVME_FEAT_VOLATILE_WRITE_CACHE:
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DPRINTF((" volatile write cache"));
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DPRINTF(" volatile write cache");
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break;
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case NVME_FEAT_NUMBER_OF_QUEUES:
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compl->cdw0 = NVME_FEATURE_NUM_QUEUES(sc);
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DPRINTF((" number of queues (submit %u, completion %u)",
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DPRINTF(" number of queues (submit %u, completion %u)",
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compl->cdw0 & 0xFFFF,
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(compl->cdw0 >> 16) & 0xFFFF));
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(compl->cdw0 >> 16) & 0xFFFF);
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break;
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case NVME_FEAT_INTERRUPT_COALESCING:
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DPRINTF((" interrupt coalescing"));
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DPRINTF(" interrupt coalescing");
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break;
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case NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION:
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DPRINTF((" interrupt vector configuration"));
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DPRINTF(" interrupt vector configuration");
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break;
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case NVME_FEAT_WRITE_ATOMICITY:
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DPRINTF((" write atomicity"));
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DPRINTF(" write atomicity");
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break;
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case NVME_FEAT_ASYNC_EVENT_CONFIGURATION:
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DPRINTF((" async event configuration"));
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DPRINTF(" async event configuration");
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sc->async_ev_config = command->cdw11;
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break;
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case NVME_FEAT_SOFTWARE_PROGRESS_MARKER:
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DPRINTF((" software progress marker"));
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DPRINTF(" software progress marker");
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break;
|
||||
case 0x0C:
|
||||
DPRINTF((" autonomous power state transition"));
|
||||
DPRINTF(" autonomous power state transition");
|
||||
break;
|
||||
default:
|
||||
WPRINTF(("%s invalid feature 0x%x", __func__, feature));
|
||||
WPRINTF("%s invalid feature 0x%x", __func__, feature);
|
||||
pci_nvme_status_genc(&compl->status, NVME_SC_INVALID_FIELD);
|
||||
return (1);
|
||||
}
|
||||
@ -1049,8 +1049,8 @@ static int
|
||||
nvme_opc_abort(struct pci_nvme_softc* sc, struct nvme_command* command,
|
||||
struct nvme_completion* compl)
|
||||
{
|
||||
DPRINTF(("%s submission queue %u, command ID 0x%x", __func__,
|
||||
command->cdw10 & 0xFFFF, (command->cdw10 >> 16) & 0xFFFF));
|
||||
DPRINTF("%s submission queue %u, command ID 0x%x", __func__,
|
||||
command->cdw10 & 0xFFFF, (command->cdw10 >> 16) & 0xFFFF);
|
||||
|
||||
/* TODO: search for the command ID and abort it */
|
||||
|
||||
@ -1063,7 +1063,7 @@ static int
|
||||
nvme_opc_async_event_req(struct pci_nvme_softc* sc,
|
||||
struct nvme_command* command, struct nvme_completion* compl)
|
||||
{
|
||||
DPRINTF(("%s async event request 0x%x", __func__, command->cdw11));
|
||||
DPRINTF("%s async event request 0x%x", __func__, command->cdw11);
|
||||
|
||||
/*
|
||||
* TODO: raise events when they happen based on the Set Features cmd.
|
||||
@ -1084,7 +1084,7 @@ pci_nvme_handle_admin_cmd(struct pci_nvme_softc* sc, uint64_t value)
|
||||
struct nvme_completion_queue *cq;
|
||||
uint16_t sqhead;
|
||||
|
||||
DPRINTF(("%s index %u", __func__, (uint32_t)value));
|
||||
DPRINTF("%s index %u", __func__, (uint32_t)value);
|
||||
|
||||
sq = &sc->submit_queues[0];
|
||||
cq = &sc->compl_queues[0];
|
||||
@ -1092,12 +1092,12 @@ pci_nvme_handle_admin_cmd(struct pci_nvme_softc* sc, uint64_t value)
|
||||
sqhead = atomic_load_acq_short(&sq->head);
|
||||
|
||||
if (atomic_testandset_int(&sq->busy, 1)) {
|
||||
DPRINTF(("%s SQ busy, head %u, tail %u",
|
||||
__func__, sqhead, sq->tail));
|
||||
DPRINTF("%s SQ busy, head %u, tail %u",
|
||||
__func__, sqhead, sq->tail);
|
||||
return;
|
||||
}
|
||||
|
||||
DPRINTF(("sqhead %u, tail %u", sqhead, sq->tail));
|
||||
DPRINTF("sqhead %u, tail %u", sqhead, sq->tail);
|
||||
|
||||
while (sqhead != atomic_load_acq_short(&sq->tail)) {
|
||||
cmd = &(sq->qbase)[sqhead];
|
||||
@ -1106,51 +1106,51 @@ pci_nvme_handle_admin_cmd(struct pci_nvme_softc* sc, uint64_t value)
|
||||
|
||||
switch (cmd->opc) {
|
||||
case NVME_OPC_DELETE_IO_SQ:
|
||||
DPRINTF(("%s command DELETE_IO_SQ", __func__));
|
||||
DPRINTF("%s command DELETE_IO_SQ", __func__);
|
||||
nvme_opc_delete_io_sq(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_CREATE_IO_SQ:
|
||||
DPRINTF(("%s command CREATE_IO_SQ", __func__));
|
||||
DPRINTF("%s command CREATE_IO_SQ", __func__);
|
||||
nvme_opc_create_io_sq(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_DELETE_IO_CQ:
|
||||
DPRINTF(("%s command DELETE_IO_CQ", __func__));
|
||||
DPRINTF("%s command DELETE_IO_CQ", __func__);
|
||||
nvme_opc_delete_io_cq(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_CREATE_IO_CQ:
|
||||
DPRINTF(("%s command CREATE_IO_CQ", __func__));
|
||||
DPRINTF("%s command CREATE_IO_CQ", __func__);
|
||||
nvme_opc_create_io_cq(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_GET_LOG_PAGE:
|
||||
DPRINTF(("%s command GET_LOG_PAGE", __func__));
|
||||
DPRINTF("%s command GET_LOG_PAGE", __func__);
|
||||
nvme_opc_get_log_page(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_IDENTIFY:
|
||||
DPRINTF(("%s command IDENTIFY", __func__));
|
||||
DPRINTF("%s command IDENTIFY", __func__);
|
||||
nvme_opc_identify(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_ABORT:
|
||||
DPRINTF(("%s command ABORT", __func__));
|
||||
DPRINTF("%s command ABORT", __func__);
|
||||
nvme_opc_abort(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_SET_FEATURES:
|
||||
DPRINTF(("%s command SET_FEATURES", __func__));
|
||||
DPRINTF("%s command SET_FEATURES", __func__);
|
||||
nvme_opc_set_features(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_GET_FEATURES:
|
||||
DPRINTF(("%s command GET_FEATURES", __func__));
|
||||
DPRINTF("%s command GET_FEATURES", __func__);
|
||||
nvme_opc_get_features(sc, cmd, &compl);
|
||||
break;
|
||||
case NVME_OPC_ASYNC_EVENT_REQUEST:
|
||||
DPRINTF(("%s command ASYNC_EVENT_REQ", __func__));
|
||||
DPRINTF("%s command ASYNC_EVENT_REQ", __func__);
|
||||
/* XXX dont care, unhandled for now
|
||||
nvme_opc_async_event_req(sc, cmd, &compl);
|
||||
*/
|
||||
compl.status = NVME_NO_STATUS;
|
||||
break;
|
||||
default:
|
||||
WPRINTF(("0x%x command is not implemented",
|
||||
cmd->opc));
|
||||
WPRINTF("0x%x command is not implemented",
|
||||
cmd->opc);
|
||||
pci_nvme_status_genc(&compl.status, NVME_SC_INVALID_OPCODE);
|
||||
}
|
||||
sqhead = (sqhead + 1) % sq->size;
|
||||
@ -1173,7 +1173,7 @@ pci_nvme_handle_admin_cmd(struct pci_nvme_softc* sc, uint64_t value)
|
||||
}
|
||||
}
|
||||
|
||||
DPRINTF(("setting sqhead %u", sqhead));
|
||||
DPRINTF("setting sqhead %u", sqhead);
|
||||
atomic_store_short(&sq->head, sqhead);
|
||||
atomic_store_int(&sq->busy, 0);
|
||||
|
||||
@ -1208,7 +1208,7 @@ pci_nvme_append_iov_req(struct pci_nvme_softc *sc, struct pci_nvme_ioreq *req,
|
||||
if (iovidx == NVME_MAX_BLOCKIOVS) {
|
||||
int err = 0;
|
||||
|
||||
DPRINTF(("large I/O, doing partial req"));
|
||||
DPRINTF("large I/O, doing partial req");
|
||||
|
||||
iovidx = 0;
|
||||
req->io_req.br_iovcnt = 0;
|
||||
@ -1252,7 +1252,7 @@ pci_nvme_append_iov_req(struct pci_nvme_softc *sc, struct pci_nvme_ioreq *req,
|
||||
void *gptr;
|
||||
|
||||
if ((lba + size) > sc->nvstore.size) {
|
||||
WPRINTF(("%s write would overflow RAM", __func__));
|
||||
WPRINTF("%s write would overflow RAM", __func__);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
@ -1275,9 +1275,9 @@ pci_nvme_set_completion(struct pci_nvme_softc *sc,
|
||||
struct nvme_completion *compl;
|
||||
int phase;
|
||||
|
||||
DPRINTF(("%s sqid %d cqid %u cid %u status: 0x%x 0x%x",
|
||||
DPRINTF("%s sqid %d cqid %u cid %u status: 0x%x 0x%x",
|
||||
__func__, sqid, sq->cqid, cid, NVME_STATUS_GET_SCT(status),
|
||||
NVME_STATUS_GET_SC(status)));
|
||||
NVME_STATUS_GET_SC(status));
|
||||
|
||||
pthread_mutex_lock(&cq->mtx);
|
||||
|
||||
@ -1303,8 +1303,8 @@ pci_nvme_set_completion(struct pci_nvme_softc *sc,
|
||||
if (cq->intr_en & NVME_CQ_INTEN) {
|
||||
pci_generate_msix(sc->nsc_pi, cq->intr_vec);
|
||||
} else {
|
||||
DPRINTF(("%s: CQ%u interrupt disabled\n",
|
||||
__func__, sq->cqid));
|
||||
DPRINTF("%s: CQ%u interrupt disabled",
|
||||
__func__, sq->cqid);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1366,7 +1366,7 @@ pci_nvme_io_done(struct blockif_req *br, int err)
|
||||
struct nvme_submission_queue *sq = req->nvme_sq;
|
||||
uint16_t code, status;
|
||||
|
||||
DPRINTF(("%s error %d %s", __func__, err, strerror(err)));
|
||||
DPRINTF("%s error %d %s", __func__, err, strerror(err));
|
||||
|
||||
/* TODO return correct error */
|
||||
code = err ? NVME_SC_DATA_TRANSFER_ERROR : NVME_SC_SUCCESS;
|
||||
@ -1381,7 +1381,7 @@ pci_nvme_io_partial(struct blockif_req *br, int err)
|
||||
{
|
||||
struct pci_nvme_ioreq *req = br->br_param;
|
||||
|
||||
DPRINTF(("%s error %d %s", __func__, err, strerror(err)));
|
||||
DPRINTF("%s error %d %s", __func__, err, strerror(err));
|
||||
|
||||
pthread_cond_signal(&req->cv);
|
||||
}
|
||||
@ -1520,14 +1520,14 @@ pci_nvme_handle_io_cmd(struct pci_nvme_softc* sc, uint16_t idx)
|
||||
sq = &sc->submit_queues[idx];
|
||||
|
||||
if (atomic_testandset_int(&sq->busy, 1)) {
|
||||
DPRINTF(("%s sqid %u busy", __func__, idx));
|
||||
DPRINTF("%s sqid %u busy", __func__, idx);
|
||||
return;
|
||||
}
|
||||
|
||||
sqhead = atomic_load_acq_short(&sq->head);
|
||||
|
||||
DPRINTF(("nvme_handle_io qid %u head %u tail %u cmdlist %p",
|
||||
idx, sqhead, sq->tail, sq->qbase));
|
||||
DPRINTF("nvme_handle_io qid %u head %u tail %u cmdlist %p",
|
||||
idx, sqhead, sq->tail, sq->qbase);
|
||||
|
||||
while (sqhead != atomic_load_acq_short(&sq->tail)) {
|
||||
struct nvme_command *cmd;
|
||||
@ -1550,8 +1550,8 @@ pci_nvme_handle_io_cmd(struct pci_nvme_softc* sc, uint16_t idx)
|
||||
continue;
|
||||
} else if (cmd->opc == 0x08) {
|
||||
/* TODO: write zeroes */
|
||||
WPRINTF(("%s write zeroes lba 0x%lx blocks %u",
|
||||
__func__, lba, cmd->cdw12 & 0xFFFF));
|
||||
WPRINTF("%s write zeroes lba 0x%lx blocks %u",
|
||||
__func__, lba, cmd->cdw12 & 0xFFFF);
|
||||
pci_nvme_status_genc(&status, NVME_SC_SUCCESS);
|
||||
pci_nvme_set_completion(sc, sq, idx, cmd->cid, 0,
|
||||
status, 1);
|
||||
@ -1585,17 +1585,17 @@ pci_nvme_handle_io_cmd(struct pci_nvme_softc* sc, uint16_t idx)
|
||||
* increase page count
|
||||
*/
|
||||
|
||||
DPRINTF(("[h%u:t%u:n%u] %s starting LBA 0x%lx blocks %lu "
|
||||
DPRINTF("[h%u:t%u:n%u] %s starting LBA 0x%lx blocks %lu "
|
||||
"(%lu-bytes)",
|
||||
sqhead==0 ? sq->size-1 : sqhead-1, sq->tail, sq->size,
|
||||
cmd->opc == NVME_OPC_WRITE ?
|
||||
"WRITE" : "READ",
|
||||
lba, nblocks, bytes));
|
||||
lba, nblocks, bytes);
|
||||
|
||||
cmd->prp1 &= ~(0x03UL);
|
||||
cmd->prp2 &= ~(0x03UL);
|
||||
|
||||
DPRINTF((" prp1 0x%lx prp2 0x%lx", cmd->prp1, cmd->prp2));
|
||||
DPRINTF(" prp1 0x%lx prp2 0x%lx", cmd->prp1, cmd->prp2);
|
||||
|
||||
size = bytes;
|
||||
lba *= sc->nvstore.sectsz;
|
||||
@ -1653,7 +1653,7 @@ pci_nvme_handle_io_cmd(struct pci_nvme_softc* sc, uint16_t idx)
|
||||
i = 0;
|
||||
}
|
||||
if (prp_list[i] == 0) {
|
||||
WPRINTF(("PRP2[%d] = 0 !!!", i));
|
||||
WPRINTF("PRP2[%d] = 0 !!!", i);
|
||||
err = 1;
|
||||
break;
|
||||
}
|
||||
@ -1699,8 +1699,8 @@ pci_nvme_handle_io_cmd(struct pci_nvme_softc* sc, uint16_t idx)
|
||||
err = blockif_write(sc->nvstore.ctx, &req->io_req);
|
||||
break;
|
||||
default:
|
||||
WPRINTF(("%s unhandled io command 0x%x",
|
||||
__func__, cmd->opc));
|
||||
WPRINTF("%s unhandled io command 0x%x",
|
||||
__func__, cmd->opc);
|
||||
err = 1;
|
||||
}
|
||||
|
||||
@ -1725,8 +1725,8 @@ static void
|
||||
pci_nvme_handle_doorbell(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
||||
uint64_t idx, int is_sq, uint64_t value)
|
||||
{
|
||||
DPRINTF(("nvme doorbell %lu, %s, val 0x%lx",
|
||||
idx, is_sq ? "SQ" : "CQ", value & 0xFFFF));
|
||||
DPRINTF("nvme doorbell %lu, %s, val 0x%lx",
|
||||
idx, is_sq ? "SQ" : "CQ", value & 0xFFFF);
|
||||
|
||||
if (is_sq) {
|
||||
atomic_store_short(&sc->submit_queues[idx].tail,
|
||||
@ -1737,18 +1737,18 @@ pci_nvme_handle_doorbell(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
||||
} else {
|
||||
/* submission queue; handle new entries in SQ */
|
||||
if (idx > sc->num_squeues) {
|
||||
WPRINTF(("%s SQ index %lu overflow from "
|
||||
WPRINTF("%s SQ index %lu overflow from "
|
||||
"guest (max %u)",
|
||||
__func__, idx, sc->num_squeues));
|
||||
__func__, idx, sc->num_squeues);
|
||||
return;
|
||||
}
|
||||
pci_nvme_handle_io_cmd(sc, (uint16_t)idx);
|
||||
}
|
||||
} else {
|
||||
if (idx > sc->num_cqueues) {
|
||||
WPRINTF(("%s queue index %lu overflow from "
|
||||
WPRINTF("%s queue index %lu overflow from "
|
||||
"guest (max %u)",
|
||||
__func__, idx, sc->num_cqueues));
|
||||
__func__, idx, sc->num_cqueues);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -1763,46 +1763,46 @@ pci_nvme_bar0_reg_dumps(const char *func, uint64_t offset, int iswrite)
|
||||
|
||||
switch (offset) {
|
||||
case NVME_CR_CAP_LOW:
|
||||
DPRINTF(("%s %s NVME_CR_CAP_LOW", func, s));
|
||||
DPRINTF("%s %s NVME_CR_CAP_LOW", func, s);
|
||||
break;
|
||||
case NVME_CR_CAP_HI:
|
||||
DPRINTF(("%s %s NVME_CR_CAP_HI", func, s));
|
||||
DPRINTF("%s %s NVME_CR_CAP_HI", func, s);
|
||||
break;
|
||||
case NVME_CR_VS:
|
||||
DPRINTF(("%s %s NVME_CR_VS", func, s));
|
||||
DPRINTF("%s %s NVME_CR_VS", func, s);
|
||||
break;
|
||||
case NVME_CR_INTMS:
|
||||
DPRINTF(("%s %s NVME_CR_INTMS", func, s));
|
||||
DPRINTF("%s %s NVME_CR_INTMS", func, s);
|
||||
break;
|
||||
case NVME_CR_INTMC:
|
||||
DPRINTF(("%s %s NVME_CR_INTMC", func, s));
|
||||
DPRINTF("%s %s NVME_CR_INTMC", func, s);
|
||||
break;
|
||||
case NVME_CR_CC:
|
||||
DPRINTF(("%s %s NVME_CR_CC", func, s));
|
||||
DPRINTF("%s %s NVME_CR_CC", func, s);
|
||||
break;
|
||||
case NVME_CR_CSTS:
|
||||
DPRINTF(("%s %s NVME_CR_CSTS", func, s));
|
||||
DPRINTF("%s %s NVME_CR_CSTS", func, s);
|
||||
break;
|
||||
case NVME_CR_NSSR:
|
||||
DPRINTF(("%s %s NVME_CR_NSSR", func, s));
|
||||
DPRINTF("%s %s NVME_CR_NSSR", func, s);
|
||||
break;
|
||||
case NVME_CR_AQA:
|
||||
DPRINTF(("%s %s NVME_CR_AQA", func, s));
|
||||
DPRINTF("%s %s NVME_CR_AQA", func, s);
|
||||
break;
|
||||
case NVME_CR_ASQ_LOW:
|
||||
DPRINTF(("%s %s NVME_CR_ASQ_LOW", func, s));
|
||||
DPRINTF("%s %s NVME_CR_ASQ_LOW", func, s);
|
||||
break;
|
||||
case NVME_CR_ASQ_HI:
|
||||
DPRINTF(("%s %s NVME_CR_ASQ_HI", func, s));
|
||||
DPRINTF("%s %s NVME_CR_ASQ_HI", func, s);
|
||||
break;
|
||||
case NVME_CR_ACQ_LOW:
|
||||
DPRINTF(("%s %s NVME_CR_ACQ_LOW", func, s));
|
||||
DPRINTF("%s %s NVME_CR_ACQ_LOW", func, s);
|
||||
break;
|
||||
case NVME_CR_ACQ_HI:
|
||||
DPRINTF(("%s %s NVME_CR_ACQ_HI", func, s));
|
||||
DPRINTF("%s %s NVME_CR_ACQ_HI", func, s);
|
||||
break;
|
||||
default:
|
||||
DPRINTF(("unknown nvme bar-0 offset 0x%lx", offset));
|
||||
DPRINTF("unknown nvme bar-0 offset 0x%lx", offset);
|
||||
}
|
||||
|
||||
}
|
||||
@ -1819,9 +1819,9 @@ pci_nvme_write_bar_0(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
||||
int is_sq = (belloffset % 8) < 4;
|
||||
|
||||
if (belloffset > ((sc->max_queues+1) * 8 - 4)) {
|
||||
WPRINTF(("guest attempted an overflow write offset "
|
||||
WPRINTF("guest attempted an overflow write offset "
|
||||
"0x%lx, val 0x%lx in %s",
|
||||
offset, value, __func__));
|
||||
offset, value, __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -1829,13 +1829,13 @@ pci_nvme_write_bar_0(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
||||
return;
|
||||
}
|
||||
|
||||
DPRINTF(("nvme-write offset 0x%lx, size %d, value 0x%lx",
|
||||
offset, size, value));
|
||||
DPRINTF("nvme-write offset 0x%lx, size %d, value 0x%lx",
|
||||
offset, size, value);
|
||||
|
||||
if (size != 4) {
|
||||
WPRINTF(("guest wrote invalid size %d (offset 0x%lx, "
|
||||
WPRINTF("guest wrote invalid size %d (offset 0x%lx, "
|
||||
"val 0x%lx) to bar0 in %s",
|
||||
size, offset, value, __func__));
|
||||
size, offset, value, __func__);
|
||||
/* TODO: shutdown device */
|
||||
return;
|
||||
}
|
||||
@ -1861,12 +1861,12 @@ pci_nvme_write_bar_0(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
||||
case NVME_CR_CC:
|
||||
ccreg = (uint32_t)value;
|
||||
|
||||
DPRINTF(("%s NVME_CR_CC en %x css %x shn %x iosqes %u "
|
||||
DPRINTF("%s NVME_CR_CC en %x css %x shn %x iosqes %u "
|
||||
"iocqes %u",
|
||||
__func__,
|
||||
NVME_CC_GET_EN(ccreg), NVME_CC_GET_CSS(ccreg),
|
||||
NVME_CC_GET_SHN(ccreg), NVME_CC_GET_IOSQES(ccreg),
|
||||
NVME_CC_GET_IOCQES(ccreg)));
|
||||
NVME_CC_GET_IOCQES(ccreg));
|
||||
|
||||
if (NVME_CC_GET_SHN(ccreg)) {
|
||||
/* perform shutdown - flush out data to backend */
|
||||
@ -1920,8 +1920,8 @@ pci_nvme_write_bar_0(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
||||
(value << 32);
|
||||
break;
|
||||
default:
|
||||
DPRINTF(("%s unknown offset 0x%lx, value 0x%lx size %d",
|
||||
__func__, offset, value, size));
|
||||
DPRINTF("%s unknown offset 0x%lx, value 0x%lx size %d",
|
||||
__func__, offset, value, size);
|
||||
}
|
||||
pthread_mutex_unlock(&sc->mtx);
|
||||
}
|
||||
@ -1934,8 +1934,8 @@ pci_nvme_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
|
||||
if (baridx == pci_msix_table_bar(pi) ||
|
||||
baridx == pci_msix_pba_bar(pi)) {
|
||||
DPRINTF(("nvme-write baridx %d, msix: off 0x%lx, size %d, "
|
||||
" value 0x%lx", baridx, offset, size, value));
|
||||
DPRINTF("nvme-write baridx %d, msix: off 0x%lx, size %d, "
|
||||
" value 0x%lx", baridx, offset, size, value);
|
||||
|
||||
pci_emul_msix_twrite(pi, offset, size, value);
|
||||
return;
|
||||
@ -1947,8 +1947,8 @@ pci_nvme_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
break;
|
||||
|
||||
default:
|
||||
DPRINTF(("%s unknown baridx %d, val 0x%lx",
|
||||
__func__, baridx, value));
|
||||
DPRINTF("%s unknown baridx %d, val 0x%lx",
|
||||
__func__, baridx, value);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1966,7 +1966,7 @@ static uint64_t pci_nvme_read_bar_0(struct pci_nvme_softc* sc,
|
||||
pthread_mutex_unlock(&sc->mtx);
|
||||
} else {
|
||||
value = 0;
|
||||
WPRINTF(("pci_nvme: read invalid offset %ld", offset));
|
||||
WPRINTF("pci_nvme: read invalid offset %ld", offset);
|
||||
}
|
||||
|
||||
switch (size) {
|
||||
@ -1981,8 +1981,8 @@ static uint64_t pci_nvme_read_bar_0(struct pci_nvme_softc* sc,
|
||||
break;
|
||||
}
|
||||
|
||||
DPRINTF((" nvme-read offset 0x%lx, size %d -> value 0x%x",
|
||||
offset, size, (uint32_t)value));
|
||||
DPRINTF(" nvme-read offset 0x%lx, size %d -> value 0x%x",
|
||||
offset, size, (uint32_t)value);
|
||||
|
||||
return (value);
|
||||
}
|
||||
@ -1997,8 +1997,8 @@ pci_nvme_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
|
||||
|
||||
if (baridx == pci_msix_table_bar(pi) ||
|
||||
baridx == pci_msix_pba_bar(pi)) {
|
||||
DPRINTF(("nvme-read bar: %d, msix: regoff 0x%lx, size %d",
|
||||
baridx, offset, size));
|
||||
DPRINTF("nvme-read bar: %d, msix: regoff 0x%lx, size %d",
|
||||
baridx, offset, size);
|
||||
|
||||
return pci_emul_msix_tread(pi, offset, size);
|
||||
}
|
||||
@ -2008,7 +2008,7 @@ pci_nvme_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
|
||||
return pci_nvme_read_bar_0(sc, offset, size);
|
||||
|
||||
default:
|
||||
DPRINTF(("unknown bar %d, 0x%lx", baridx, offset));
|
||||
DPRINTF("unknown bar %d, 0x%lx", baridx, offset);
|
||||
}
|
||||
|
||||
return (0);
|
||||
@ -2174,23 +2174,23 @@ pci_nvme_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
2 * sizeof(uint32_t) * (sc->max_queues + 1);
|
||||
pci_membar_sz = MAX(pci_membar_sz, NVME_MMIO_SPACE_MIN);
|
||||
|
||||
DPRINTF(("nvme membar size: %u", pci_membar_sz));
|
||||
DPRINTF("nvme membar size: %u", pci_membar_sz);
|
||||
|
||||
error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM64, pci_membar_sz);
|
||||
if (error) {
|
||||
WPRINTF(("%s pci alloc mem bar failed", __func__));
|
||||
WPRINTF("%s pci alloc mem bar failed", __func__);
|
||||
goto done;
|
||||
}
|
||||
|
||||
error = pci_emul_add_msixcap(pi, sc->max_queues + 1, NVME_MSIX_BAR);
|
||||
if (error) {
|
||||
WPRINTF(("%s pci add msixcap failed", __func__));
|
||||
WPRINTF("%s pci add msixcap failed", __func__);
|
||||
goto done;
|
||||
}
|
||||
|
||||
error = pci_emul_add_pciecap(pi, PCIEM_TYPE_ROOT_INT_EP);
|
||||
if (error) {
|
||||
WPRINTF(("%s pci add Express capability failed", __func__));
|
||||
WPRINTF("%s pci add Express capability failed", __func__);
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user