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Fix comment.

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This commit is contained in:
Ruslan Bukin 2016-02-22 14:19:45 +00:00
parent c7977d4cee
commit 041c26e7ff
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=295892
1 changed files with 3 additions and 2 deletions
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5
sys/riscv/riscv/timer.c
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@ -145,8 +145,9 @@ riscv_tmr_intr(void *arg)
/*
* Clear interrupt pending bit.
* Note sip register is unimplemented in Spike simulator,
* so use machine command to clear in mip.
* Note: SIP_STIP bit is not implemented in sip register
* in Spike simulator, so use machine command to clear
* interrupt pending bit in mip.
*/
machine_command(ECALL_CLEAR_PENDING, 0);