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Make Marvell Armada reset registers usage generic

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Define reset registers for both Armada38X and ArmadaXP and
choose proper one during runtime based on information from FDT.

Submitted by: Rafal Kozik <rk@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential Revision: https://reviews.freebsd.org/D14745
This commit is contained in:
Marcin Wojtas 2018-04-04 10:14:43 +00:00
parent ccc1e6eb49
commit 04bb9a6625
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=332002
4 changed files with 15 additions and 17 deletions
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8
sys/arm/mv/armada/wdt.c
View File

@ -245,9 +245,9 @@ mv_wdt_enable_armada_38x_xp_helper()
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
val = read_cpu_misc(RSTOUTn_MASK);
val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val &= ~RSTOUTn_MASK_WD;
write_cpu_misc(RSTOUTn_MASK, val);
write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
}
static void
@ -305,9 +305,9 @@ mv_wdt_disable_armada_38x_xp_helper(void)
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
val = read_cpu_misc(RSTOUTn_MASK);
val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val |= RSTOUTn_MASK_WD;
write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
}
static void

4
sys/arm/mv/mv_armv7_machdep.c
View File

@ -439,8 +439,8 @@ static void
mv_cpu_reset(platform_t plat)
{
write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7);
write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7);
}
#if defined(SOC_MV_ARMADA38X)

12
sys/arm/mv/mvreg.h
View File

@ -103,17 +103,15 @@
/*
* System reset
*/
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define RSTOUTn_MASK 0x60
#define SYSTEM_SOFT_RESET 0x64
#define SOFT_RST_OUT_EN 0x00000001
#define SYS_SOFT_RST 0x00000001
#else
#define RSTOUTn_MASK_ARMV7 0x60
#define SYSTEM_SOFT_RESET_ARMV7 0x64
#define SOFT_RST_OUT_EN_ARMV7 0x00000001
#define SYS_SOFT_RST_ARMV7 0x00000001
#define RSTOUTn_MASK 0x8
#define SOFT_RST_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET 0xc
#define SYS_SOFT_RST 0x00000001
#endif
#define RSTOUTn_MASK_WD 0x400
#define WD_RSTOUTn_MASK 0x4
#define WD_GLOBAL_MASK 0x00000100

8
sys/arm/mv/timer.c
View File

@ -411,9 +411,9 @@ mv_watchdog_enable_armadaxp(void)
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
val = read_cpu_misc(RSTOUTn_MASK);
val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val &= ~RSTOUTn_MASK_WD;
write_cpu_misc(RSTOUTn_MASK, val);
write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
val = mv_get_timer_control();
val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
@ -451,9 +451,9 @@ mv_watchdog_disable_armadaxp(void)
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
val = read_cpu_misc(RSTOUTn_MASK);
val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val |= RSTOUTn_MASK_WD;
write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER_WD_CLR;