Make Marvell Armada reset registers usage generic
Define reset registers for both Armada38X and ArmadaXP and choose proper one during runtime based on information from FDT. Submitted by: Rafal Kozik <rk@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14745
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=332002
@ -245,9 +245,9 @@ mv_wdt_enable_armada_38x_xp_helper()
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
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val &= ~RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, val);
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write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
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}
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static void
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@ -305,9 +305,9 @@ mv_wdt_disable_armada_38x_xp_helper(void)
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
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val |= RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
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write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
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}
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static void
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@ -439,8 +439,8 @@ static void
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mv_cpu_reset(platform_t plat)
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{
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write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
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write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
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write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7);
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write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7);
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}
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#if defined(SOC_MV_ARMADA38X)
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@ -103,17 +103,15 @@
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/*
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* System reset
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*/
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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#define RSTOUTn_MASK 0x60
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#define SYSTEM_SOFT_RESET 0x64
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#define SOFT_RST_OUT_EN 0x00000001
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#define SYS_SOFT_RST 0x00000001
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#else
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#define RSTOUTn_MASK_ARMV7 0x60
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#define SYSTEM_SOFT_RESET_ARMV7 0x64
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#define SOFT_RST_OUT_EN_ARMV7 0x00000001
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#define SYS_SOFT_RST_ARMV7 0x00000001
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#define RSTOUTn_MASK 0x8
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#define SOFT_RST_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET 0xc
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#define SYS_SOFT_RST 0x00000001
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#endif
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#define RSTOUTn_MASK_WD 0x400
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#define WD_RSTOUTn_MASK 0x4
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#define WD_GLOBAL_MASK 0x00000100
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@ -411,9 +411,9 @@ mv_watchdog_enable_armadaxp(void)
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
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val &= ~RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, val);
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write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
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val = mv_get_timer_control();
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
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@ -451,9 +451,9 @@ mv_watchdog_disable_armadaxp(void)
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK);
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val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
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val |= RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
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write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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