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Sign-extend the 48-bit AMD PMC counter before treating it to a 64-bit

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2's compliment.

The 2's compliment transform is done so a "count down" sampling interval
can be converted into a "count up" PMC value. a 2's complimented 'count down'
value is written to the PMC counter; then the read-back counter is reverted
via another 2's compliment.

PR: kern/121660
Reviewed by: jkoshy
Approved by: jkoshy
MFC after: 1 week
This commit is contained in:
Adrian Chadd 2008-03-18 08:39:11 +00:00
parent 4dd3c84f5f
commit 05e486c71e
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=177344
1 changed files with 8 additions and 5 deletions
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13
sys/dev/hwpmc/hwpmc_amd.c
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@ -302,12 +302,15 @@ amd_read_pmc(int cpu, int ri, pmc_value_t *v)
#endif
tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
if (PMC_IS_SAMPLING_MODE(mode))
*v = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
else
*v = tmp;
PMCDBG(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
if (PMC_IS_SAMPLING_MODE(mode)) {
/* Sign extend 48 bit value to 64 bits. */
tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16);
tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
}
*v = tmp;
PMCDBG(MDP,REA,2,"amd-read id=%d -> %jd", ri, *v);
PMCDBG(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
return 0;
}