Rework managing hotplug commands with command completions.
Previously the command completion interrupt would post any pending command immediately before pcib_pcie_hotplug_update() had been run to inspect the current status. Now, the command completion interrupt merely clears the flag and stops the timer assuming that the caller is always going to call pcib_pcie_hotplug_update() to generate the next hotplug command if one is needed. While here, fix a bug for systems with command completion where the old (existing) value was written to the slot control register instead of the new value. This fixes the complaint about a missing hotplug interrupt on my T400. Differential Revision: https://reviews.freebsd.org/D6363
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parent
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=300074
@ -874,8 +874,11 @@ pcib_probe_hotplug(struct pcib_softc *sc)
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/*
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* Send a HotPlug command to the slot control register. If this slot
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* uses command completion interrupts, these updates will be buffered
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* while a previous command is completing.
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* uses command completion interrupts and a previous command is still
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* in progress, then the command is dropped. Once the previous
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* command completes or times out, pcib_pcie_hotplug_update() will be
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* invoked to post a new command based on the slot's state at that
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* time.
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*/
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static void
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pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
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@ -884,28 +887,20 @@ pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
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uint16_t ctl, new;
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dev = sc->dev;
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if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) {
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ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
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new = (ctl & ~mask) | val;
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if (new != ctl)
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pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
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return;
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}
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if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) {
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sc->pcie_pending_link_ctl_val &= ~mask;
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sc->pcie_pending_link_ctl_val |= val;
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sc->pcie_pending_link_ctl_mask |= mask;
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} else {
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ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
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new = (ctl & ~mask) | val;
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if (new != ctl) {
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pcie_write_config(dev, PCIER_SLOT_CTL, ctl, 2);
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sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
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if (!cold)
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callout_reset(&sc->pcie_cc_timer, hz,
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pcib_pcie_cc_timeout, sc);
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}
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if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
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return;
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ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
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new = (ctl & ~mask) | val;
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if (new == ctl)
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return;
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pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
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if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) {
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sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
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if (!cold)
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callout_reset(&sc->pcie_cc_timer, hz,
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pcib_pcie_cc_timeout, sc);
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}
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}
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@ -913,7 +908,6 @@ static void
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pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
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{
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device_t dev;
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uint16_t ctl, new;
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dev = sc->dev;
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@ -921,23 +915,8 @@ pcib_pcie_hotplug_command_completed(struct pcib_softc *sc)
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device_printf(dev, "Command Completed\n");
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if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING))
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return;
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if (sc->pcie_pending_link_ctl_mask != 0) {
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ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
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new = ctl & ~sc->pcie_pending_link_ctl_mask;
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new |= sc->pcie_pending_link_ctl_val;
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if (new != ctl) {
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pcie_write_config(dev, PCIER_SLOT_CTL, ctl, 2);
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if (!cold)
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callout_reset(&sc->pcie_cc_timer, hz,
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pcib_pcie_cc_timeout, sc);
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} else
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sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
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sc->pcie_pending_link_ctl_mask = 0;
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sc->pcie_pending_link_ctl_val = 0;
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} else {
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callout_stop(&sc->pcie_cc_timer);
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sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
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}
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callout_stop(&sc->pcie_cc_timer);
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sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING;
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}
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/*
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@ -1041,11 +1020,10 @@ pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask,
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* Interlock.
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*/
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if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) {
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mask |= PCIEM_SLOT_CTL_EIC;
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if (card_inserted !=
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!(sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS)) {
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mask |= PCIEM_SLOT_CTL_EIC;
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!(sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS))
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val |= PCIEM_SLOT_CTL_EIC;
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}
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}
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/*
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@ -134,8 +134,6 @@ struct pcib_softc
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uint16_t pcie_slot_sta;
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uint32_t pcie_link_cap;
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uint32_t pcie_slot_cap;
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uint16_t pcie_pending_link_ctl_mask;
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uint16_t pcie_pending_link_ctl_val;
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struct resource *pcie_irq;
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void *pcie_ihand;
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struct task pcie_hp_task;
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