Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
6.0.0 (branches/release_60 r324090). This introduces retpoline support, with the -mretpoline flag. The upstream initial commit message (r323155 by Chandler Carruth) contains quite a bit of explanation. Quoting: Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all shared libraries with LLD and pass `-z retpolineplt` (or use similar functionality from some other linker). We strongly recommend also using `-z now` as non-lazy binding allows the retpoline-mitigated PLT to be substantially smaller. When manually apply similar transformations to `-mretpoline` to the Linux kernel we observed very small performance hits to applications running typic al workloads, and relatively minor hits (approximately 2%) even for extremely syscall-heavy applications. This is largely due to the small number of indirect branches that occur in performance sensitive paths of the kernel. When using these patches on statically linked applications, especially C++ applications, you should expect to see a much more dramatic performance hit. For microbenchmarks that are switch, indirect-, or virtual-call heavy we have seen overheads ranging from 10% to 50%. However, real-world workloads exhibit substantially lower performance impact. Notably, techniques such as PGO and ThinLTO dramatically reduce the impact of hot indirect calls (by speculatively promoting them to direct calls) and allow optimized search trees to be used to lower switches. If you need to deploy these techniques in C++ applications, we *strongly* recommend that you ensure all hot call targets are statically linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well tuned servers using all of these techniques saw 5% - 10% overhead from the use of retpoline. We will add detailed documentation covering these components in subsequent patches, but wanted to make the core functionality available as soon as possible. Happy for more code review, but we'd really like to get these patches landed and backported ASAP for obvious reasons. We're planning to backport this to both 6.0 and 5.0 release streams and get a 5.0 release with just this cherry picked ASAP for distros and vendors. This patch is the work of a number of people over the past month: Eric, Reid, Rui, and myself. I'm mailing it out as a single commit due to the time sensitive nature of landing this and the need to backport it. Huge thanks to everyone who helped out here, and everyone at Intel who helped out in discussions about how to craft this. Also, credit goes to Paul Turner (at Google, but not an LLVM contributor) for much of the underlying retpoline design. Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41723 MFC after: 3 months X-MFC-With: r327952 PR: 224669
This commit is contained in:
Dimitry Andric
commit
07577dfe2e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=328817
@ -417,6 +417,9 @@ namespace llvm {
|
||||
// This pass expands memcmp() to load/stores.
|
||||
FunctionPass *createExpandMemCmpPass();
|
||||
|
||||
// This pass expands indirectbr instructions.
|
||||
FunctionPass *createIndirectBrExpandPass();
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
#endif
|
||||
|
||||
@ -950,6 +950,10 @@ class TargetInstrInfo : public MCInstrInfo {
|
||||
/// Return true when a target supports MachineCombiner.
|
||||
virtual bool useMachineCombiner() const { return false; }
|
||||
|
||||
/// Return true if the given SDNode can be copied during scheduling
|
||||
/// even if it has glue.
|
||||
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
|
||||
|
||||
protected:
|
||||
/// Target-dependent implementation for foldMemoryOperand.
|
||||
/// Target-independent code in foldMemoryOperand will
|
||||
|
||||
@ -800,7 +800,7 @@ class TargetLoweringBase {
|
||||
}
|
||||
|
||||
/// Return true if lowering to a jump table is allowed.
|
||||
bool areJTsAllowed(const Function *Fn) const {
|
||||
virtual bool areJTsAllowed(const Function *Fn) const {
|
||||
if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
|
||||
return false;
|
||||
|
||||
|
||||
@ -416,6 +416,13 @@ class TargetPassConfig : public ImmutablePass {
|
||||
/// immediately before machine code is emitted.
|
||||
virtual void addPreEmitPass() { }
|
||||
|
||||
/// Targets may add passes immediately before machine code is emitted in this
|
||||
/// callback. This is called even later than `addPreEmitPass`.
|
||||
// FIXME: Rename `addPreEmitPass` to something more sensible given its actual
|
||||
// position and remove the `2` suffix here as this callback is what
|
||||
// `addPreEmitPass` *should* be but in reality isn't.
|
||||
virtual void addPreEmitPass2() {}
|
||||
|
||||
/// Utilities for targets to add passes to the pass manager.
|
||||
///
|
||||
|
||||
|
||||
@ -174,6 +174,9 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
|
||||
/// \brief True if the subtarget should run the atomic expansion pass.
|
||||
virtual bool enableAtomicExpand() const;
|
||||
|
||||
/// True if the subtarget should run the indirectbr expansion pass.
|
||||
virtual bool enableIndirectBrExpand() const;
|
||||
|
||||
/// \brief Override generic scheduling policy within a region.
|
||||
///
|
||||
/// This is a convenient way for targets that don't provide any custom
|
||||
|
||||
@ -161,6 +161,7 @@ void initializeIVUsersWrapperPassPass(PassRegistry&);
|
||||
void initializeIfConverterPass(PassRegistry&);
|
||||
void initializeImplicitNullChecksPass(PassRegistry&);
|
||||
void initializeIndVarSimplifyLegacyPassPass(PassRegistry&);
|
||||
void initializeIndirectBrExpandPassPass(PassRegistry&);
|
||||
void initializeInductiveRangeCheckEliminationPass(PassRegistry&);
|
||||
void initializeInferAddressSpacesPass(PassRegistry&);
|
||||
void initializeInferFunctionAttrsLegacyPassPass(PassRegistry&);
|
||||
|
||||
@ -38,6 +38,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
|
||||
initializeGCModuleInfoPass(Registry);
|
||||
initializeIfConverterPass(Registry);
|
||||
initializeImplicitNullChecksPass(Registry);
|
||||
initializeIndirectBrExpandPassPass(Registry);
|
||||
initializeInterleavedAccessPass(Registry);
|
||||
initializeLiveDebugValuesPass(Registry);
|
||||
initializeLiveDebugVariablesPass(Registry);
|
||||
|
||||
221
contrib/llvm/lib/CodeGen/IndirectBrExpandPass.cpp
Normal file
221
contrib/llvm/lib/CodeGen/IndirectBrExpandPass.cpp
Normal file
@ -0,0 +1,221 @@
|
||||
//===- IndirectBrExpandPass.cpp - Expand indirectbr to switch -------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
/// \file
|
||||
///
|
||||
/// Implements an expansion pass to turn `indirectbr` instructions in the IR
|
||||
/// into `switch` instructions. This works by enumerating the basic blocks in
|
||||
/// a dense range of integers, replacing each `blockaddr` constant with the
|
||||
/// corresponding integer constant, and then building a switch that maps from
|
||||
/// the integers to the actual blocks. All of the indirectbr instructions in the
|
||||
/// function are redirected to this common switch.
|
||||
///
|
||||
/// While this is generically useful if a target is unable to codegen
|
||||
/// `indirectbr` natively, it is primarily useful when there is some desire to
|
||||
/// get the builtin non-jump-table lowering of a switch even when the input
|
||||
/// source contained an explicit indirect branch construct.
|
||||
///
|
||||
/// Note that it doesn't make any sense to enable this pass unless a target also
|
||||
/// disables jump-table lowering of switches. Doing that is likely to pessimize
|
||||
/// the code.
|
||||
///
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/Sequence.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/TargetPassConfig.h"
|
||||
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
||||
#include "llvm/IR/BasicBlock.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/IRBuilder.h"
|
||||
#include "llvm/IR/InstIterator.h"
|
||||
#include "llvm/IR/Instruction.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "indirectbr-expand"
|
||||
|
||||
namespace {
|
||||
|
||||
class IndirectBrExpandPass : public FunctionPass {
|
||||
const TargetLowering *TLI = nullptr;
|
||||
|
||||
public:
|
||||
static char ID; // Pass identification, replacement for typeid
|
||||
|
||||
IndirectBrExpandPass() : FunctionPass(ID) {
|
||||
initializeIndirectBrExpandPassPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
|
||||
bool runOnFunction(Function &F) override;
|
||||
};
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char IndirectBrExpandPass::ID = 0;
|
||||
|
||||
INITIALIZE_PASS(IndirectBrExpandPass, DEBUG_TYPE,
|
||||
"Expand indirectbr instructions", false, false)
|
||||
|
||||
FunctionPass *llvm::createIndirectBrExpandPass() {
|
||||
return new IndirectBrExpandPass();
|
||||
}
|
||||
|
||||
bool IndirectBrExpandPass::runOnFunction(Function &F) {
|
||||
auto &DL = F.getParent()->getDataLayout();
|
||||
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
|
||||
if (!TPC)
|
||||
return false;
|
||||
|
||||
auto &TM = TPC->getTM<TargetMachine>();
|
||||
auto &STI = *TM.getSubtargetImpl(F);
|
||||
if (!STI.enableIndirectBrExpand())
|
||||
return false;
|
||||
TLI = STI.getTargetLowering();
|
||||
|
||||
SmallVector<IndirectBrInst *, 1> IndirectBrs;
|
||||
|
||||
// Set of all potential successors for indirectbr instructions.
|
||||
SmallPtrSet<BasicBlock *, 4> IndirectBrSuccs;
|
||||
|
||||
// Build a list of indirectbrs that we want to rewrite.
|
||||
for (BasicBlock &BB : F)
|
||||
if (auto *IBr = dyn_cast<IndirectBrInst>(BB.getTerminator())) {
|
||||
// Handle the degenerate case of no successors by replacing the indirectbr
|
||||
// with unreachable as there is no successor available.
|
||||
if (IBr->getNumSuccessors() == 0) {
|
||||
(void)new UnreachableInst(F.getContext(), IBr);
|
||||
IBr->eraseFromParent();
|
||||
continue;
|
||||
}
|
||||
|
||||
IndirectBrs.push_back(IBr);
|
||||
for (BasicBlock *SuccBB : IBr->successors())
|
||||
IndirectBrSuccs.insert(SuccBB);
|
||||
}
|
||||
|
||||
if (IndirectBrs.empty())
|
||||
return false;
|
||||
|
||||
// If we need to replace any indirectbrs we need to establish integer
|
||||
// constants that will correspond to each of the basic blocks in the function
|
||||
// whose address escapes. We do that here and rewrite all the blockaddress
|
||||
// constants to just be those integer constants cast to a pointer type.
|
||||
SmallVector<BasicBlock *, 4> BBs;
|
||||
|
||||
for (BasicBlock &BB : F) {
|
||||
// Skip blocks that aren't successors to an indirectbr we're going to
|
||||
// rewrite.
|
||||
if (!IndirectBrSuccs.count(&BB))
|
||||
continue;
|
||||
|
||||
auto IsBlockAddressUse = [&](const Use &U) {
|
||||
return isa<BlockAddress>(U.getUser());
|
||||
};
|
||||
auto BlockAddressUseIt = llvm::find_if(BB.uses(), IsBlockAddressUse);
|
||||
if (BlockAddressUseIt == BB.use_end())
|
||||
continue;
|
||||
|
||||
assert(std::find_if(std::next(BlockAddressUseIt), BB.use_end(),
|
||||
IsBlockAddressUse) == BB.use_end() &&
|
||||
"There should only ever be a single blockaddress use because it is "
|
||||
"a constant and should be uniqued.");
|
||||
|
||||
auto *BA = cast<BlockAddress>(BlockAddressUseIt->getUser());
|
||||
|
||||
// Skip if the constant was formed but ended up not being used (due to DCE
|
||||
// or whatever).
|
||||
if (!BA->isConstantUsed())
|
||||
continue;
|
||||
|
||||
// Compute the index we want to use for this basic block. We can't use zero
|
||||
// because null can be compared with block addresses.
|
||||
int BBIndex = BBs.size() + 1;
|
||||
BBs.push_back(&BB);
|
||||
|
||||
auto *ITy = cast<IntegerType>(DL.getIntPtrType(BA->getType()));
|
||||
ConstantInt *BBIndexC = ConstantInt::get(ITy, BBIndex);
|
||||
|
||||
// Now rewrite the blockaddress to an integer constant based on the index.
|
||||
// FIXME: We could potentially preserve the uses as arguments to inline asm.
|
||||
// This would allow some uses such as diagnostic information in crashes to
|
||||
// have higher quality even when this transform is enabled, but would break
|
||||
// users that round-trip blockaddresses through inline assembly and then
|
||||
// back into an indirectbr.
|
||||
BA->replaceAllUsesWith(ConstantExpr::getIntToPtr(BBIndexC, BA->getType()));
|
||||
}
|
||||
|
||||
if (BBs.empty()) {
|
||||
// There are no blocks whose address is taken, so any indirectbr instruction
|
||||
// cannot get a valid input and we can replace all of them with unreachable.
|
||||
for (auto *IBr : IndirectBrs) {
|
||||
(void)new UnreachableInst(F.getContext(), IBr);
|
||||
IBr->eraseFromParent();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
BasicBlock *SwitchBB;
|
||||
Value *SwitchValue;
|
||||
|
||||
// Compute a common integer type across all the indirectbr instructions.
|
||||
IntegerType *CommonITy = nullptr;
|
||||
for (auto *IBr : IndirectBrs) {
|
||||
auto *ITy =
|
||||
cast<IntegerType>(DL.getIntPtrType(IBr->getAddress()->getType()));
|
||||
if (!CommonITy || ITy->getBitWidth() > CommonITy->getBitWidth())
|
||||
CommonITy = ITy;
|
||||
}
|
||||
|
||||
auto GetSwitchValue = [DL, CommonITy](IndirectBrInst *IBr) {
|
||||
return CastInst::CreatePointerCast(
|
||||
IBr->getAddress(), CommonITy,
|
||||
Twine(IBr->getAddress()->getName()) + ".switch_cast", IBr);
|
||||
};
|
||||
|
||||
if (IndirectBrs.size() == 1) {
|
||||
// If we only have one indirectbr, we can just directly replace it within
|
||||
// its block.
|
||||
SwitchBB = IndirectBrs[0]->getParent();
|
||||
SwitchValue = GetSwitchValue(IndirectBrs[0]);
|
||||
IndirectBrs[0]->eraseFromParent();
|
||||
} else {
|
||||
// Otherwise we need to create a new block to hold the switch across BBs,
|
||||
// jump to that block instead of each indirectbr, and phi together the
|
||||
// values for the switch.
|
||||
SwitchBB = BasicBlock::Create(F.getContext(), "switch_bb", &F);
|
||||
auto *SwitchPN = PHINode::Create(CommonITy, IndirectBrs.size(),
|
||||
"switch_value_phi", SwitchBB);
|
||||
SwitchValue = SwitchPN;
|
||||
|
||||
// Now replace the indirectbr instructions with direct branches to the
|
||||
// switch block and fill out the PHI operands.
|
||||
for (auto *IBr : IndirectBrs) {
|
||||
SwitchPN->addIncoming(GetSwitchValue(IBr), IBr->getParent());
|
||||
BranchInst::Create(SwitchBB, IBr);
|
||||
IBr->eraseFromParent();
|
||||
}
|
||||
}
|
||||
|
||||
// Now build the switch in the block. The block will have no terminator
|
||||
// already.
|
||||
auto *SI = SwitchInst::Create(SwitchValue, BBs[0], BBs.size(), SwitchBB);
|
||||
|
||||
// Add a case for each block.
|
||||
for (int i : llvm::seq<int>(1, BBs.size()))
|
||||
SI->addCase(ConstantInt::get(CommonITy, i + 1), BBs[i]);
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -1996,14 +1996,15 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
|
||||
Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
|
||||
Entry.Node = Op;
|
||||
Entry.Ty = ArgTy;
|
||||
Entry.IsSExt = isSigned;
|
||||
Entry.IsZExt = !isSigned;
|
||||
Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
|
||||
Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
|
||||
Args.push_back(Entry);
|
||||
}
|
||||
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
|
||||
TLI.getPointerTy(DAG.getDataLayout()));
|
||||
|
||||
Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
|
||||
EVT RetVT = Node->getValueType(0);
|
||||
Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
|
||||
|
||||
// By default, the input chain to this libcall is the entry node of the
|
||||
// function. If the libcall is going to be emitted as a tail call then
|
||||
@ -2022,13 +2023,14 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
|
||||
InChain = TCChain;
|
||||
|
||||
TargetLowering::CallLoweringInfo CLI(DAG);
|
||||
bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
|
||||
CLI.setDebugLoc(SDLoc(Node))
|
||||
.setChain(InChain)
|
||||
.setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
|
||||
std::move(Args))
|
||||
.setTailCall(isTailCall)
|
||||
.setSExtResult(isSigned)
|
||||
.setZExtResult(!isSigned)
|
||||
.setSExtResult(signExtend)
|
||||
.setZExtResult(!signExtend)
|
||||
.setIsPostTypeLegalization(true);
|
||||
|
||||
std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
|
||||
|
||||
@ -1117,22 +1117,34 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
|
||||
if (!N)
|
||||
return nullptr;
|
||||
|
||||
if (SU->getNode()->getGluedNode())
|
||||
DEBUG(dbgs() << "Considering duplicating the SU\n");
|
||||
DEBUG(SU->dump(this));
|
||||
|
||||
if (N->getGluedNode() &&
|
||||
!TII->canCopyGluedNodeDuringSchedule(N)) {
|
||||
DEBUG(dbgs()
|
||||
<< "Giving up because it has incoming glue and the target does not "
|
||||
"want to copy it\n");
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
SUnit *NewSU;
|
||||
bool TryUnfold = false;
|
||||
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
|
||||
MVT VT = N->getSimpleValueType(i);
|
||||
if (VT == MVT::Glue)
|
||||
if (VT == MVT::Glue) {
|
||||
DEBUG(dbgs() << "Giving up because it has outgoing glue\n");
|
||||
return nullptr;
|
||||
else if (VT == MVT::Other)
|
||||
} else if (VT == MVT::Other)
|
||||
TryUnfold = true;
|
||||
}
|
||||
for (const SDValue &Op : N->op_values()) {
|
||||
MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
|
||||
if (VT == MVT::Glue)
|
||||
if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) {
|
||||
DEBUG(dbgs() << "Giving up because it one of the operands is glue and "
|
||||
"the target does not want to copy it\n");
|
||||
return nullptr;
|
||||
}
|
||||
}
|
||||
|
||||
// If possible unfold instruction.
|
||||
|
||||
@ -907,6 +907,9 @@ void TargetPassConfig::addMachinePasses() {
|
||||
if (EnableMachineOutliner)
|
||||
PM->add(createMachineOutlinerPass(EnableLinkOnceODROutlining));
|
||||
|
||||
// Add passes that directly emit MI after all other MI passes.
|
||||
addPreEmitPass2();
|
||||
|
||||
AddingMachinePasses = false;
|
||||
}
|
||||
|
||||
|
||||
@ -38,6 +38,10 @@ bool TargetSubtargetInfo::enableAtomicExpand() const {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool TargetSubtargetInfo::enableIndirectBrExpand() const {
|
||||
return false;
|
||||
}
|
||||
|
||||
bool TargetSubtargetInfo::enableMachineScheduler() const {
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -3756,36 +3756,45 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
|
||||
// FIXME: This isn't safe because the addressing mode doesn't work
|
||||
// correctly if vaddr is negative.
|
||||
//
|
||||
// FIXME: Handle v_add_u32 and VOP3 form. Also don't rely on immediate
|
||||
// being in src0.
|
||||
//
|
||||
// FIXME: Should probably be done somewhere else, maybe SIFoldOperands.
|
||||
//
|
||||
// See if we can extract an immediate offset by recognizing one of these:
|
||||
// V_ADD_I32_e32 dst, imm, src1
|
||||
// V_ADD_I32_e32 dst, (S_MOV_B32 imm), src1
|
||||
// V_ADD will be removed by "Remove dead machine instructions".
|
||||
if (Add && Add->getOpcode() == AMDGPU::V_ADD_I32_e32) {
|
||||
const MachineOperand *Src =
|
||||
getNamedOperand(*Add, AMDGPU::OpName::src0);
|
||||
if (Add &&
|
||||
(Add->getOpcode() == AMDGPU::V_ADD_I32_e32 ||
|
||||
Add->getOpcode() == AMDGPU::V_ADD_U32_e64)) {
|
||||
static const unsigned SrcNames[2] = {
|
||||
AMDGPU::OpName::src0,
|
||||
AMDGPU::OpName::src1,
|
||||
};
|
||||
|
||||
if (Src->isReg()) {
|
||||
auto Mov = MRI.getUniqueVRegDef(Src->getReg());
|
||||
if (Mov && Mov->getOpcode() == AMDGPU::S_MOV_B32)
|
||||
Src = &Mov->getOperand(1);
|
||||
}
|
||||
// Find a literal offset in one of source operands.
|
||||
for (int i = 0; i < 2; i++) {
|
||||
const MachineOperand *Src =
|
||||
getNamedOperand(*Add, SrcNames[i]);
|
||||
|
||||
if (Src) {
|
||||
if (Src->isImm())
|
||||
Offset = Src->getImm();
|
||||
else if (Src->isCImm())
|
||||
Offset = Src->getCImm()->getZExtValue();
|
||||
}
|
||||
if (Src->isReg()) {
|
||||
auto Mov = MRI.getUniqueVRegDef(Src->getReg());
|
||||
if (Mov && Mov->getOpcode() == AMDGPU::S_MOV_B32)
|
||||
Src = &Mov->getOperand(1);
|
||||
}
|
||||
|
||||
if (Src) {
|
||||
if (Src->isImm())
|
||||
Offset = Src->getImm();
|
||||
else if (Src->isCImm())
|
||||
Offset = Src->getCImm()->getZExtValue();
|
||||
}
|
||||
|
||||
if (Offset && isLegalMUBUFImmOffset(Offset)) {
|
||||
VAddr = getNamedOperand(*Add, SrcNames[!i]);
|
||||
break;
|
||||
}
|
||||
|
||||
if (Offset && isLegalMUBUFImmOffset(Offset))
|
||||
VAddr = getNamedOperand(*Add, AMDGPU::OpName::src1);
|
||||
else
|
||||
Offset = 0;
|
||||
}
|
||||
}
|
||||
|
||||
BuildMI(*MBB, Inst, Inst.getDebugLoc(),
|
||||
|
||||
@ -141,3 +141,16 @@ void Thumb1InstrInfo::expandLoadStackGuard(
|
||||
else
|
||||
expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);
|
||||
}
|
||||
|
||||
bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const {
|
||||
// In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
|
||||
// but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
|
||||
// even if they have glue.
|
||||
// FIXME. Actually implement the cross-copy where it is possible (post v6)
|
||||
// because these copies entail more spilling.
|
||||
unsigned Opcode = N->getMachineOpcode();
|
||||
if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -53,6 +53,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override;
|
||||
private:
|
||||
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
|
||||
};
|
||||
|
||||
@ -3507,10 +3507,9 @@ MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
|
||||
|
||||
bool
|
||||
MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
|
||||
if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
|
||||
if (Type == MVT::i32)
|
||||
if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
|
||||
return true;
|
||||
}
|
||||
|
||||
return IsSigned;
|
||||
}
|
||||
|
||||
|
||||
@ -136,6 +136,13 @@ IsGlobalInSmallSectionImpl(const GlobalObject *GO,
|
||||
return false;
|
||||
|
||||
Type *Ty = GVA->getValueType();
|
||||
|
||||
// It is possible that the type of the global is unsized, i.e. a declaration
|
||||
// of a extern struct. In this case don't presume it is in the small data
|
||||
// section. This happens e.g. when building the FreeBSD kernel.
|
||||
if (!Ty->isSized())
|
||||
return false;
|
||||
|
||||
return IsInSmallSection(
|
||||
GVA->getParent()->getDataLayout().getTypeAllocSize(Ty));
|
||||
}
|
||||
|
||||
@ -88,10 +88,11 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
|
||||
|
||||
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
|
||||
MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
|
||||
const SparcInstrInfo &TII =
|
||||
*static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
|
||||
*static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo());
|
||||
const SparcRegisterInfo &RegInfo =
|
||||
*static_cast<const SparcRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
|
||||
*static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo());
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
// Debug location must be unknown since the first debug location is used
|
||||
// to determine the end of the prologue.
|
||||
@ -141,7 +142,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
|
||||
|
||||
// Adds the SPARC subtarget-specific spill area to the stack
|
||||
// size. Also ensures target-required alignment.
|
||||
NumBytes = MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes);
|
||||
NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
|
||||
|
||||
// Finally, ensure that the size is sufficiently aligned for the
|
||||
// data on the stack.
|
||||
@ -176,9 +177,27 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
|
||||
.addCFIIndex(CFIIndex);
|
||||
|
||||
if (NeedsStackRealignment) {
|
||||
// andn %o6, MaxAlign-1, %o6
|
||||
int64_t Bias = Subtarget.getStackPointerBias();
|
||||
unsigned regUnbiased;
|
||||
if (Bias) {
|
||||
// This clobbers G1 which we always know is available here.
|
||||
regUnbiased = SP::G1;
|
||||
// add %o6, BIAS, %g1
|
||||
BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
|
||||
.addReg(SP::O6).addImm(Bias);
|
||||
} else
|
||||
regUnbiased = SP::O6;
|
||||
|
||||
// andn %regUnbiased, MaxAlign-1, %regUnbiased
|
||||
int MaxAlign = MFI.getMaxAlignment();
|
||||
BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1);
|
||||
BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
|
||||
.addReg(regUnbiased).addImm(MaxAlign - 1);
|
||||
|
||||
if (Bias) {
|
||||
// add %g1, -BIAS, %o6
|
||||
BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
|
||||
.addReg(regUnbiased).addImm(-Bias);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -22,6 +22,7 @@ namespace llvm {
|
||||
class FunctionPass;
|
||||
class ImmutablePass;
|
||||
class InstructionSelector;
|
||||
class ModulePass;
|
||||
class PassRegistry;
|
||||
class X86RegisterBankInfo;
|
||||
class X86Subtarget;
|
||||
@ -102,6 +103,9 @@ void initializeFixupBWInstPassPass(PassRegistry &);
|
||||
/// encoding when possible in order to reduce code size.
|
||||
FunctionPass *createX86EvexToVexInsts();
|
||||
|
||||
/// This pass creates the thunks for the retpoline feature.
|
||||
FunctionPass *createX86RetpolineThunksPass();
|
||||
|
||||
InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
|
||||
X86Subtarget &,
|
||||
X86RegisterBankInfo &);
|
||||
|
||||
@ -329,6 +329,27 @@ def FeatureHasFastGather
|
||||
: SubtargetFeature<"fast-gather", "HasFastGather", "true",
|
||||
"Indicates if gather is reasonably fast.">;
|
||||
|
||||
// Enable mitigation of some aspects of speculative execution related
|
||||
// vulnerabilities by removing speculatable indirect branches. This disables
|
||||
// jump-table formation, rewrites explicit `indirectbr` instructions into
|
||||
// `switch` instructions, and uses a special construct called a "retpoline" to
|
||||
// prevent speculation of the remaining indirect branches (indirect calls and
|
||||
// tail calls).
|
||||
def FeatureRetpoline
|
||||
: SubtargetFeature<"retpoline", "UseRetpoline", "true",
|
||||
"Remove speculation of indirect branches from the "
|
||||
"generated code, either by avoiding them entirely or "
|
||||
"lowering them with a speculation blocking construct.">;
|
||||
|
||||
// Rely on external thunks for the emitted retpoline calls. This allows users
|
||||
// to provide their own custom thunk definitions in highly specialized
|
||||
// environments such as a kernel that does boot-time hot patching.
|
||||
def FeatureRetpolineExternalThunk
|
||||
: SubtargetFeature<
|
||||
"retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
|
||||
"Enable retpoline, but with an externally provided thunk.",
|
||||
[FeatureRetpoline]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register File Description
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -32,6 +32,7 @@ class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
|
||||
FaultMaps FM;
|
||||
std::unique_ptr<MCCodeEmitter> CodeEmitter;
|
||||
bool EmitFPOData = false;
|
||||
bool NeedsRetpoline = false;
|
||||
|
||||
// This utility class tracks the length of a stackmap instruction's 'shadow'.
|
||||
// It is used by the X86AsmPrinter to ensure that the stackmap shadow
|
||||
|
||||
@ -3172,6 +3172,10 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
|
||||
(CalledFn && CalledFn->hasFnAttribute("no_caller_saved_registers")))
|
||||
return false;
|
||||
|
||||
// Functions using retpoline should use SDISel for calls.
|
||||
if (Subtarget->useRetpoline())
|
||||
return false;
|
||||
|
||||
// Handle only C, fastcc, and webkit_js calling conventions for now.
|
||||
switch (CC) {
|
||||
default: return false;
|
||||
|
||||
@ -741,6 +741,11 @@ void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
|
||||
bool InProlog) const {
|
||||
bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
|
||||
|
||||
// FIXME: Add retpoline support and remove this.
|
||||
if (Is64Bit && IsLargeCodeModel && STI.useRetpoline())
|
||||
report_fatal_error("Emitting stack probe calls on 64-bit with the large "
|
||||
"code model and retpoline not yet implemented.");
|
||||
|
||||
unsigned CallOp;
|
||||
if (Is64Bit)
|
||||
CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
|
||||
@ -2345,6 +2350,10 @@ void X86FrameLowering::adjustForSegmentedStacks(
|
||||
// This solution is not perfect, as it assumes that the .rodata section
|
||||
// is laid out within 2^31 bytes of each function body, but this seems
|
||||
// to be sufficient for JIT.
|
||||
// FIXME: Add retpoline support and remove the error here..
|
||||
if (STI.useRetpoline())
|
||||
report_fatal_error("Emitting morestack calls on 64-bit with the large "
|
||||
"code model and retpoline not yet implemented.");
|
||||
BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
|
||||
.addReg(X86::RIP)
|
||||
.addImm(0)
|
||||
|
||||
@ -629,11 +629,11 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
|
||||
SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
|
||||
|
||||
if (OptLevel != CodeGenOpt::None &&
|
||||
// Only does this when target favors doesn't favor register indirect
|
||||
// call.
|
||||
// Only do this when the target can fold the load into the call or
|
||||
// jmp.
|
||||
!Subtarget->useRetpoline() &&
|
||||
((N->getOpcode() == X86ISD::CALL && !Subtarget->slowTwoMemOps()) ||
|
||||
(N->getOpcode() == X86ISD::TC_RETURN &&
|
||||
// Only does this if load can be folded into TC_RETURN.
|
||||
(Subtarget->is64Bit() ||
|
||||
!getTargetMachine().isPositionIndependent())))) {
|
||||
/// Also try moving call address load from outside callseq_start to just
|
||||
|
||||
@ -25767,6 +25767,15 @@ X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
||||
return isShuffleMaskLegal(Mask, VT);
|
||||
}
|
||||
|
||||
bool X86TargetLowering::areJTsAllowed(const Function *Fn) const {
|
||||
// If the subtarget is using retpolines, we need to not generate jump tables.
|
||||
if (Subtarget.useRetpoline())
|
||||
return false;
|
||||
|
||||
// Otherwise, fallback on the generic logic.
|
||||
return TargetLowering::areJTsAllowed(Fn);
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86 Scheduler Hooks
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -27069,6 +27078,115 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr &MI,
|
||||
return BB;
|
||||
}
|
||||
|
||||
static unsigned getOpcodeForRetpoline(unsigned RPOpc) {
|
||||
switch (RPOpc) {
|
||||
case X86::RETPOLINE_CALL32:
|
||||
return X86::CALLpcrel32;
|
||||
case X86::RETPOLINE_CALL64:
|
||||
return X86::CALL64pcrel32;
|
||||
case X86::RETPOLINE_TCRETURN32:
|
||||
return X86::TCRETURNdi;
|
||||
case X86::RETPOLINE_TCRETURN64:
|
||||
return X86::TCRETURNdi64;
|
||||
}
|
||||
llvm_unreachable("not retpoline opcode");
|
||||
}
|
||||
|
||||
static const char *getRetpolineSymbol(const X86Subtarget &Subtarget,
|
||||
unsigned Reg) {
|
||||
switch (Reg) {
|
||||
case 0:
|
||||
assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
|
||||
return Subtarget.useRetpolineExternalThunk()
|
||||
? "__llvm_external_retpoline_push"
|
||||
: "__llvm_retpoline_push";
|
||||
case X86::EAX:
|
||||
return Subtarget.useRetpolineExternalThunk()
|
||||
? "__llvm_external_retpoline_eax"
|
||||
: "__llvm_retpoline_eax";
|
||||
case X86::ECX:
|
||||
return Subtarget.useRetpolineExternalThunk()
|
||||
? "__llvm_external_retpoline_ecx"
|
||||
: "__llvm_retpoline_ecx";
|
||||
case X86::EDX:
|
||||
return Subtarget.useRetpolineExternalThunk()
|
||||
? "__llvm_external_retpoline_edx"
|
||||
: "__llvm_retpoline_edx";
|
||||
case X86::R11:
|
||||
return Subtarget.useRetpolineExternalThunk()
|
||||
? "__llvm_external_retpoline_r11"
|
||||
: "__llvm_retpoline_r11";
|
||||
}
|
||||
llvm_unreachable("unexpected reg for retpoline");
|
||||
}
|
||||
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitLoweredRetpoline(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
// Copy the virtual register into the R11 physical register and
|
||||
// call the retpoline thunk.
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
const X86InstrInfo *TII = Subtarget.getInstrInfo();
|
||||
unsigned CalleeVReg = MI.getOperand(0).getReg();
|
||||
unsigned Opc = getOpcodeForRetpoline(MI.getOpcode());
|
||||
|
||||
// Find an available scratch register to hold the callee. On 64-bit, we can
|
||||
// just use R11, but we scan for uses anyway to ensure we don't generate
|
||||
// incorrect code. On 32-bit, we use one of EAX, ECX, or EDX that isn't
|
||||
// already a register use operand to the call to hold the callee. If none
|
||||
// are available, push the callee instead. This is less efficient, but is
|
||||
// necessary for functions using 3 regparms. Such function calls are
|
||||
// (currently) not eligible for tail call optimization, because there is no
|
||||
// scratch register available to hold the address of the callee.
|
||||
SmallVector<unsigned, 3> AvailableRegs;
|
||||
if (Subtarget.is64Bit())
|
||||
AvailableRegs.push_back(X86::R11);
|
||||
else
|
||||
AvailableRegs.append({X86::EAX, X86::ECX, X86::EDX});
|
||||
|
||||
// Zero out any registers that are already used.
|
||||
for (const auto &MO : MI.operands()) {
|
||||
if (MO.isReg() && MO.isUse())
|
||||
for (unsigned &Reg : AvailableRegs)
|
||||
if (Reg == MO.getReg())
|
||||
Reg = 0;
|
||||
}
|
||||
|
||||
// Choose the first remaining non-zero available register.
|
||||
unsigned AvailableReg = 0;
|
||||
for (unsigned MaybeReg : AvailableRegs) {
|
||||
if (MaybeReg) {
|
||||
AvailableReg = MaybeReg;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
const char *Symbol = getRetpolineSymbol(Subtarget, AvailableReg);
|
||||
|
||||
if (AvailableReg == 0) {
|
||||
// No register available. Use PUSH. This must not be a tailcall, and this
|
||||
// must not be x64.
|
||||
if (Subtarget.is64Bit())
|
||||
report_fatal_error(
|
||||
"Cannot make an indirect call on x86-64 using both retpoline and a "
|
||||
"calling convention that preservers r11");
|
||||
if (Opc != X86::CALLpcrel32)
|
||||
report_fatal_error("Cannot make an indirect tail call on x86 using "
|
||||
"retpoline without a preserved register");
|
||||
BuildMI(*BB, MI, DL, TII->get(X86::PUSH32r)).addReg(CalleeVReg);
|
||||
MI.getOperand(0).ChangeToES(Symbol);
|
||||
MI.setDesc(TII->get(Opc));
|
||||
} else {
|
||||
BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), AvailableReg)
|
||||
.addReg(CalleeVReg);
|
||||
MI.getOperand(0).ChangeToES(Symbol);
|
||||
MI.setDesc(TII->get(Opc));
|
||||
MachineInstrBuilder(*BB->getParent(), &MI)
|
||||
.addReg(AvailableReg, RegState::Implicit | RegState::Kill);
|
||||
}
|
||||
return BB;
|
||||
}
|
||||
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
|
||||
MachineBasicBlock *MBB) const {
|
||||
@ -27584,6 +27702,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
||||
case X86::TLS_base_addr32:
|
||||
case X86::TLS_base_addr64:
|
||||
return EmitLoweredTLSAddr(MI, BB);
|
||||
case X86::RETPOLINE_CALL32:
|
||||
case X86::RETPOLINE_CALL64:
|
||||
case X86::RETPOLINE_TCRETURN32:
|
||||
case X86::RETPOLINE_TCRETURN64:
|
||||
return EmitLoweredRetpoline(MI, BB);
|
||||
case X86::CATCHRET:
|
||||
return EmitLoweredCatchRet(MI, BB);
|
||||
case X86::CATCHPAD:
|
||||
|
||||
@ -982,6 +982,9 @@ namespace llvm {
|
||||
bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
||||
EVT VT) const override;
|
||||
|
||||
/// Returns true if lowering to a jump table is allowed.
|
||||
bool areJTsAllowed(const Function *Fn) const override;
|
||||
|
||||
/// If true, then instruction selection should
|
||||
/// seek to shrink the FP constant of the specified type to a smaller type
|
||||
/// in order to save space and / or reduce runtime.
|
||||
@ -1294,6 +1297,9 @@ namespace llvm {
|
||||
MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
|
||||
MachineBasicBlock *EmitLoweredRetpoline(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
|
||||
MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
|
||||
MachineBasicBlock *MBB) const;
|
||||
|
||||
|
||||
@ -1146,14 +1146,14 @@ def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
|
||||
|
||||
def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
|
||||
(TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
|
||||
Requires<[Not64BitMode]>;
|
||||
Requires<[Not64BitMode, NotUseRetpoline]>;
|
||||
|
||||
// FIXME: This is disabled for 32-bit PIC mode because the global base
|
||||
// register which is part of the address mode may be assigned a
|
||||
// callee-saved register.
|
||||
def : Pat<(X86tcret (load addr:$dst), imm:$off),
|
||||
(TCRETURNmi addr:$dst, imm:$off)>,
|
||||
Requires<[Not64BitMode, IsNotPIC]>;
|
||||
Requires<[Not64BitMode, IsNotPIC, NotUseRetpoline]>;
|
||||
|
||||
def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
|
||||
(TCRETURNdi tglobaladdr:$dst, imm:$off)>,
|
||||
@ -1165,13 +1165,21 @@ def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
|
||||
|
||||
def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
|
||||
(TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
|
||||
Requires<[In64BitMode]>;
|
||||
Requires<[In64BitMode, NotUseRetpoline]>;
|
||||
|
||||
// Don't fold loads into X86tcret requiring more than 6 regs.
|
||||
// There wouldn't be enough scratch registers for base+index.
|
||||
def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
|
||||
(TCRETURNmi64 addr:$dst, imm:$off)>,
|
||||
Requires<[In64BitMode]>;
|
||||
Requires<[In64BitMode, NotUseRetpoline]>;
|
||||
|
||||
def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
|
||||
(RETPOLINE_TCRETURN64 ptr_rc_tailcall:$dst, imm:$off)>,
|
||||
Requires<[In64BitMode, UseRetpoline]>;
|
||||
|
||||
def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
|
||||
(RETPOLINE_TCRETURN32 ptr_rc_tailcall:$dst, imm:$off)>,
|
||||
Requires<[Not64BitMode, UseRetpoline]>;
|
||||
|
||||
def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
|
||||
(TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
|
||||
|
||||
@ -211,11 +211,12 @@ let isCall = 1 in
|
||||
Sched<[WriteJumpLd]>;
|
||||
def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
|
||||
"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
|
||||
OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
|
||||
OpSize32, Requires<[Not64BitMode,NotUseRetpoline]>,
|
||||
Sched<[WriteJump]>;
|
||||
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
|
||||
"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
|
||||
IIC_CALL_MEM>, OpSize32,
|
||||
Requires<[Not64BitMode,FavorMemIndirectCall]>,
|
||||
Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>,
|
||||
Sched<[WriteJumpLd]>;
|
||||
|
||||
let Predicates = [Not64BitMode] in {
|
||||
@ -298,11 +299,12 @@ let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
|
||||
def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
|
||||
"call{q}\t{*}$dst", [(X86call GR64:$dst)],
|
||||
IIC_CALL_RI>,
|
||||
Requires<[In64BitMode]>;
|
||||
Requires<[In64BitMode,NotUseRetpoline]>;
|
||||
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
|
||||
"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
|
||||
IIC_CALL_MEM>,
|
||||
Requires<[In64BitMode,FavorMemIndirectCall]>;
|
||||
Requires<[In64BitMode,FavorMemIndirectCall,
|
||||
NotUseRetpoline]>;
|
||||
|
||||
def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
|
||||
"lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
|
||||
@ -341,6 +343,27 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
|
||||
}
|
||||
}
|
||||
|
||||
let isPseudo = 1, isCall = 1, isCodeGenOnly = 1,
|
||||
Uses = [RSP, SSP],
|
||||
usesCustomInserter = 1,
|
||||
SchedRW = [WriteJump] in {
|
||||
def RETPOLINE_CALL32 :
|
||||
PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>,
|
||||
Requires<[Not64BitMode,UseRetpoline]>;
|
||||
|
||||
def RETPOLINE_CALL64 :
|
||||
PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>,
|
||||
Requires<[In64BitMode,UseRetpoline]>;
|
||||
|
||||
// Retpoline variant of indirect tail calls.
|
||||
let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
|
||||
def RETPOLINE_TCRETURN64 :
|
||||
PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>;
|
||||
def RETPOLINE_TCRETURN32 :
|
||||
PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>;
|
||||
}
|
||||
}
|
||||
|
||||
// Conditional tail calls are similar to the above, but they are branches
|
||||
// rather than barriers, and they use EFLAGS.
|
||||
let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
|
||||
|
||||
@ -938,6 +938,8 @@ def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">;
|
||||
def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">;
|
||||
def HasERMSB : Predicate<"Subtarget->hasERMSB()">;
|
||||
def HasMFence : Predicate<"Subtarget->hasMFence()">;
|
||||
def UseRetpoline : Predicate<"Subtarget->useRetpoline()">;
|
||||
def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86 Instruction Format Definitions.
|
||||
|
||||
@ -874,6 +874,10 @@ void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
|
||||
// address is to far away. (TODO: support non-relative addressing)
|
||||
break;
|
||||
case MachineOperand::MO_Register:
|
||||
// FIXME: Add retpoline support and remove this.
|
||||
if (Subtarget->useRetpoline())
|
||||
report_fatal_error("Lowering register statepoints with retpoline not "
|
||||
"yet implemented.");
|
||||
CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
|
||||
CallOpcode = X86::CALL64r;
|
||||
break;
|
||||
@ -1028,6 +1032,10 @@ void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
|
||||
|
||||
EmitAndCountInstruction(
|
||||
MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
|
||||
// FIXME: Add retpoline support and remove this.
|
||||
if (Subtarget->useRetpoline())
|
||||
report_fatal_error(
|
||||
"Lowering patchpoint with retpoline not yet implemented.");
|
||||
EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
|
||||
}
|
||||
|
||||
|
||||
311
contrib/llvm/lib/Target/X86/X86RetpolineThunks.cpp
Normal file
311
contrib/llvm/lib/Target/X86/X86RetpolineThunks.cpp
Normal file
@ -0,0 +1,311 @@
|
||||
//======- X86RetpolineThunks.cpp - Construct retpoline thunks for x86 --=====//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
/// \file
|
||||
///
|
||||
/// Pass that injects an MI thunk implementing a "retpoline". This is
|
||||
/// a RET-implemented trampoline that is used to lower indirect calls in a way
|
||||
/// that prevents speculation on some x86 processors and can be used to mitigate
|
||||
/// security vulnerabilities due to targeted speculative execution and side
|
||||
/// channels such as CVE-2017-5715.
|
||||
///
|
||||
/// TODO(chandlerc): All of this code could use better comments and
|
||||
/// documentation.
|
||||
///
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "X86.h"
|
||||
#include "X86InstrBuilder.h"
|
||||
#include "X86Subtarget.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineModuleInfo.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/CodeGen/TargetPassConfig.h"
|
||||
#include "llvm/IR/IRBuilder.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/IR/Module.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "x86-retpoline-thunks"
|
||||
|
||||
static const char ThunkNamePrefix[] = "__llvm_retpoline_";
|
||||
static const char R11ThunkName[] = "__llvm_retpoline_r11";
|
||||
static const char EAXThunkName[] = "__llvm_retpoline_eax";
|
||||
static const char ECXThunkName[] = "__llvm_retpoline_ecx";
|
||||
static const char EDXThunkName[] = "__llvm_retpoline_edx";
|
||||
static const char PushThunkName[] = "__llvm_retpoline_push";
|
||||
|
||||
namespace {
|
||||
class X86RetpolineThunks : public MachineFunctionPass {
|
||||
public:
|
||||
static char ID;
|
||||
|
||||
X86RetpolineThunks() : MachineFunctionPass(ID) {}
|
||||
|
||||
StringRef getPassName() const override { return "X86 Retpoline Thunks"; }
|
||||
|
||||
bool doInitialization(Module &M) override;
|
||||
bool runOnMachineFunction(MachineFunction &F) override;
|
||||
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
AU.addRequired<MachineModuleInfo>();
|
||||
AU.addPreserved<MachineModuleInfo>();
|
||||
}
|
||||
|
||||
private:
|
||||
MachineModuleInfo *MMI;
|
||||
const TargetMachine *TM;
|
||||
bool Is64Bit;
|
||||
const X86Subtarget *STI;
|
||||
const X86InstrInfo *TII;
|
||||
|
||||
bool InsertedThunks;
|
||||
|
||||
void createThunkFunction(Module &M, StringRef Name);
|
||||
void insertRegReturnAddrClobber(MachineBasicBlock &MBB, unsigned Reg);
|
||||
void insert32BitPushReturnAddrClobber(MachineBasicBlock &MBB);
|
||||
void populateThunk(MachineFunction &MF, Optional<unsigned> Reg = None);
|
||||
};
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
FunctionPass *llvm::createX86RetpolineThunksPass() {
|
||||
return new X86RetpolineThunks();
|
||||
}
|
||||
|
||||
char X86RetpolineThunks::ID = 0;
|
||||
|
||||
bool X86RetpolineThunks::doInitialization(Module &M) {
|
||||
InsertedThunks = false;
|
||||
return false;
|
||||
}
|
||||
|
||||
bool X86RetpolineThunks::runOnMachineFunction(MachineFunction &MF) {
|
||||
DEBUG(dbgs() << getPassName() << '\n');
|
||||
|
||||
TM = &MF.getTarget();;
|
||||
STI = &MF.getSubtarget<X86Subtarget>();
|
||||
TII = STI->getInstrInfo();
|
||||
Is64Bit = TM->getTargetTriple().getArch() == Triple::x86_64;
|
||||
|
||||
MMI = &getAnalysis<MachineModuleInfo>();
|
||||
Module &M = const_cast<Module &>(*MMI->getModule());
|
||||
|
||||
// If this function is not a thunk, check to see if we need to insert
|
||||
// a thunk.
|
||||
if (!MF.getName().startswith(ThunkNamePrefix)) {
|
||||
// If we've already inserted a thunk, nothing else to do.
|
||||
if (InsertedThunks)
|
||||
return false;
|
||||
|
||||
// Only add a thunk if one of the functions has the retpoline feature
|
||||
// enabled in its subtarget, and doesn't enable external thunks.
|
||||
// FIXME: Conditionalize on indirect calls so we don't emit a thunk when
|
||||
// nothing will end up calling it.
|
||||
// FIXME: It's a little silly to look at every function just to enumerate
|
||||
// the subtargets, but eventually we'll want to look at them for indirect
|
||||
// calls, so maybe this is OK.
|
||||
if (!STI->useRetpoline() || STI->useRetpolineExternalThunk())
|
||||
return false;
|
||||
|
||||
// Otherwise, we need to insert the thunk.
|
||||
// WARNING: This is not really a well behaving thing to do in a function
|
||||
// pass. We extract the module and insert a new function (and machine
|
||||
// function) directly into the module.
|
||||
if (Is64Bit)
|
||||
createThunkFunction(M, R11ThunkName);
|
||||
else
|
||||
for (StringRef Name :
|
||||
{EAXThunkName, ECXThunkName, EDXThunkName, PushThunkName})
|
||||
createThunkFunction(M, Name);
|
||||
InsertedThunks = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
// If this *is* a thunk function, we need to populate it with the correct MI.
|
||||
if (Is64Bit) {
|
||||
assert(MF.getName() == "__llvm_retpoline_r11" &&
|
||||
"Should only have an r11 thunk on 64-bit targets");
|
||||
|
||||
// __llvm_retpoline_r11:
|
||||
// callq .Lr11_call_target
|
||||
// .Lr11_capture_spec:
|
||||
// pause
|
||||
// lfence
|
||||
// jmp .Lr11_capture_spec
|
||||
// .align 16
|
||||
// .Lr11_call_target:
|
||||
// movq %r11, (%rsp)
|
||||
// retq
|
||||
populateThunk(MF, X86::R11);
|
||||
} else {
|
||||
// For 32-bit targets we need to emit a collection of thunks for various
|
||||
// possible scratch registers as well as a fallback that is used when
|
||||
// there are no scratch registers and assumes the retpoline target has
|
||||
// been pushed.
|
||||
// __llvm_retpoline_eax:
|
||||
// calll .Leax_call_target
|
||||
// .Leax_capture_spec:
|
||||
// pause
|
||||
// jmp .Leax_capture_spec
|
||||
// .align 16
|
||||
// .Leax_call_target:
|
||||
// movl %eax, (%esp) # Clobber return addr
|
||||
// retl
|
||||
//
|
||||
// __llvm_retpoline_ecx:
|
||||
// ... # Same setup
|
||||
// movl %ecx, (%esp)
|
||||
// retl
|
||||
//
|
||||
// __llvm_retpoline_edx:
|
||||
// ... # Same setup
|
||||
// movl %edx, (%esp)
|
||||
// retl
|
||||
//
|
||||
// This last one is a bit more special and so needs a little extra
|
||||
// handling.
|
||||
// __llvm_retpoline_push:
|
||||
// calll .Lpush_call_target
|
||||
// .Lpush_capture_spec:
|
||||
// pause
|
||||
// lfence
|
||||
// jmp .Lpush_capture_spec
|
||||
// .align 16
|
||||
// .Lpush_call_target:
|
||||
// # Clear pause_loop return address.
|
||||
// addl $4, %esp
|
||||
// # Top of stack words are: Callee, RA. Exchange Callee and RA.
|
||||
// pushl 4(%esp) # Push callee
|
||||
// pushl 4(%esp) # Push RA
|
||||
// popl 8(%esp) # Pop RA to final RA
|
||||
// popl (%esp) # Pop callee to next top of stack
|
||||
// retl # Ret to callee
|
||||
if (MF.getName() == EAXThunkName)
|
||||
populateThunk(MF, X86::EAX);
|
||||
else if (MF.getName() == ECXThunkName)
|
||||
populateThunk(MF, X86::ECX);
|
||||
else if (MF.getName() == EDXThunkName)
|
||||
populateThunk(MF, X86::EDX);
|
||||
else if (MF.getName() == PushThunkName)
|
||||
populateThunk(MF);
|
||||
else
|
||||
llvm_unreachable("Invalid thunk name on x86-32!");
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void X86RetpolineThunks::createThunkFunction(Module &M, StringRef Name) {
|
||||
assert(Name.startswith(ThunkNamePrefix) &&
|
||||
"Created a thunk with an unexpected prefix!");
|
||||
|
||||
LLVMContext &Ctx = M.getContext();
|
||||
auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
|
||||
Function *F =
|
||||
Function::Create(Type, GlobalValue::LinkOnceODRLinkage, Name, &M);
|
||||
F->setVisibility(GlobalValue::HiddenVisibility);
|
||||
F->setComdat(M.getOrInsertComdat(Name));
|
||||
|
||||
// Add Attributes so that we don't create a frame, unwind information, or
|
||||
// inline.
|
||||
AttrBuilder B;
|
||||
B.addAttribute(llvm::Attribute::NoUnwind);
|
||||
B.addAttribute(llvm::Attribute::Naked);
|
||||
F->addAttributes(llvm::AttributeList::FunctionIndex, B);
|
||||
|
||||
// Populate our function a bit so that we can verify.
|
||||
BasicBlock *Entry = BasicBlock::Create(Ctx, "entry", F);
|
||||
IRBuilder<> Builder(Entry);
|
||||
|
||||
Builder.CreateRetVoid();
|
||||
}
|
||||
|
||||
void X86RetpolineThunks::insertRegReturnAddrClobber(MachineBasicBlock &MBB,
|
||||
unsigned Reg) {
|
||||
const unsigned MovOpc = Is64Bit ? X86::MOV64mr : X86::MOV32mr;
|
||||
const unsigned SPReg = Is64Bit ? X86::RSP : X86::ESP;
|
||||
addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(MovOpc)), SPReg, false, 0)
|
||||
.addReg(Reg);
|
||||
}
|
||||
|
||||
void X86RetpolineThunks::insert32BitPushReturnAddrClobber(
|
||||
MachineBasicBlock &MBB) {
|
||||
// The instruction sequence we use to replace the return address without
|
||||
// a scratch register is somewhat complicated:
|
||||
// # Clear capture_spec from return address.
|
||||
// addl $4, %esp
|
||||
// # Top of stack words are: Callee, RA. Exchange Callee and RA.
|
||||
// pushl 4(%esp) # Push callee
|
||||
// pushl 4(%esp) # Push RA
|
||||
// popl 8(%esp) # Pop RA to final RA
|
||||
// popl (%esp) # Pop callee to next top of stack
|
||||
// retl # Ret to callee
|
||||
BuildMI(&MBB, DebugLoc(), TII->get(X86::ADD32ri), X86::ESP)
|
||||
.addReg(X86::ESP)
|
||||
.addImm(4);
|
||||
addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::PUSH32rmm)), X86::ESP,
|
||||
false, 4);
|
||||
addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::PUSH32rmm)), X86::ESP,
|
||||
false, 4);
|
||||
addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::POP32rmm)), X86::ESP,
|
||||
false, 8);
|
||||
addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::POP32rmm)), X86::ESP,
|
||||
false, 0);
|
||||
}
|
||||
|
||||
void X86RetpolineThunks::populateThunk(MachineFunction &MF,
|
||||
Optional<unsigned> Reg) {
|
||||
// Set MF properties. We never use vregs...
|
||||
MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
|
||||
|
||||
MachineBasicBlock *Entry = &MF.front();
|
||||
Entry->clear();
|
||||
|
||||
MachineBasicBlock *CaptureSpec = MF.CreateMachineBasicBlock(Entry->getBasicBlock());
|
||||
MachineBasicBlock *CallTarget = MF.CreateMachineBasicBlock(Entry->getBasicBlock());
|
||||
MF.push_back(CaptureSpec);
|
||||
MF.push_back(CallTarget);
|
||||
|
||||
const unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
|
||||
const unsigned RetOpc = Is64Bit ? X86::RETQ : X86::RETL;
|
||||
|
||||
BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addMBB(CallTarget);
|
||||
Entry->addSuccessor(CallTarget);
|
||||
Entry->addSuccessor(CaptureSpec);
|
||||
CallTarget->setHasAddressTaken();
|
||||
|
||||
// In the capture loop for speculation, we want to stop the processor from
|
||||
// speculating as fast as possible. On Intel processors, the PAUSE instruction
|
||||
// will block speculation without consuming any execution resources. On AMD
|
||||
// processors, the PAUSE instruction is (essentially) a nop, so we also use an
|
||||
// LFENCE instruction which they have advised will stop speculation as well
|
||||
// with minimal resource utilization. We still end the capture with a jump to
|
||||
// form an infinite loop to fully guarantee that no matter what implementation
|
||||
// of the x86 ISA, speculating this code path never escapes.
|
||||
BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE));
|
||||
BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE));
|
||||
BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
|
||||
CaptureSpec->setHasAddressTaken();
|
||||
CaptureSpec->addSuccessor(CaptureSpec);
|
||||
|
||||
CallTarget->setAlignment(4);
|
||||
if (Reg) {
|
||||
insertRegReturnAddrClobber(*CallTarget, *Reg);
|
||||
} else {
|
||||
assert(!Is64Bit && "We only support non-reg thunks on 32-bit x86!");
|
||||
insert32BitPushReturnAddrClobber(*CallTarget);
|
||||
}
|
||||
BuildMI(CallTarget, DebugLoc(), TII->get(RetOpc));
|
||||
}
|
||||
@ -314,6 +314,8 @@ void X86Subtarget::initializeEnvironment() {
|
||||
HasSGX = false;
|
||||
HasCLFLUSHOPT = false;
|
||||
HasCLWB = false;
|
||||
UseRetpoline = false;
|
||||
UseRetpolineExternalThunk = false;
|
||||
IsPMULLDSlow = false;
|
||||
IsSHLDSlow = false;
|
||||
IsUAMem16Slow = false;
|
||||
|
||||
@ -341,6 +341,14 @@ class X86Subtarget final : public X86GenSubtargetInfo {
|
||||
/// Processor supports Cache Line Write Back instruction
|
||||
bool HasCLWB;
|
||||
|
||||
/// Use a retpoline thunk rather than indirect calls to block speculative
|
||||
/// execution.
|
||||
bool UseRetpoline;
|
||||
|
||||
/// When using a retpoline thunk, call an externally provided thunk rather
|
||||
/// than emitting one inside the compiler.
|
||||
bool UseRetpolineExternalThunk;
|
||||
|
||||
/// Use software floating point for code generation.
|
||||
bool UseSoftFloat;
|
||||
|
||||
@ -574,6 +582,8 @@ class X86Subtarget final : public X86GenSubtargetInfo {
|
||||
bool hasIBT() const { return HasIBT; }
|
||||
bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
|
||||
bool hasCLWB() const { return HasCLWB; }
|
||||
bool useRetpoline() const { return UseRetpoline; }
|
||||
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
|
||||
|
||||
bool isXRaySupported() const override { return is64Bit(); }
|
||||
|
||||
@ -696,6 +706,10 @@ class X86Subtarget final : public X86GenSubtargetInfo {
|
||||
/// Return true if the subtarget allows calls to immediate address.
|
||||
bool isLegalToCallImmediateAddr() const;
|
||||
|
||||
/// If we are using retpolines, we need to expand indirectbr to avoid it
|
||||
/// lowering to an actual indirect jump.
|
||||
bool enableIndirectBrExpand() const override { return useRetpoline(); }
|
||||
|
||||
/// Enable the MachineScheduler pass for all X86 subtargets.
|
||||
bool enableMachineScheduler() const override { return true; }
|
||||
|
||||
|
||||
@ -321,6 +321,7 @@ class X86PassConfig : public TargetPassConfig {
|
||||
void addPreRegAlloc() override;
|
||||
void addPostRegAlloc() override;
|
||||
void addPreEmitPass() override;
|
||||
void addPreEmitPass2() override;
|
||||
void addPreSched2() override;
|
||||
};
|
||||
|
||||
@ -350,6 +351,11 @@ void X86PassConfig::addIRPasses() {
|
||||
|
||||
if (TM->getOptLevel() != CodeGenOpt::None)
|
||||
addPass(createInterleavedAccessPass());
|
||||
|
||||
// Add passes that handle indirect branch removal and insertion of a retpoline
|
||||
// thunk. These will be a no-op unless a function subtarget has the retpoline
|
||||
// feature enabled.
|
||||
addPass(createIndirectBrExpandPass());
|
||||
}
|
||||
|
||||
bool X86PassConfig::addInstSelector() {
|
||||
@ -436,3 +442,7 @@ void X86PassConfig::addPreEmitPass() {
|
||||
addPass(createX86EvexToVexInsts());
|
||||
}
|
||||
}
|
||||
|
||||
void X86PassConfig::addPreEmitPass2() {
|
||||
addPass(createX86RetpolineThunksPass());
|
||||
}
|
||||
|
||||
@ -1176,7 +1176,8 @@ static bool eliminateDeadStores(BasicBlock &BB, AliasAnalysis *AA,
|
||||
auto *Earlier = dyn_cast<StoreInst>(DepWrite);
|
||||
auto *Later = dyn_cast<StoreInst>(Inst);
|
||||
if (Earlier && isa<ConstantInt>(Earlier->getValueOperand()) &&
|
||||
Later && isa<ConstantInt>(Later->getValueOperand())) {
|
||||
Later && isa<ConstantInt>(Later->getValueOperand()) &&
|
||||
memoryIsNotModifiedBetween(Earlier, Later, AA)) {
|
||||
// If the store we find is:
|
||||
// a) partially overwritten by the store to 'Loc'
|
||||
// b) the later store is fully contained in the earlier one and
|
||||
|
||||
@ -1071,6 +1071,7 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
|
||||
NewGEP = GetElementPtrInst::Create(GEP->getResultElementType(), NewGEP,
|
||||
ConstantInt::get(IntPtrTy, Index, true),
|
||||
GEP->getName(), GEP);
|
||||
NewGEP->copyMetadata(*GEP);
|
||||
// Inherit the inbounds attribute of the original GEP.
|
||||
cast<GetElementPtrInst>(NewGEP)->setIsInBounds(GEPWasInBounds);
|
||||
} else {
|
||||
@ -1095,6 +1096,7 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
|
||||
Type::getInt8Ty(GEP->getContext()), NewGEP,
|
||||
ConstantInt::get(IntPtrTy, AccumulativeByteOffset, true), "uglygep",
|
||||
GEP);
|
||||
NewGEP->copyMetadata(*GEP);
|
||||
// Inherit the inbounds attribute of the original GEP.
|
||||
cast<GetElementPtrInst>(NewGEP)->setIsInBounds(GEPWasInBounds);
|
||||
if (GEP->getType() != I8PtrTy)
|
||||
|
||||
@ -2583,6 +2583,10 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Features_Group>;
|
||||
def mno_shstk : Flag<["-"], "mno-shstk">, Group<m_x86_Features_Group>;
|
||||
def mibt : Flag<["-"], "mibt">, Group<m_x86_Features_Group>;
|
||||
def mno_ibt : Flag<["-"], "mno-ibt">, Group<m_x86_Features_Group>;
|
||||
def mretpoline : Flag<["-"], "mretpoline">, Group<m_x86_Features_Group>;
|
||||
def mno_retpoline : Flag<["-"], "mno-retpoline">, Group<m_x86_Features_Group>;
|
||||
def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group<m_x86_Features_Group>;
|
||||
def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>;
|
||||
|
||||
// These are legacy user-facing driver-level option spellings. They are always
|
||||
// aliases for options that are spelled using the more common Unix / GNU flag
|
||||
|
||||
@ -763,6 +763,10 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
|
||||
HasPREFETCHWT1 = true;
|
||||
} else if (Feature == "+clzero") {
|
||||
HasCLZERO = true;
|
||||
} else if (Feature == "+retpoline") {
|
||||
HasRetpoline = true;
|
||||
} else if (Feature == "+retpoline-external-thunk") {
|
||||
HasRetpolineExternalThunk = true;
|
||||
}
|
||||
|
||||
X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
|
||||
@ -1305,6 +1309,8 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
|
||||
.Case("prfchw", HasPRFCHW)
|
||||
.Case("rdrnd", HasRDRND)
|
||||
.Case("rdseed", HasRDSEED)
|
||||
.Case("retpoline", HasRetpoline)
|
||||
.Case("retpoline-external-thunk", HasRetpolineExternalThunk)
|
||||
.Case("rtm", HasRTM)
|
||||
.Case("sgx", HasSGX)
|
||||
.Case("sha", HasSHA)
|
||||
|
||||
@ -96,6 +96,8 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
|
||||
bool HasCLWB = false;
|
||||
bool HasMOVBE = false;
|
||||
bool HasPREFETCHWT1 = false;
|
||||
bool HasRetpoline = false;
|
||||
bool HasRetpolineExternalThunk = false;
|
||||
|
||||
/// \brief Enumeration of all of the X86 CPUs supported by Clang.
|
||||
///
|
||||
|
||||
@ -21,7 +21,7 @@ using namespace lld;
|
||||
using namespace lld::elf;
|
||||
|
||||
namespace {
|
||||
class X86 final : public TargetInfo {
|
||||
class X86 : public TargetInfo {
|
||||
public:
|
||||
X86();
|
||||
RelExpr getRelExpr(RelType Type, const Symbol &S,
|
||||
@ -399,7 +399,145 @@ void X86::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
|
||||
memcpy(Loc - 2, Inst, sizeof(Inst));
|
||||
}
|
||||
|
||||
TargetInfo *elf::getX86TargetInfo() {
|
||||
static X86 Target;
|
||||
return &Target;
|
||||
namespace {
|
||||
class RetpolinePic : public X86 {
|
||||
public:
|
||||
RetpolinePic();
|
||||
void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
|
||||
void writePltHeader(uint8_t *Buf) const override;
|
||||
void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
|
||||
int32_t Index, unsigned RelOff) const override;
|
||||
};
|
||||
|
||||
class RetpolineNoPic : public X86 {
|
||||
public:
|
||||
RetpolineNoPic();
|
||||
void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
|
||||
void writePltHeader(uint8_t *Buf) const override;
|
||||
void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
|
||||
int32_t Index, unsigned RelOff) const override;
|
||||
};
|
||||
} // namespace
|
||||
|
||||
RetpolinePic::RetpolinePic() {
|
||||
PltHeaderSize = 48;
|
||||
PltEntrySize = 32;
|
||||
}
|
||||
|
||||
void RetpolinePic::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
|
||||
write32le(Buf, S.getPltVA() + 17);
|
||||
}
|
||||
|
||||
void RetpolinePic::writePltHeader(uint8_t *Buf) const {
|
||||
const uint8_t Insn[] = {
|
||||
0xff, 0xb3, 0, 0, 0, 0, // 0: pushl GOTPLT+4(%ebx)
|
||||
0x50, // 6: pushl %eax
|
||||
0x8b, 0x83, 0, 0, 0, 0, // 7: mov GOTPLT+8(%ebx), %eax
|
||||
0xe8, 0x0e, 0x00, 0x00, 0x00, // d: call next
|
||||
0xf3, 0x90, // 12: loop: pause
|
||||
0x0f, 0xae, 0xe8, // 14: lfence
|
||||
0xeb, 0xf9, // 17: jmp loop
|
||||
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 19: int3; .align 16
|
||||
0x89, 0x0c, 0x24, // 20: next: mov %ecx, (%esp)
|
||||
0x8b, 0x4c, 0x24, 0x04, // 23: mov 0x4(%esp), %ecx
|
||||
0x89, 0x44, 0x24, 0x04, // 27: mov %eax ,0x4(%esp)
|
||||
0x89, 0xc8, // 2b: mov %ecx, %eax
|
||||
0x59, // 2d: pop %ecx
|
||||
0xc3, // 2e: ret
|
||||
};
|
||||
memcpy(Buf, Insn, sizeof(Insn));
|
||||
|
||||
uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
|
||||
uint32_t GotPlt = InX::GotPlt->getVA() - Ebx;
|
||||
write32le(Buf + 2, GotPlt + 4);
|
||||
write32le(Buf + 9, GotPlt + 8);
|
||||
}
|
||||
|
||||
void RetpolinePic::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
|
||||
uint64_t PltEntryAddr, int32_t Index,
|
||||
unsigned RelOff) const {
|
||||
const uint8_t Insn[] = {
|
||||
0x50, // pushl %eax
|
||||
0x8b, 0x83, 0, 0, 0, 0, // mov foo@GOT(%ebx), %eax
|
||||
0xe8, 0, 0, 0, 0, // call plt+0x20
|
||||
0xe9, 0, 0, 0, 0, // jmp plt+0x12
|
||||
0x68, 0, 0, 0, 0, // pushl $reloc_offset
|
||||
0xe9, 0, 0, 0, 0, // jmp plt+0
|
||||
};
|
||||
memcpy(Buf, Insn, sizeof(Insn));
|
||||
|
||||
uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
|
||||
write32le(Buf + 3, GotPltEntryAddr - Ebx);
|
||||
write32le(Buf + 8, -Index * PltEntrySize - PltHeaderSize - 12 + 32);
|
||||
write32le(Buf + 13, -Index * PltEntrySize - PltHeaderSize - 17 + 18);
|
||||
write32le(Buf + 18, RelOff);
|
||||
write32le(Buf + 23, -Index * PltEntrySize - PltHeaderSize - 27);
|
||||
}
|
||||
|
||||
RetpolineNoPic::RetpolineNoPic() {
|
||||
PltHeaderSize = 48;
|
||||
PltEntrySize = 32;
|
||||
}
|
||||
|
||||
void RetpolineNoPic::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
|
||||
write32le(Buf, S.getPltVA() + 16);
|
||||
}
|
||||
|
||||
void RetpolineNoPic::writePltHeader(uint8_t *Buf) const {
|
||||
const uint8_t PltData[] = {
|
||||
0xff, 0x35, 0, 0, 0, 0, // 0: pushl GOTPLT+4
|
||||
0x50, // 6: pushl %eax
|
||||
0xa1, 0, 0, 0, 0, // 7: mov GOTPLT+8, %eax
|
||||
0xe8, 0x0f, 0x00, 0x00, 0x00, // c: call next
|
||||
0xf3, 0x90, // 11: loop: pause
|
||||
0x0f, 0xae, 0xe8, // 13: lfence
|
||||
0xeb, 0xf9, // 16: jmp loop
|
||||
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 18: int3
|
||||
0xcc, 0xcc, 0xcc, // 1f: int3; .align 16
|
||||
0x89, 0x0c, 0x24, // 20: next: mov %ecx, (%esp)
|
||||
0x8b, 0x4c, 0x24, 0x04, // 23: mov 0x4(%esp), %ecx
|
||||
0x89, 0x44, 0x24, 0x04, // 27: mov %eax ,0x4(%esp)
|
||||
0x89, 0xc8, // 2b: mov %ecx, %eax
|
||||
0x59, // 2d: pop %ecx
|
||||
0xc3, // 2e: ret
|
||||
};
|
||||
memcpy(Buf, PltData, sizeof(PltData));
|
||||
|
||||
uint32_t GotPlt = InX::GotPlt->getVA();
|
||||
write32le(Buf + 2, GotPlt + 4);
|
||||
write32le(Buf + 8, GotPlt + 8);
|
||||
}
|
||||
|
||||
void RetpolineNoPic::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
|
||||
uint64_t PltEntryAddr, int32_t Index,
|
||||
unsigned RelOff) const {
|
||||
const uint8_t Insn[] = {
|
||||
0x50, // 0: pushl %eax
|
||||
0xa1, 0, 0, 0, 0, // 1: mov foo_in_GOT, %eax
|
||||
0xe8, 0, 0, 0, 0, // 6: call plt+0x20
|
||||
0xe9, 0, 0, 0, 0, // b: jmp plt+0x11
|
||||
0x68, 0, 0, 0, 0, // 10: pushl $reloc_offset
|
||||
0xe9, 0, 0, 0, 0, // 15: jmp plt+0
|
||||
};
|
||||
memcpy(Buf, Insn, sizeof(Insn));
|
||||
|
||||
write32le(Buf + 2, GotPltEntryAddr);
|
||||
write32le(Buf + 7, -Index * PltEntrySize - PltHeaderSize - 11 + 32);
|
||||
write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16 + 17);
|
||||
write32le(Buf + 17, RelOff);
|
||||
write32le(Buf + 22, -Index * PltEntrySize - PltHeaderSize - 26);
|
||||
}
|
||||
|
||||
TargetInfo *elf::getX86TargetInfo() {
|
||||
if (Config->ZRetpolineplt) {
|
||||
if (Config->Pic) {
|
||||
static RetpolinePic T;
|
||||
return &T;
|
||||
}
|
||||
static RetpolineNoPic T;
|
||||
return &T;
|
||||
}
|
||||
|
||||
static X86 T;
|
||||
return &T;
|
||||
}
|
||||
|
||||
@ -23,7 +23,7 @@ using namespace lld;
|
||||
using namespace lld::elf;
|
||||
|
||||
namespace {
|
||||
template <class ELFT> class X86_64 final : public TargetInfo {
|
||||
template <class ELFT> class X86_64 : public TargetInfo {
|
||||
public:
|
||||
X86_64();
|
||||
RelExpr getRelExpr(RelType Type, const Symbol &S,
|
||||
@ -460,12 +460,125 @@ void X86_64<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const {
|
||||
write32le(Loc - 1, Val + 1);
|
||||
}
|
||||
|
||||
TargetInfo *elf::getX32TargetInfo() {
|
||||
static X86_64<ELF32LE> Target;
|
||||
return &Target;
|
||||
namespace {
|
||||
template <class ELFT> class Retpoline : public X86_64<ELFT> {
|
||||
public:
|
||||
Retpoline();
|
||||
void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
|
||||
void writePltHeader(uint8_t *Buf) const override;
|
||||
void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
|
||||
int32_t Index, unsigned RelOff) const override;
|
||||
};
|
||||
|
||||
template <class ELFT> class RetpolineZNow : public X86_64<ELFT> {
|
||||
public:
|
||||
RetpolineZNow();
|
||||
void writeGotPlt(uint8_t *Buf, const Symbol &S) const override {}
|
||||
void writePltHeader(uint8_t *Buf) const override;
|
||||
void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
|
||||
int32_t Index, unsigned RelOff) const override;
|
||||
};
|
||||
} // namespace
|
||||
|
||||
template <class ELFT> Retpoline<ELFT>::Retpoline() {
|
||||
TargetInfo::PltHeaderSize = 48;
|
||||
TargetInfo::PltEntrySize = 32;
|
||||
}
|
||||
|
||||
TargetInfo *elf::getX86_64TargetInfo() {
|
||||
static X86_64<ELF64LE> Target;
|
||||
return &Target;
|
||||
template <class ELFT>
|
||||
void Retpoline<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
|
||||
write32le(Buf, S.getPltVA() + 17);
|
||||
}
|
||||
|
||||
template <class ELFT> void Retpoline<ELFT>::writePltHeader(uint8_t *Buf) const {
|
||||
const uint8_t Insn[] = {
|
||||
0xff, 0x35, 0, 0, 0, 0, // 0: pushq GOTPLT+8(%rip)
|
||||
0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // 6: mov GOTPLT+16(%rip), %r11
|
||||
0xe8, 0x0e, 0x00, 0x00, 0x00, // d: callq next
|
||||
0xf3, 0x90, // 12: loop: pause
|
||||
0x0f, 0xae, 0xe8, // 14: lfence
|
||||
0xeb, 0xf9, // 17: jmp loop
|
||||
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 19: int3; .align 16
|
||||
0x4c, 0x89, 0x1c, 0x24, // 20: next: mov %r11, (%rsp)
|
||||
0xc3, // 24: ret
|
||||
};
|
||||
memcpy(Buf, Insn, sizeof(Insn));
|
||||
|
||||
uint64_t GotPlt = InX::GotPlt->getVA();
|
||||
uint64_t Plt = InX::Plt->getVA();
|
||||
write32le(Buf + 2, GotPlt - Plt - 6 + 8);
|
||||
write32le(Buf + 9, GotPlt - Plt - 13 + 16);
|
||||
}
|
||||
|
||||
template <class ELFT>
|
||||
void Retpoline<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
|
||||
uint64_t PltEntryAddr, int32_t Index,
|
||||
unsigned RelOff) const {
|
||||
const uint8_t Insn[] = {
|
||||
0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // 0: mov foo@GOTPLT(%rip), %r11
|
||||
0xe8, 0, 0, 0, 0, // 7: callq plt+0x20
|
||||
0xe9, 0, 0, 0, 0, // c: jmp plt+0x12
|
||||
0x68, 0, 0, 0, 0, // 11: pushq <relocation index>
|
||||
0xe9, 0, 0, 0, 0, // 16: jmp plt+0
|
||||
};
|
||||
memcpy(Buf, Insn, sizeof(Insn));
|
||||
|
||||
uint64_t Off = TargetInfo::PltHeaderSize + TargetInfo::PltEntrySize * Index;
|
||||
|
||||
write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7);
|
||||
write32le(Buf + 8, -Off - 12 + 32);
|
||||
write32le(Buf + 13, -Off - 17 + 18);
|
||||
write32le(Buf + 18, Index);
|
||||
write32le(Buf + 23, -Off - 27);
|
||||
}
|
||||
|
||||
template <class ELFT> RetpolineZNow<ELFT>::RetpolineZNow() {
|
||||
TargetInfo::PltHeaderSize = 32;
|
||||
TargetInfo::PltEntrySize = 16;
|
||||
}
|
||||
|
||||
template <class ELFT>
|
||||
void RetpolineZNow<ELFT>::writePltHeader(uint8_t *Buf) const {
|
||||
const uint8_t Insn[] = {
|
||||
0xe8, 0x0b, 0x00, 0x00, 0x00, // 0: call next
|
||||
0xf3, 0x90, // 5: loop: pause
|
||||
0x0f, 0xae, 0xe8, // 7: lfence
|
||||
0xeb, 0xf9, // a: jmp loop
|
||||
0xcc, 0xcc, 0xcc, 0xcc, // c: int3; .align 16
|
||||
0x4c, 0x89, 0x1c, 0x24, // 10: next: mov %r11, (%rsp)
|
||||
0xc3, // 14: ret
|
||||
};
|
||||
memcpy(Buf, Insn, sizeof(Insn));
|
||||
}
|
||||
|
||||
template <class ELFT>
|
||||
void RetpolineZNow<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
|
||||
uint64_t PltEntryAddr, int32_t Index,
|
||||
unsigned RelOff) const {
|
||||
const uint8_t Insn[] = {
|
||||
0x4c, 0x8b, 0x1d, 0, 0, 0, 0, // mov foo@GOTPLT(%rip), %r11
|
||||
0xe9, 0, 0, 0, 0, // jmp plt+0
|
||||
};
|
||||
memcpy(Buf, Insn, sizeof(Insn));
|
||||
|
||||
write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7);
|
||||
write32le(Buf + 8,
|
||||
-Index * TargetInfo::PltEntrySize - TargetInfo::PltHeaderSize - 12);
|
||||
}
|
||||
|
||||
template <class ELFT> TargetInfo *getTargetInfo() {
|
||||
if (Config->ZRetpolineplt) {
|
||||
if (Config->ZNow) {
|
||||
static RetpolineZNow<ELFT> T;
|
||||
return &T;
|
||||
}
|
||||
static Retpoline<ELFT> T;
|
||||
return &T;
|
||||
}
|
||||
|
||||
static X86_64<ELFT> T;
|
||||
return &T;
|
||||
}
|
||||
|
||||
TargetInfo *elf::getX32TargetInfo() { return getTargetInfo<ELF32LE>(); }
|
||||
TargetInfo *elf::getX86_64TargetInfo() { return getTargetInfo<ELF64LE>(); }
|
||||
|
||||
@ -159,6 +159,7 @@ struct Configuration {
|
||||
bool ZRelro;
|
||||
bool ZRodynamic;
|
||||
bool ZText;
|
||||
bool ZRetpolineplt;
|
||||
bool ExitEarly;
|
||||
bool ZWxneeded;
|
||||
DiscardPolicy Discard;
|
||||
|
||||
@ -674,6 +674,7 @@ void LinkerDriver::readConfigs(opt::InputArgList &Args) {
|
||||
Config->ZNow = hasZOption(Args, "now");
|
||||
Config->ZOrigin = hasZOption(Args, "origin");
|
||||
Config->ZRelro = !hasZOption(Args, "norelro");
|
||||
Config->ZRetpolineplt = hasZOption(Args, "retpolineplt");
|
||||
Config->ZRodynamic = hasZOption(Args, "rodynamic");
|
||||
Config->ZStackSize = args::getZOptionValue(Args, OPT_z, "stack-size", 0);
|
||||
Config->ZText = !hasZOption(Args, "notext");
|
||||
|
||||
@ -402,6 +402,7 @@ int main(int argc, char **argv) {
|
||||
initializeSjLjEHPreparePass(Registry);
|
||||
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
|
||||
initializeGlobalMergePass(Registry);
|
||||
initializeIndirectBrExpandPassPass(Registry);
|
||||
initializeInterleavedAccessPass(Registry);
|
||||
initializeEntryExitInstrumenterPass(Registry);
|
||||
initializePostInlineEntryExitInstrumenterPass(Registry);
|
||||
|
||||
@ -8,4 +8,4 @@
|
||||
|
||||
#define CLANG_VENDOR "FreeBSD "
|
||||
|
||||
#define SVN_REVISION "323948"
|
||||
#define SVN_REVISION "324090"
|
||||
|
||||
@ -4,5 +4,5 @@
|
||||
#define LLD_VERSION_STRING "6.0.0"
|
||||
#define LLD_VERSION_MAJOR 6
|
||||
#define LLD_VERSION_MINOR 0
|
||||
#define LLD_REVISION_STRING "323948"
|
||||
#define LLD_REVISION_STRING "324090"
|
||||
#define LLD_REPOSITORY_STRING "FreeBSD"
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
/* $FreeBSD$ */
|
||||
#define LLVM_REVISION "svn-r323948"
|
||||
#define LLVM_REVISION "svn-r324090"
|
||||
|
||||
@ -183,6 +183,7 @@ SRCS_MIN+= CodeGen/GlobalISel/Utils.cpp
|
||||
SRCS_MIN+= CodeGen/GlobalMerge.cpp
|
||||
SRCS_MIN+= CodeGen/IfConversion.cpp
|
||||
SRCS_MIN+= CodeGen/ImplicitNullChecks.cpp
|
||||
SRCS_MIN+= CodeGen/IndirectBrExpandPass.cpp
|
||||
SRCS_MIN+= CodeGen/InlineSpiller.cpp
|
||||
SRCS_MIN+= CodeGen/InterferenceCache.cpp
|
||||
SRCS_MIN+= CodeGen/InterleavedAccessPass.cpp
|
||||
@ -1057,6 +1058,7 @@ SRCS_MIN+= Target/X86/X86OptimizeLEAs.cpp
|
||||
SRCS_MIN+= Target/X86/X86PadShortFunction.cpp
|
||||
SRCS_MIN+= Target/X86/X86RegisterBankInfo.cpp
|
||||
SRCS_MIN+= Target/X86/X86RegisterInfo.cpp
|
||||
SRCS_MIN+= Target/X86/X86RetpolineThunks.cpp
|
||||
SRCS_MIN+= Target/X86/X86SelectionDAGInfo.cpp
|
||||
SRCS_MIN+= Target/X86/X86ShuffleDecodeConstantPool.cpp
|
||||
SRCS_MIN+= Target/X86/X86Subtarget.cpp
|
||||
|
||||
Loading…
Reference in New Issue
Block a user