Import from rebasing repo at b78b6b80 (new files)
This commit is contained in:
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2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=270866 svn path=/vendor/device-tree/ianc-b78b6b80/dist/; revision=270867; tag=vendor/device-tree/ianc-b78b6b80
4
.gitignore
vendored
Normal file
4
.gitignore
vendored
Normal file
@ -0,0 +1,4 @@
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||||
.*
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||||
!.gitignore
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*.dtb
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|
7
Bindings/arm/adapteva.txt
Normal file
7
Bindings/arm/adapteva.txt
Normal file
@ -0,0 +1,7 @@
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Adapteva Platforms Device Tree Bindings
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---------------------------------------
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Parallella board
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Required root node properties:
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- compatible = "adapteva,parallella";
|
9
Bindings/arm/armada-375.txt
Normal file
9
Bindings/arm/armada-375.txt
Normal file
@ -0,0 +1,9 @@
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Marvell Armada 375 Platforms Device Tree Bindings
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-------------------------------------------------
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Boards with a SoC of the Marvell Armada 375 family shall have the
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following property:
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Required root node property:
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|
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compatible: must contain "marvell,armada375"
|
14
Bindings/arm/armada-380-mpcore-soc-ctrl.txt
Normal file
14
Bindings/arm/armada-380-mpcore-soc-ctrl.txt
Normal file
@ -0,0 +1,14 @@
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Marvell Armada 38x CA9 MPcore SoC Controller
|
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============================================
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Required properties:
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- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
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|
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- reg: should be the register base and length as documented in the
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datasheet for the CA9 MPcore SoC Control registers
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|
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mpcore-soc-ctrl@20d20 {
|
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compatible = "marvell,armada-380-mpcore-soc-ctrl";
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reg = <0x20d20 0x6c>;
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};
|
20
Bindings/arm/armada-38x.txt
Normal file
20
Bindings/arm/armada-38x.txt
Normal file
@ -0,0 +1,20 @@
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Marvell Armada 38x Platforms Device Tree Bindings
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-------------------------------------------------
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Boards with a SoC of the Marvell Armada 38x family shall have the
|
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following property:
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||||
|
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Required root node property:
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||||
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- compatible: must contain "marvell,armada380"
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|
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In addition, boards using the Marvell Armada 385 SoC shall have the
|
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following property before the previous one:
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Required root node property:
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compatible: must contain "marvell,armada385"
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Example:
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compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
|
14
Bindings/arm/armada-cpu-reset.txt
Normal file
14
Bindings/arm/armada-cpu-reset.txt
Normal file
@ -0,0 +1,14 @@
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Marvell Armada CPU reset controller
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===================================
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|
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Required properties:
|
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|
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- compatible: Should be "marvell,armada-370-cpu-reset".
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|
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- reg: should be register base and length as documented in the
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datasheet for the CPU reset registers
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cpurst: cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x20>;
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};
|
12
Bindings/arm/axxia.txt
Normal file
12
Bindings/arm/axxia.txt
Normal file
@ -0,0 +1,12 @@
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Axxia AXM55xx device tree bindings
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Boards using the AXM55xx SoC need to have the following properties:
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Required root node property:
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- compatible = "lsi,axm5516"
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Boards:
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LSI AXM5516 Validation board (Amarillo)
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compatible = "lsi,axm5516-amarillo", "lsi,axm5516"
|
15
Bindings/arm/bcm/bcm21664.txt
Normal file
15
Bindings/arm/bcm/bcm21664.txt
Normal file
@ -0,0 +1,15 @@
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Broadcom BCM21664 device tree bindings
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--------------------------------------
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This document describes the device tree bindings for boards with the BCM21664
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SoC.
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|
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Required root node property:
|
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- compatible: brcm,bcm21664
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Example:
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/ {
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model = "BCM21664 SoC";
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compatible = "brcm,bcm21664";
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[...]
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}
|
36
Bindings/arm/bcm/brcm,bcm11351-cpu-method
Normal file
36
Bindings/arm/bcm/brcm,bcm11351-cpu-method
Normal file
@ -0,0 +1,36 @@
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Broadcom Kona Family CPU Enable Method
|
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--------------------------------------
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This binding defines the enable method used for starting secondary
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CPUs in the following Broadcom SoCs:
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BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
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|
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The enable method is specified by defining the following required
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properties in the "cpus" device tree node:
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- enable-method = "brcm,bcm11351-cpu-method";
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- secondary-boot-reg = <...>;
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|
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The secondary-boot-reg property is a u32 value that specifies the
|
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physical address of the register used to request the ROM holding pen
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code release a secondary CPU. The value written to the register is
|
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formed by encoding the target CPU id into the low bits of the
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physical start address it should jump to.
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm11351-cpu-method";
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secondary-boot-reg = <0x3500417c>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu1: cpu@1 {
|
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
|
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};
|
14
Bindings/arm/bcm/kona-resetmgr.txt
Normal file
14
Bindings/arm/bcm/kona-resetmgr.txt
Normal file
@ -0,0 +1,14 @@
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Broadcom Kona Family Reset Manager
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----------------------------------
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The reset manager is used on the Broadcom BCM21664 SoC.
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Required properties:
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- compatible: brcm,bcm21664-resetmgr
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- reg: memory address & range
|
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Example:
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brcm,resetmgr@35001f00 {
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compatible = "brcm,bcm21664-resetmgr";
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reg = <0x35001f00 0x24>;
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};
|
8
Bindings/arm/bcm4708.txt
Normal file
8
Bindings/arm/bcm4708.txt
Normal file
@ -0,0 +1,8 @@
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Broadcom BCM4708 device tree bindings
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-------------------------------------------
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Boards with the BCM4708 SoC shall have the following properties:
|
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Required root node property:
|
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compatible = "brcm,bcm4708";
|
95
Bindings/arm/brcm-brcmstb.txt
Normal file
95
Bindings/arm/brcm-brcmstb.txt
Normal file
@ -0,0 +1,95 @@
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ARM Broadcom STB platforms Device Tree Bindings
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-----------------------------------------------
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Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
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SoC shall have the following DT organization:
|
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Required root node properties:
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- compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
|
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example:
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Broadcom STB (bcm7445)";
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compatible = "brcm,bcm7445", "brcm,brcmstb";
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Further, syscon nodes that map platform-specific registers used for general
|
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system control is required:
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|
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- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
|
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- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
|
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- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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|
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example:
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rdb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x00 0xf0000000 0x1000000>;
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sun_top_ctrl: syscon@404000 {
|
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compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
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reg = <0x404000 0x51c>;
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};
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hif_cpubiuctrl: syscon@3e2400 {
|
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compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
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reg = <0x3e2400 0x5b4>;
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};
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hif_continuation: syscon@452000 {
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compatible = "brcm,bcm7445-hif-continuation", "syscon";
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reg = <0x452000 0x100>;
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};
|
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};
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|
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Lastly, nodes that allow for support of SMP initialization and reboot are
|
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required:
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smpboot
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-------
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Required properties:
|
||||
|
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- compatible
|
||||
The string "brcm,brcmstb-smpboot".
|
||||
|
||||
- syscon-cpu
|
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A phandle / integer array property which lets the BSP know the location
|
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of certain CPU power-on registers.
|
||||
|
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The layout of the property is as follows:
|
||||
o a phandle to the "hif_cpubiuctrl" syscon node
|
||||
o offset to the base CPU power zone register
|
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o offset to the base CPU reset register
|
||||
|
||||
- syscon-cont
|
||||
A phandle pointing to the syscon node which describes the CPU boot
|
||||
continuation registers.
|
||||
o a phandle to the "hif_continuation" syscon node
|
||||
|
||||
example:
|
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smpboot {
|
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compatible = "brcm,brcmstb-smpboot";
|
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syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
|
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syscon-cont = <&hif_continuation>;
|
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};
|
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|
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reboot
|
||||
-------
|
||||
Required properties
|
||||
|
||||
- compatible
|
||||
The string property "brcm,brcmstb-reboot".
|
||||
|
||||
- syscon
|
||||
A phandle / integer array that points to the syscon node which describes
|
||||
the general system reset registers.
|
||||
o a phandle to "sun_top_ctrl"
|
||||
o offset to the "reset source enable" register
|
||||
o offset to the "software master reset" register
|
||||
|
||||
example:
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
21
Bindings/arm/ccn.txt
Normal file
21
Bindings/arm/ccn.txt
Normal file
@ -0,0 +1,21 @@
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* ARM CCN (Cache Coherent Network)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: (standard compatible string) should be one of:
|
||||
"arm,ccn-504"
|
||||
"arm,ccn-508"
|
||||
|
||||
- reg: (standard registers property) physical address and size
|
||||
(16MB) of the configuration registers block
|
||||
|
||||
- interrupts: (standard interrupt property) single interrupt
|
||||
generated by the control block
|
||||
|
||||
Example:
|
||||
|
||||
ccn@0x2000000000 {
|
||||
compatible = "arm,ccn-504";
|
||||
reg = <0x20 0x00000000 0 0x1000000>;
|
||||
interrupts = <0 181 4>;
|
||||
};
|
41
Bindings/arm/cpu-enable-method/marvell,berlin-smp
Normal file
41
Bindings/arm/cpu-enable-method/marvell,berlin-smp
Normal file
@ -0,0 +1,41 @@
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========================================================
|
||||
Secondary CPU enable-method "marvell,berlin-smp" binding
|
||||
========================================================
|
||||
|
||||
This document describes the "marvell,berlin-smp" method for enabling secondary
|
||||
CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
|
||||
be defined in the "cpus" node.
|
||||
|
||||
Enable method name: "marvell,berlin-smp"
|
||||
Compatible machines: "marvell,berlin2" and "marvell,berlin2q"
|
||||
Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
|
||||
Related properties: (none)
|
||||
|
||||
Note:
|
||||
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
|
||||
"marvell,berlin-cpu-ctrl"[1].
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,berlin-smp";
|
||||
|
||||
cpu@0 {
|
||||
compatible = "marvell,pj4b";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "marvell,pj4b";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
--
|
||||
[1] arm/marvell,berlin.txt
|
38
Bindings/arm/exynos/smp-sysram.txt
Normal file
38
Bindings/arm/exynos/smp-sysram.txt
Normal file
@ -0,0 +1,38 @@
|
||||
Samsung Exynos SYSRAM for SMP bringup:
|
||||
------------------------------------
|
||||
|
||||
Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
|
||||
of the secondary cores. Once the core gets powered up it executes the
|
||||
code that is residing at some specific location of the SYSRAM.
|
||||
|
||||
Therefore reserved section sub-nodes have to be added to the mmio-sram
|
||||
declaration. These nodes are of two types depending upon secure or
|
||||
non-secure execution environment.
|
||||
|
||||
Required sub-node properties:
|
||||
- compatible : depending upon boot mode, should be
|
||||
"samsung,exynos4210-sysram" : for Secure SYSRAM
|
||||
"samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
|
||||
|
||||
The rest of the properties should follow the generic mmio-sram discription
|
||||
found in ../../misc/sysram.txt
|
||||
|
||||
Example:
|
||||
|
||||
sysram@02020000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x02020000 0x54000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x02020000 0x54000>;
|
||||
|
||||
smp-sysram@0 {
|
||||
compatible = "samsung,exynos4210-sysram";
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
smp-sysram@53000 {
|
||||
compatible = "samsung,exynos4210-sysram-ns";
|
||||
reg = <0x53000 0x1000>;
|
||||
};
|
||||
};
|
79
Bindings/arm/gic-v3.txt
Normal file
79
Bindings/arm/gic-v3.txt
Normal file
@ -0,0 +1,79 @@
|
||||
* ARM Generic Interrupt Controller, version 3
|
||||
|
||||
AArch64 SMP cores are often associated with a GICv3, providing Private
|
||||
Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
|
||||
Software Generated Interrupts (SGI), and Locality-specific Peripheral
|
||||
Interrupts (LPI).
|
||||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : should at least contain "arm,gic-v3".
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. Must be a single cell with a value of at least 3.
|
||||
|
||||
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
||||
interrupts. Other values are reserved for future use.
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
bits[3:0] trigger type and level flags.
|
||||
1 = edge triggered
|
||||
4 = level triggered
|
||||
|
||||
Cells 4 and beyond are reserved for future use. When the 1st cell
|
||||
has a value of 0 or 1, cells 4 and beyond act as padding, and may be
|
||||
ignored. It is recommended that padding cells have a value of 0.
|
||||
|
||||
- reg : Specifies base physical address(s) and size of the GIC
|
||||
registers, in the following order:
|
||||
- GIC Distributor interface (GICD)
|
||||
- GIC Redistributors (GICR), one range per redistributor region
|
||||
- GIC CPU interface (GICC)
|
||||
- GIC Hypervisor interface (GICH)
|
||||
- GIC Virtual CPU interface (GICV)
|
||||
|
||||
GICC, GICH and GICV are optional.
|
||||
|
||||
- interrupts : Interrupt source of the VGIC maintenance interrupt.
|
||||
|
||||
Optional
|
||||
|
||||
- redistributor-stride : If using padding pages, specifies the stride
|
||||
of consecutive redistributors. Must be a multiple of 64kB.
|
||||
|
||||
- #redistributor-regions: The number of independent contiguous regions
|
||||
occupied by the redistributors. Required if more than one such
|
||||
region is present.
|
||||
|
||||
Examples:
|
||||
|
||||
gic: interrupt-controller@2cf00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2f000000 0 0x10000>, // GICD
|
||||
<0x0 0x2f100000 0 0x200000>, // GICR
|
||||
<0x0 0x2c000000 0 0x2000>, // GICC
|
||||
<0x0 0x2c010000 0 0x2000>, // GICH
|
||||
<0x0 0x2c020000 0 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c010000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
redistributor-stride = <0x0 0x40000>; // 256kB stride
|
||||
#redistributor-regions = <2>;
|
||||
reg = <0x0 0x2c010000 0 0x10000>, // GICD
|
||||
<0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
|
||||
<0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
|
||||
<0x0 0x2c040000 0 0x2000>, // GICC
|
||||
<0x0 0x2c060000 0 0x2000>, // GICH
|
||||
<0x0 0x2c080000 0 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
};
|
22
Bindings/arm/marvell,dove.txt
Normal file
22
Bindings/arm/marvell,dove.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Marvell Dove Platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
|
||||
Boards with a Marvell Dove SoC shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
- compatible: must contain "marvell,dove";
|
||||
|
||||
* Global Configuration registers
|
||||
|
||||
Global Configuration registers of Dove SoC are shared by a syscon node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must contain "marvell,dove-global-config" and "syscon".
|
||||
- reg: base address and size of the Global Configuration registers.
|
||||
|
||||
Example:
|
||||
|
||||
gconf: global-config@e802c {
|
||||
compatible = "marvell,dove-global-config", "syscon";
|
||||
reg = <0xe802c 0x14>;
|
||||
};
|
97
Bindings/arm/marvell,kirkwood.txt
Normal file
97
Bindings/arm/marvell,kirkwood.txt
Normal file
@ -0,0 +1,97 @@
|
||||
Marvell Kirkwood SoC Family Device Tree Bindings
|
||||
------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Kirkwook family, eg 88f6281
|
||||
|
||||
* Required root node properties:
|
||||
compatible: must contain "marvell,kirkwood"
|
||||
|
||||
In addition, the above compatible shall be extended with the specific
|
||||
SoC. Currently known SoC compatibles are:
|
||||
|
||||
"marvell,kirkwood-88f6192"
|
||||
"marvell,kirkwood-88f6281"
|
||||
"marvell,kirkwood-88f6282"
|
||||
"marvell,kirkwood-88f6283"
|
||||
"marvell,kirkwood-88f6702"
|
||||
"marvell,kirkwood-98DX4122"
|
||||
|
||||
And in addition, the compatible shall be extended with the specific
|
||||
board. Currently known boards are:
|
||||
|
||||
"buffalo,lschlv2"
|
||||
"buffalo,lsxhl"
|
||||
"buffalo,lsxl"
|
||||
"dlink,dns-320"
|
||||
"dlink,dns-320-a1"
|
||||
"dlink,dns-325"
|
||||
"dlink,dns-325-a1"
|
||||
"dlink,dns-kirkwood"
|
||||
"excito,b3"
|
||||
"globalscale,dreamplug-003-ds2001"
|
||||
"globalscale,guruplug"
|
||||
"globalscale,guruplug-server-plus"
|
||||
"globalscale,sheevaplug"
|
||||
"globalscale,sheevaplug"
|
||||
"globalscale,sheevaplug-esata"
|
||||
"globalscale,sheevaplug-esata-rev13"
|
||||
"iom,iconnect"
|
||||
"iom,iconnect-1.1"
|
||||
"iom,ix2-200"
|
||||
"keymile,km_kirkwood"
|
||||
"lacie,cloudbox"
|
||||
"lacie,inetspace_v2"
|
||||
"lacie,laplug"
|
||||
"lacie,netspace_lite_v2"
|
||||
"lacie,netspace_max_v2"
|
||||
"lacie,netspace_mini_v2"
|
||||
"lacie,netspace_v2"
|
||||
"marvell,db-88f6281-bp"
|
||||
"marvell,db-88f6282-bp"
|
||||
"marvell,mv88f6281gtw-ge"
|
||||
"marvell,rd88f6281"
|
||||
"marvell,rd88f6281"
|
||||
"marvell,rd88f6281-a0"
|
||||
"marvell,rd88f6281-a1"
|
||||
"mpl,cec4"
|
||||
"mpl,cec4-10"
|
||||
"netgear,readynas"
|
||||
"netgear,readynas"
|
||||
"netgear,readynas-duo-v2"
|
||||
"netgear,readynas-nv+-v2"
|
||||
"plathome,openblocks-a6"
|
||||
"plathome,openblocks-a7"
|
||||
"raidsonic,ib-nas6210"
|
||||
"raidsonic,ib-nas6210-b"
|
||||
"raidsonic,ib-nas6220"
|
||||
"raidsonic,ib-nas6220-b"
|
||||
"raidsonic,ib-nas62x0"
|
||||
"seagate,dockstar"
|
||||
"seagate,goflexnet"
|
||||
"synology,ds109"
|
||||
"synology,ds110jv10"
|
||||
"synology,ds110jv20"
|
||||
"synology,ds110jv30"
|
||||
"synology,ds111"
|
||||
"synology,ds209"
|
||||
"synology,ds210jv10"
|
||||
"synology,ds210jv20"
|
||||
"synology,ds212"
|
||||
"synology,ds212jv10"
|
||||
"synology,ds212jv20"
|
||||
"synology,ds212pv10"
|
||||
"synology,ds409"
|
||||
"synology,ds409slim"
|
||||
"synology,ds410j"
|
||||
"synology,ds411"
|
||||
"synology,ds411j"
|
||||
"synology,ds411slim"
|
||||
"synology,ds413jv10"
|
||||
"synology,rs212"
|
||||
"synology,rs409"
|
||||
"synology,rs411"
|
||||
"synology,rs812"
|
||||
"usi,topkick"
|
||||
"usi,topkick-1281P2"
|
||||
"zyxel,nsa310"
|
||||
"zyxel,nsa310a"
|
8
Bindings/arm/mediatek.txt
Normal file
8
Bindings/arm/mediatek.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Mediatek MT6589 Platforms Device Tree Bindings
|
||||
|
||||
Boards with a SoC of the Mediatek MT6589 shall have the following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "mediatek,mt6589"
|
||||
|
16
Bindings/arm/mrvl/feroceon.txt
Normal file
16
Bindings/arm/mrvl/feroceon.txt
Normal file
@ -0,0 +1,16 @@
|
||||
* Marvell Feroceon Cache
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be either "marvell,feroceon-cache" or
|
||||
"marvell,kirkwood-cache".
|
||||
|
||||
Optional properties:
|
||||
- reg : Address of the L2 cache control register. Mandatory for
|
||||
"marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
|
||||
|
||||
|
||||
Example:
|
||||
l2: l2-cache@20128 {
|
||||
compatible = "marvell,kirkwood-cache";
|
||||
reg = <0x20128 0x4>;
|
||||
};
|
30
Bindings/arm/msm/qcom,kpss-acc.txt
Normal file
30
Bindings/arm/msm/qcom,kpss-acc.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
|
||||
|
||||
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
|
||||
There is one ACC register region per CPU within the KPSS remapped region as
|
||||
well as an alias register region that remaps accesses to the ACC associated
|
||||
with the CPU accessing the region.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: should be one of:
|
||||
"qcom,kpss-acc-v1"
|
||||
"qcom,kpss-acc-v2"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the first element specifies the base address and size of
|
||||
the register region. An optional second element specifies
|
||||
the base address and size of the alias register region.
|
||||
|
||||
Example:
|
||||
|
||||
clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0x02088000 0x1000>,
|
||||
<0x02008000 0x1000>;
|
||||
};
|
35
Bindings/arm/msm/qcom,saw2.txt
Normal file
35
Bindings/arm/msm/qcom,saw2.txt
Normal file
@ -0,0 +1,35 @@
|
||||
SPM AVS Wrapper 2 (SAW2)
|
||||
|
||||
The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
|
||||
Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
|
||||
micro-controller that transitions a piece of hardware (like a processor or
|
||||
subsystem) into and out of low power modes via a direct connection to
|
||||
the PMIC. It can also be wired up to interact with other processors in the
|
||||
system, notifying them when a low power state is entered or exited.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: shall contain "qcom,saw2". A more specific value should be
|
||||
one of:
|
||||
"qcom,saw2-v1"
|
||||
"qcom,saw2-v1.1"
|
||||
"qcom,saw2-v2"
|
||||
"qcom,saw2-v2.1"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the first element specifies the base address and size of
|
||||
the register region. An optional second element specifies
|
||||
the base address and size of the alias register region.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
regulator@2099000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
};
|
63
Bindings/arm/omap/crossbar.txt
Normal file
63
Bindings/arm/omap/crossbar.txt
Normal file
@ -0,0 +1,63 @@
|
||||
Some socs have a large number of interrupts requests to service
|
||||
the needs of its many peripherals and subsystems. All of the
|
||||
interrupt lines from the subsystems are not needed at the same
|
||||
time, so they have to be muxed to the irq-controller appropriately.
|
||||
In such places a interrupt controllers are preceded by an CROSSBAR
|
||||
that provides flexibility in muxing the device requests to the controller
|
||||
inputs.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,irq-crossbar"
|
||||
- reg: Base address and the size of the crossbar registers.
|
||||
- ti,max-irqs: Total number of irqs available at the interrupt controller.
|
||||
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
|
||||
- ti,reg-size: Size of a individual register in bytes. Every individual
|
||||
register is assumed to be of same size. Valid sizes are 1, 2, 4.
|
||||
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
|
||||
crossbar. These interrupt lines are reserved in the soc,
|
||||
so crossbar bar driver should not consider them as free
|
||||
lines.
|
||||
|
||||
Optional properties:
|
||||
- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
|
||||
SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
|
||||
crossbar. These irqs have a crossbar register, but still cannot be used.
|
||||
|
||||
- ti,irqs-safe-map: integer which maps to a safe configuration to use
|
||||
when the interrupt controller irq is unused (when not provided, default is 0)
|
||||
|
||||
Examples:
|
||||
crossbar_mpu: @4a020000 {
|
||||
compatible = "ti,irq-crossbar";
|
||||
reg = <0x4a002a48 0x130>;
|
||||
ti,max-irqs = <160>;
|
||||
ti,max-crossbar-sources = <400>;
|
||||
ti,reg-size = <2>;
|
||||
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
|
||||
ti,irqs-skip = <10 133 139 140>;
|
||||
};
|
||||
|
||||
Consumer:
|
||||
========
|
||||
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
|
||||
Documentation/devicetree/bindings/arm/gic.txt for further details.
|
||||
|
||||
An interrupt consumer on an SoC using crossbar will use:
|
||||
interrupts = <GIC_SPI request_number interrupt_level>
|
||||
When the request number is between 0 to that described by
|
||||
"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
|
||||
request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
|
||||
quirky hardware mapping direct to GIC.
|
||||
|
||||
Example:
|
||||
device_x@0x4a023000 {
|
||||
/* Crossbar 8 used */
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
...
|
||||
};
|
||||
|
||||
device_y@0x4a033000 {
|
||||
/* Direct mapped GIC SPI 1 used */
|
||||
interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
|
||||
...
|
||||
};
|
22
Bindings/arm/omap/dmm.txt
Normal file
22
Bindings/arm/omap/dmm.txt
Normal file
@ -0,0 +1,22 @@
|
||||
OMAP Dynamic Memory Manager (DMM) bindings
|
||||
|
||||
The dynamic memory manager (DMM) is a module located immediately in front of the
|
||||
SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
|
||||
accesses such as priority generation amongst initiators, configuration of SDRAM
|
||||
interleaving, optimizing transfer of 2D block objects, and provide MMU-like page
|
||||
translation for initiators which need contiguous dma bus addresses.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "ti,omap4-dmm" for OMAP4 family
|
||||
Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family
|
||||
- reg: Contains DMM register address range (base address and length)
|
||||
- interrupts: Should contain an interrupt-specifier for DMM_IRQ.
|
||||
- ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm"
|
||||
|
||||
Example:
|
||||
|
||||
dmm@4e000000 {
|
||||
compatible = "ti,omap4-dmm";
|
||||
reg = <0x4e000000 0x800>;
|
||||
ti,hwmods = "dmm";
|
||||
};
|
65
Bindings/arm/omap/prcm.txt
Normal file
65
Bindings/arm/omap/prcm.txt
Normal file
@ -0,0 +1,65 @@
|
||||
OMAP PRCM bindings
|
||||
|
||||
Power Reset and Clock Manager lists the device clocks and clockdomains under
|
||||
a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
|
||||
each describing one module and the clock hierarchy under it. see [1] for
|
||||
documentation about the individual clock/clockdomain nodes.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/ti/*
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
"ti,am3-prcm"
|
||||
"ti,am3-scrm"
|
||||
"ti,am4-prcm"
|
||||
"ti,am4-scrm"
|
||||
"ti,omap2-prcm"
|
||||
"ti,omap2-scrm"
|
||||
"ti,omap3-prm"
|
||||
"ti,omap3-cm"
|
||||
"ti,omap3-scrm"
|
||||
"ti,omap4-cm1"
|
||||
"ti,omap4-prm"
|
||||
"ti,omap4-cm2"
|
||||
"ti,omap4-scrm"
|
||||
"ti,omap5-prm"
|
||||
"ti,omap5-cm-core-aon"
|
||||
"ti,omap5-scrm"
|
||||
"ti,omap5-cm-core"
|
||||
"ti,dra7-prm"
|
||||
"ti,dra7-cm-core-aon"
|
||||
"ti,dra7-cm-core"
|
||||
- reg: Contains PRCM module register address range
|
||||
(base address and length)
|
||||
- clocks: clocks for this module
|
||||
- clockdomains: clockdomains for this module
|
||||
|
||||
Example:
|
||||
|
||||
cm: cm@48004000 {
|
||||
compatible = "ti,omap3-cm";
|
||||
reg = <0x48004000 0x4000>;
|
||||
|
||||
cm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_clockdomains: clockdomains {
|
||||
};
|
||||
}
|
||||
|
||||
&cm_clocks {
|
||||
omap2_32k_fck: omap_32k_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>;
|
||||
};
|
||||
};
|
10
Bindings/arm/rockchip.txt
Normal file
10
Bindings/arm/rockchip.txt
Normal file
@ -0,0 +1,10 @@
|
||||
Rockchip platforms device tree bindings
|
||||
---------------------------------------
|
||||
|
||||
- bq Curie 2 tablet:
|
||||
Required root node properties:
|
||||
- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
|
||||
|
||||
- Radxa Rock board:
|
||||
Required root node properties:
|
||||
- compatible = "radxa,rock", "rockchip,rk3188";
|
16
Bindings/arm/rockchip/pmu.txt
Normal file
16
Bindings/arm/rockchip/pmu.txt
Normal file
@ -0,0 +1,16 @@
|
||||
Rockchip power-management-unit:
|
||||
-------------------------------
|
||||
|
||||
The pmu is used to turn off and on different power domains of the SoCs
|
||||
This includes the power to the CPU cores.
|
||||
|
||||
Required node properties:
|
||||
- compatible value : = "rockchip,rk3066-pmu";
|
||||
- reg : physical base address and the size of the registers window
|
||||
|
||||
Example:
|
||||
|
||||
pmu@20004000 {
|
||||
compatible = "rockchip,rk3066-pmu";
|
||||
reg = <0x20004000 0x100>;
|
||||
};
|
30
Bindings/arm/rockchip/smp-sram.txt
Normal file
30
Bindings/arm/rockchip/smp-sram.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Rockchip SRAM for smp bringup:
|
||||
------------------------------
|
||||
|
||||
Rockchip's smp-capable SoCs use the first part of the sram for the bringup
|
||||
of the cores. Once the core gets powered up it executes the code that is
|
||||
residing at the very beginning of the sram.
|
||||
|
||||
Therefore a reserved section sub-node has to be added to the mmio-sram
|
||||
declaration.
|
||||
|
||||
Required sub-node properties:
|
||||
- compatible : should be "rockchip,rk3066-smp-sram"
|
||||
|
||||
The rest of the properties should follow the generic mmio-sram discription
|
||||
found in ../../misc/sram.txt
|
||||
|
||||
Example:
|
||||
|
||||
sram: sram@10080000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x10080000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
smp-sram@10080000 {
|
||||
compatible = "rockchip,rk3066-smp-sram";
|
||||
reg = <0x10080000 0x50>;
|
||||
};
|
||||
};
|
51
Bindings/arm/samsung/pmu.txt
Normal file
51
Bindings/arm/samsung/pmu.txt
Normal file
@ -0,0 +1,51 @@
|
||||
SAMSUNG Exynos SoC series PMU Registers
|
||||
|
||||
Properties:
|
||||
- compatible : should contain two values. First value must be one from following list:
|
||||
- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
|
||||
- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
|
||||
- "samsung,exynos4212-pmu" - for Exynos4212 SoC,
|
||||
- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
|
||||
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
|
||||
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
|
||||
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
|
||||
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
|
||||
second value must be always "syscon".
|
||||
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
|
||||
The single specifier cell is used as index to list of clocks
|
||||
provided by PMU, which is currently:
|
||||
0 : SoC clock output (CLKOUT pin)
|
||||
|
||||
- clock-names : list of clock names for particular CLKOUT mux inputs in
|
||||
following format:
|
||||
"clkoutN", where N is a decimal number corresponding to
|
||||
CLKOUT mux control bits value for given input, e.g.
|
||||
"clkout0", "clkout7", "clkout15".
|
||||
|
||||
- clocks : list of phandles and specifiers to all input clocks listed in
|
||||
clock-names property.
|
||||
|
||||
Example :
|
||||
pmu_system_controller: system-controller@10040000 {
|
||||
compatible = "samsung,exynos5250-pmu", "syscon";
|
||||
reg = <0x10040000 0x5000>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
||||
"clkout4", "clkout8", "clkout9";
|
||||
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
||||
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
||||
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
|
||||
<&clock CLK_XUSBXTI>;
|
||||
};
|
||||
|
||||
Example of clock consumer :
|
||||
|
||||
usb3503: usb3503@08 {
|
||||
/* ... */
|
||||
clock-names = "refclk";
|
||||
clocks = <&pmu_system_controller 0>;
|
||||
/* ... */
|
||||
};
|
9
Bindings/arm/spear-misc.txt
Normal file
9
Bindings/arm/spear-misc.txt
Normal file
@ -0,0 +1,9 @@
|
||||
SPEAr Misc configuration
|
||||
===========================
|
||||
SPEAr SOCs have some miscellaneous registers which are used to configure
|
||||
few properties of different peripheral controllers.
|
||||
|
||||
misc node required properties:
|
||||
|
||||
- compatible Should be "st,spear1340-misc", "syscon".
|
||||
- reg: Address range of misc space upto 8K
|
15
Bindings/arm/sti.txt
Normal file
15
Bindings/arm/sti.txt
Normal file
@ -0,0 +1,15 @@
|
||||
ST STi Platforms Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
Boards with the ST STiH415 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih415";
|
||||
|
||||
Boards with the ST STiH416 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih416";
|
||||
|
||||
Boards with the ST STiH407 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih407";
|
||||
|
31
Bindings/ata/ahci-st.txt
Normal file
31
Bindings/ata/ahci-st.txt
Normal file
@ -0,0 +1,31 @@
|
||||
STMicroelectronics STi SATA controller
|
||||
|
||||
This binding describes a SATA device.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "st,sti-ahci"
|
||||
- reg : Physical base addresses and length of register sets
|
||||
- interrupts : Interrupt associated with the SATA device
|
||||
- interrupt-names : Associated name must be; "hostc"
|
||||
- resets : The power-down and soft-reset lines of SATA IP
|
||||
- reset-names : Associated names must be; "pwr-dwn" and "sw-rst"
|
||||
- clocks : The phandle for the clock
|
||||
- clock-names : Associated name must be; "ahci_clk"
|
||||
- phys : The phandle for the PHY device
|
||||
- phy-names : Associated name must be; "ahci_phy"
|
||||
|
||||
Example:
|
||||
|
||||
sata0: sata@fe380000 {
|
||||
compatible = "st,sti-ahci";
|
||||
reg = <0xfe380000 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
|
||||
phy-names = "ahci_phy";
|
||||
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
|
||||
<&softreset STIH416_SATA0_SOFTRESET>;
|
||||
reset-names = "pwr-dwn", "sw-rst";
|
||||
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
};
|
79
Bindings/ata/apm-xgene.txt
Normal file
79
Bindings/ata/apm-xgene.txt
Normal file
@ -0,0 +1,79 @@
|
||||
* APM X-Gene 6.0 Gb/s SATA host controller nodes
|
||||
|
||||
SATA host controller nodes are defined to describe on-chip Serial ATA
|
||||
controllers. Each SATA controller (pair of ports) have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall contain:
|
||||
* "apm,xgene-ahci"
|
||||
- reg : First memory resource shall be the AHCI memory
|
||||
resource.
|
||||
Second memory resource shall be the host controller
|
||||
core memory resource.
|
||||
Third memory resource shall be the host controller
|
||||
diagnostic memory resource.
|
||||
4th memory resource shall be the host controller
|
||||
AXI memory resource.
|
||||
5th optional memory resource shall be the host
|
||||
controller MUX memory resource if required.
|
||||
- interrupts : Interrupt-specifier for SATA host controller IRQ.
|
||||
- clocks : Reference to the clock entry.
|
||||
- phys : A list of phandles + phy-specifiers, one for each
|
||||
entry in phy-names.
|
||||
- phy-names : Should contain:
|
||||
* "sata-phy" for the SATA 6.0Gbps PHY
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if dma operations are coherent
|
||||
- status : Shall be "ok" if enabled or "disabled" if disabled.
|
||||
Default is "ok".
|
||||
|
||||
Example:
|
||||
sataclk: sataclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sataclk";
|
||||
};
|
||||
|
||||
phy2: phy@1f22a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f22a000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
phy3: phy@1f23a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f23a000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
sata2: sata@1a400000 {
|
||||
compatible = "apm,xgene-ahci";
|
||||
reg = <0x0 0x1a400000 0x0 0x1000>,
|
||||
<0x0 0x1f220000 0x0 0x1000>,
|
||||
<0x0 0x1f22d000 0x0 0x1000>,
|
||||
<0x0 0x1f22e000 0x0 0x1000>,
|
||||
<0x0 0x1f227000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x87 0x4>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
clocks = <&sataclk 0>;
|
||||
phys = <&phy2 0>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
|
||||
sata3: sata@1a800000 {
|
||||
compatible = "apm,xgene-ahci-pcie";
|
||||
reg = <0x0 0x1a800000 0x0 0x1000>,
|
||||
<0x0 0x1f230000 0x0 0x1000>,
|
||||
<0x0 0x1f23d000 0x0 0x1000>,
|
||||
<0x0 0x1f23e000 0x0 0x1000>,
|
||||
<0x0 0x1f237000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x88 0x4>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
clocks = <&sataclk 0>;
|
||||
phys = <&phy3 0>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
36
Bindings/ata/imx-sata.txt
Normal file
36
Bindings/ata/imx-sata.txt
Normal file
@ -0,0 +1,36 @@
|
||||
* Freescale i.MX AHCI SATA Controller
|
||||
|
||||
The Freescale i.MX SATA controller mostly conforms to the AHCI interface
|
||||
with some special extensions at integration level.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of the following:
|
||||
- "fsl,imx53-ahci" for i.MX53 SATA controller
|
||||
- "fsl,imx6q-ahci" for i.MX6Q SATA controller
|
||||
- interrupts : interrupt mapping for SATA IRQ
|
||||
- reg : registers mapping
|
||||
- clocks : list of clock specifiers, must contain an entry for each
|
||||
required entry in clock-names
|
||||
- clock-names : should include "sata", "sata_ref" and "ahb" entries
|
||||
|
||||
Optional properties:
|
||||
- fsl,transmit-level-mV : transmit voltage level, in millivolts.
|
||||
- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels
|
||||
- fsl,transmit-atten-16ths : transmit attenuation, in 16ths
|
||||
- fsl,receive-eq-mdB : receive equalisation, in milli-decibels
|
||||
Please refer to the technical documentation or the driver source code
|
||||
for the list of legal values for these options.
|
||||
- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA
|
||||
link.
|
||||
|
||||
Examples:
|
||||
|
||||
sata@02200000 {
|
||||
compatible = "fsl,imx6q-ahci";
|
||||
reg = <0x02200000 0x4000>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6QDL_CLK_SATA>,
|
||||
<&clks IMX6QDL_CLK_SATA_REF_100M>,
|
||||
<&clks IMX6QDL_CLK_AHB>;
|
||||
clock-names = "sata", "sata_ref", "ahb";
|
||||
};
|
30
Bindings/ata/tegra-sata.txt
Normal file
30
Bindings/ata/tegra-sata.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Tegra124 SoC SATA AHCI controller
|
||||
|
||||
Required properties :
|
||||
- compatible : "nvidia,tegra124-ahci".
|
||||
- reg : Should contain 2 entries:
|
||||
- AHCI register set (SATA BAR5)
|
||||
- SATA register set
|
||||
- interrupts : Defines the interrupt used by SATA
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
- sata
|
||||
- sata-oob
|
||||
- cml1
|
||||
- pll_e
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- sata
|
||||
- sata-oob
|
||||
- sata-cold
|
||||
- phys : Must contain an entry for each entry in phy-names.
|
||||
See ../phy/phy-bindings.txt for details.
|
||||
- phy-names : Must include the following entries:
|
||||
- sata-phy : XUSB PADCTL SATA PHY
|
||||
- hvdd-supply : Defines the SATA HVDD regulator
|
||||
- vddio-supply : Defines the SATA VDDIO regulator
|
||||
- avdd-supply : Defines the SATA AVDD regulator
|
||||
- target-5v-supply : Defines the SATA 5V power regulator
|
||||
- target-12v-supply : Defines the SATA 12V power regulator
|
30
Bindings/bus/brcm,gisb-arb.txt
Normal file
30
Bindings/bus/brcm,gisb-arb.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Broadcom GISB bus Arbiter controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,gisb-arb"
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this arbiter gets interrupt line from
|
||||
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
|
||||
the parent interrupt controller
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
|
||||
masters are valid at the system level
|
||||
- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
|
||||
masters. Should match the number of bits set in brcm,gisb-master-mask and
|
||||
the order in which they appear
|
||||
|
||||
Example:
|
||||
|
||||
gisb-arb@f0400000 {
|
||||
compatible = "brcm,gisb-arb";
|
||||
reg = <0xf0400000 0x800>;
|
||||
interrupts = <0>, <2>;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
|
||||
brcm,gisb-arb-master-mask = <0x7>;
|
||||
brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
|
||||
};
|
34
Bindings/clock/arm-integrator.txt
Normal file
34
Bindings/clock/arm-integrator.txt
Normal file
@ -0,0 +1,34 @@
|
||||
Clock bindings for ARM Integrator and Versatile Core Module clocks
|
||||
|
||||
Auxilary Oscillator Clock
|
||||
|
||||
This is a configurable clock fed from a 24 MHz chrystal,
|
||||
used for generating e.g. video clocks. It is located on the
|
||||
core module and there is only one of these.
|
||||
|
||||
This clock node *must* be a subnode of the core module, since
|
||||
it obtains the base address for it's address range from its
|
||||
parent node.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Optional properties:
|
||||
- clocks: parent clock(s)
|
||||
|
||||
Example:
|
||||
|
||||
core-module@10000000 {
|
||||
xtal24mhz: xtal24mhz@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
auxosc: cm_aux_osc@25M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "arm,integrator-cm-auxosc";
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
};
|
35
Bindings/clock/clk-palmas-clk32kg-clocks.txt
Normal file
35
Bindings/clock/clk-palmas-clk32kg-clocks.txt
Normal file
@ -0,0 +1,35 @@
|
||||
* Palmas 32KHz clocks *
|
||||
|
||||
Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
|
||||
|
||||
This binding uses the common clock binding ./clock-bindings.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible : "ti,palmas-clk32kg" for clk32kg clock
|
||||
"ti,palmas-clk32kgaudio" for clk32kgaudio clock
|
||||
- #clock-cells : shall be set to 0.
|
||||
|
||||
Optional property:
|
||||
- ti,external-sleep-control: The external enable input pins controlled the
|
||||
enable/disable of clocks. The external enable input pins ENABLE1,
|
||||
ENABLE2 and NSLEEP. The valid values for the external pins are:
|
||||
PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
|
||||
PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
|
||||
PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
|
||||
Option 0 or missing this property means the clock is enabled/disabled
|
||||
via register access and these pins do not have any control.
|
||||
The macros of external control pins for DTS is defined at
|
||||
dt-bindings/mfd/palmas.h
|
||||
|
||||
Example:
|
||||
#include <dt-bindings/mfd/palmas.h>
|
||||
...
|
||||
palmas: tps65913@58 {
|
||||
...
|
||||
clk32kg: palmas_clk32k@0 {
|
||||
compatible = "ti,palmas-clk32kg";
|
||||
#clock-cells = <0>;
|
||||
ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
|
||||
};
|
||||
...
|
||||
};
|
53
Bindings/clock/clk-s5pv210-audss.txt
Normal file
53
Bindings/clock/clk-s5pv210-audss.txt
Normal file
@ -0,0 +1,53 @@
|
||||
* Samsung Audio Subsystem Clock Controller
|
||||
|
||||
The Samsung Audio Subsystem clock controller generates and supplies clocks
|
||||
to Audio Subsystem block available in the S5PV210 and compatible SoCs.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,s5pv210-audss-clock".
|
||||
- reg: physical base address and length of the controller's register set.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks:
|
||||
- hclk: AHB bus clock of the Audio Subsystem.
|
||||
- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
|
||||
not specified (i.e. xusbxti is used for PLL reference), it is fixed to
|
||||
a clock named "xxti".
|
||||
- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
|
||||
- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
|
||||
specified, it is fixed to a clock named "iiscdclk0".
|
||||
- sclk_audio0: Audio bus clock, parent of mout_i2s.
|
||||
|
||||
- clock-names: Aliases for the above clocks. They should be "hclk",
|
||||
"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example: Clock controller node.
|
||||
|
||||
clk_audss: clock-controller@c0900000 {
|
||||
compatible = "samsung,s5pv210-audss-clock";
|
||||
reg = <0xc0900000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "hclk", "xxti",
|
||||
"fout_epll", "sclk_audio0";
|
||||
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
|
||||
<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
|
||||
};
|
||||
|
||||
Example: I2S controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
/* ... */
|
||||
clock-names = "iis", "i2s_opclk0",
|
||||
"i2s_opclk1";
|
||||
clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
|
||||
<&clk_audss CLK_DOUT_AUD_BUS>;
|
||||
/* ... */
|
||||
};
|
19
Bindings/clock/clps711x-clock.txt
Normal file
19
Bindings/clock/clps711x-clock.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* Clock bindings for the Cirrus Logic CLPS711X CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall contain "cirrus,clps711x-clk".
|
||||
- reg : Address of the internal register set.
|
||||
- startup-frequency: Factory set CPU startup frequency in HZ.
|
||||
- #clock-cells : Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
|
||||
for the full list of CLPS711X clock IDs.
|
||||
|
||||
Example:
|
||||
clks: clks@80000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
|
||||
reg = <0x80000000 0xc000>;
|
||||
startup-frequency = <73728000>;
|
||||
};
|
41
Bindings/clock/exynos3250-clock.txt
Normal file
41
Bindings/clock/exynos3250-clock.txt
Normal file
@ -0,0 +1,41 @@
|
||||
* Samsung Exynos3250 Clock Controller
|
||||
|
||||
The Exynos3250 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos3250 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos3250.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
cmu: clock-controller@10030000 {
|
||||
compatible = "samsung,exynos3250-cmu";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13800000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
190
Bindings/clock/exynos5260-clock.txt
Normal file
190
Bindings/clock/exynos5260-clock.txt
Normal file
@ -0,0 +1,190 @@
|
||||
* Samsung Exynos5260 Clock Controller
|
||||
|
||||
Exynos5260 has 13 clock controllers which are instantiated
|
||||
independently from the device-tree. These clock controllers
|
||||
generate and supply clocks to various hardware blocks within
|
||||
the SoC.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use
|
||||
this identifier to specify the clock which they consume. All
|
||||
available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5260-clk.h header and can be used in
|
||||
device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It
|
||||
is expected that they are defined using standard clock bindings
|
||||
with following clock-output-names:
|
||||
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
- "xrtcxti" - input clock from XRTCXTI
|
||||
- "ioclk_pcm_extclk" - pcm external operation clock
|
||||
- "ioclk_spdif_extclk" - spdif external operation clock
|
||||
- "ioclk_i2s_cdclk" - i2s0 codec clock
|
||||
|
||||
Phy clocks:
|
||||
|
||||
There are several clocks which are generated by specific PHYs.
|
||||
These clocks are fed into the clock controller and then routed to
|
||||
the hardware blocks. These clocks are defined as fixed clocks in the
|
||||
driver with following names:
|
||||
|
||||
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
|
||||
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
|
||||
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
|
||||
- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
|
||||
- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
|
||||
- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
|
||||
- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
|
||||
- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
|
||||
- "phyclk_dptx_phy_clk_div2"
|
||||
- "phyclk_mipi_dphy_4l_m_rxclkesc0"
|
||||
- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
|
||||
- "phyclk_usbhost20_phy_freeclk"
|
||||
- "phyclk_usbhost20_phy_clk48mohci"
|
||||
- "phyclk_usbdrd30_udrd30_pipe_pclk"
|
||||
- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
|
||||
|
||||
Required Properties for Clock Controller:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
1) "samsung,exynos5260-clock-top"
|
||||
2) "samsung,exynos5260-clock-peri"
|
||||
3) "samsung,exynos5260-clock-egl"
|
||||
4) "samsung,exynos5260-clock-kfc"
|
||||
5) "samsung,exynos5260-clock-g2d"
|
||||
6) "samsung,exynos5260-clock-mif"
|
||||
7) "samsung,exynos5260-clock-mfc"
|
||||
8) "samsung,exynos5260-clock-g3d"
|
||||
9) "samsung,exynos5260-clock-fsys"
|
||||
10) "samsung,exynos5260-clock-aud"
|
||||
11) "samsung,exynos5260-clock-isp"
|
||||
12) "samsung,exynos5260-clock-gscl"
|
||||
13) "samsung,exynos5260-clock-disp"
|
||||
|
||||
- reg: physical base address of the controller and the length of
|
||||
memory mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks: list of clock identifiers which are fed as the input to
|
||||
the given clock controller. Please refer the next section to find
|
||||
the input clocks for a given controller.
|
||||
|
||||
- clock-names: list of names of clocks which are fed as the input
|
||||
to the given clock controller.
|
||||
|
||||
Input clocks for top clock controller:
|
||||
- fin_pll
|
||||
- dout_mem_pll
|
||||
- dout_bus_pll
|
||||
- dout_media_pll
|
||||
|
||||
Input clocks for peri clock controller:
|
||||
- fin_pll
|
||||
- ioclk_pcm_extclk
|
||||
- ioclk_i2s_cdclk
|
||||
- ioclk_spdif_extclk
|
||||
- phyclk_hdmi_phy_ref_cko
|
||||
- dout_aclk_peri_66
|
||||
- dout_sclk_peri_uart0
|
||||
- dout_sclk_peri_uart1
|
||||
- dout_sclk_peri_uart2
|
||||
- dout_sclk_peri_spi0_b
|
||||
- dout_sclk_peri_spi1_b
|
||||
- dout_sclk_peri_spi2_b
|
||||
- dout_aclk_peri_aud
|
||||
- dout_sclk_peri_spi0_b
|
||||
|
||||
Input clocks for egl clock controller:
|
||||
- fin_pll
|
||||
- dout_bus_pll
|
||||
|
||||
Input clocks for kfc clock controller:
|
||||
- fin_pll
|
||||
- dout_media_pll
|
||||
|
||||
Input clocks for g2d clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_g2d_333
|
||||
|
||||
Input clocks for mif clock controller:
|
||||
- fin_pll
|
||||
|
||||
Input clocks for mfc clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_mfc_333
|
||||
|
||||
Input clocks for g3d clock controller:
|
||||
- fin_pll
|
||||
|
||||
Input clocks for fsys clock controller:
|
||||
- fin_pll
|
||||
- phyclk_usbhost20_phy_phyclock
|
||||
- phyclk_usbhost20_phy_freeclk
|
||||
- phyclk_usbhost20_phy_clk48mohci
|
||||
- phyclk_usbdrd30_udrd30_pipe_pclk
|
||||
- phyclk_usbdrd30_udrd30_phyclock
|
||||
- dout_aclk_fsys_200
|
||||
|
||||
Input clocks for aud clock controller:
|
||||
- fin_pll
|
||||
- fout_aud_pll
|
||||
- ioclk_i2s_cdclk
|
||||
- ioclk_pcm_extclk
|
||||
|
||||
Input clocks for isp clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_isp1_266
|
||||
- dout_aclk_isp1_400
|
||||
- mout_aclk_isp1_266
|
||||
|
||||
Input clocks for gscl clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_gscl_400
|
||||
- dout_aclk_gscl_333
|
||||
|
||||
Input clocks for disp clock controller:
|
||||
- fin_pll
|
||||
- phyclk_dptx_phy_ch3_txd_clk
|
||||
- phyclk_dptx_phy_ch2_txd_clk
|
||||
- phyclk_dptx_phy_ch1_txd_clk
|
||||
- phyclk_dptx_phy_ch0_txd_clk
|
||||
- phyclk_hdmi_phy_tmds_clko
|
||||
- phyclk_hdmi_phy_ref_clko
|
||||
- phyclk_hdmi_phy_pixel_clko
|
||||
- phyclk_hdmi_link_o_tmds_clkhi
|
||||
- phyclk_mipi_dphy_4l_m_txbyte_clkhs
|
||||
- phyclk_dptx_phy_o_ref_clk_24m
|
||||
- phyclk_dptx_phy_clk_div2
|
||||
- phyclk_mipi_dphy_4l_m_rxclkesc0
|
||||
- phyclk_hdmi_phy_ref_cko
|
||||
- ioclk_spdif_extclk
|
||||
- dout_aclk_peri_aud
|
||||
- dout_aclk_disp_222
|
||||
- dout_sclk_disp_pixel
|
||||
- dout_aclk_disp_333
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock_mfc: clock-controller@11090000 {
|
||||
compatible = "samsung,exynos5260-clock-mfc";
|
||||
clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
|
||||
clock-names = "fin_pll", "dout_aclk_mfc_333";
|
||||
reg = <0x11090000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the
|
||||
peri clock controller. Refer to the standard clock bindings for
|
||||
information about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 146 0>;
|
||||
clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
45
Bindings/clock/exynos5410-clock.txt
Normal file
45
Bindings/clock/exynos5410-clock.txt
Normal file
@ -0,0 +1,45 @@
|
||||
* Samsung Exynos5410 Clock Controller
|
||||
|
||||
The Exynos5410 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5410 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,exynos5410-clock"
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5410.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clock:
|
||||
|
||||
There is clock that is generated outside the SoC. It
|
||||
is expected that it is defined using standard clock bindings
|
||||
with following clock-output-name:
|
||||
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5410-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
31
Bindings/clock/hix5hd2-clock.txt
Normal file
31
Bindings/clock/hix5hd2-clock.txt
Normal file
@ -0,0 +1,31 @@
|
||||
* Hisilicon Hix5hd2 Clock Controller
|
||||
|
||||
The hix5hd2 clock controller generates and supplies clock to various
|
||||
controllers within the hix5hd2 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "hisilicon,hix5hd2-clock"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
|
||||
|
||||
Examples:
|
||||
clock: clock@f8a22000 {
|
||||
compatible = "hisilicon,hix5hd2-clock";
|
||||
reg = <0xf8a22000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: uart@f8b00000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8b00000 0x1000>;
|
||||
interrupts = <0 49 4>;
|
||||
clocks = <&clock HIX5HD2_FIXED_83M>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
26
Bindings/clock/imx1-clock.txt
Normal file
26
Bindings/clock/imx1-clock.txt
Normal file
@ -0,0 +1,26 @@
|
||||
* Clock bindings for Freescale i.MX1 CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx1-ccm".
|
||||
- reg: Address and length of the register set.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
|
||||
for the full list of i.MX1 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@0021b000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "fsl,imx1-ccm";
|
||||
reg = <0x0021b000 0x1000>;
|
||||
};
|
||||
|
||||
pwm: pwm@00208000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx1-pwm";
|
||||
reg = <0x00208000 0x1000>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
28
Bindings/clock/imx21-clock.txt
Normal file
28
Bindings/clock/imx21-clock.txt
Normal file
@ -0,0 +1,28 @@
|
||||
* Clock bindings for Freescale i.MX21
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx21-ccm".
|
||||
- reg : Address and length of the register set.
|
||||
- interrupts : Should contain CCM interrupt.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
|
||||
for the full list of i.MX21 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx21-ccm";
|
||||
reg = <0x10027000 0x800>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX21_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
13
Bindings/clock/imx6sx-clock.txt
Normal file
13
Bindings/clock/imx6sx-clock.txt
Normal file
@ -0,0 +1,13 @@
|
||||
* Clock bindings for Freescale i.MX6 SoloX
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sx-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
|
||||
for the full list of i.MX6 SoloX clock IDs.
|
29
Bindings/clock/lsi,axm5516-clks.txt
Normal file
29
Bindings/clock/lsi,axm5516-clks.txt
Normal file
@ -0,0 +1,29 @@
|
||||
AXM5516 clock driver bindings
|
||||
-----------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain "lsi,axm5516-clks"
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
The consumer specifies the desired clock by having the clock ID in its "clocks"
|
||||
phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
|
||||
supported clock IDs.
|
||||
|
||||
Example:
|
||||
|
||||
clks: clock-controller@2010020000 {
|
||||
compatible = "lsi,axm5516-clks";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x20 0x10020000 0 0x20000>;
|
||||
};
|
||||
|
||||
serial0: uart@2010080000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x20 0x10080000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
48
Bindings/clock/moxa,moxart-clock.txt
Normal file
48
Bindings/clock/moxa,moxart-clock.txt
Normal file
@ -0,0 +1,48 @@
|
||||
Device Tree Clock bindings for arch-moxart
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
MOXA ART SoCs allow to determine PLL output and APB frequencies
|
||||
by reading registers holding multiplier and divisor information.
|
||||
|
||||
|
||||
PLL:
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "moxa,moxart-pll-clock"
|
||||
- #clock-cells : Should be 0
|
||||
- reg : Should contain registers location and length
|
||||
- clocks : Should contain phandle + clock-specifier for the parent clock
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : Should contain clock name
|
||||
|
||||
|
||||
APB:
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "moxa,moxart-apb-clock"
|
||||
- #clock-cells : Should be 0
|
||||
- reg : Should contain registers location and length
|
||||
- clocks : Should contain phandle + clock-specifier for the parent clock
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : Should contain clock name
|
||||
|
||||
|
||||
For example:
|
||||
|
||||
clk_pll: clk_pll@98100000 {
|
||||
compatible = "moxa,moxart-pll-clock";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x98100000 0x34>;
|
||||
};
|
||||
|
||||
clk_apb: clk_apb@98100000 {
|
||||
compatible = "moxa,moxart-apb-clock";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x98100000 0x34>;
|
||||
clocks = <&clk_pll>;
|
||||
};
|
142
Bindings/clock/qoriq-clock.txt
Normal file
142
Bindings/clock/qoriq-clock.txt
Normal file
@ -0,0 +1,142 @@
|
||||
* Clock Block on Freescale CoreNet Platforms
|
||||
|
||||
Freescale CoreNet chips take primary clocking input from the external
|
||||
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
|
||||
multiple phase locked loops (PLL) to create a variety of frequencies
|
||||
which can then be passed to a variety of internal logic, including
|
||||
cores and peripheral IP blocks.
|
||||
Please refer to the Reference Manual for details.
|
||||
|
||||
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
|
||||
which the chip complies.
|
||||
|
||||
Chassis Version Example Chips
|
||||
--------------- -------------
|
||||
1.0 p4080, p5020, p5040
|
||||
2.0 t4240, b4860, t1040
|
||||
|
||||
1. Clock Block Binding
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain a specific clock block compatible string
|
||||
and a single chassis clock compatible string.
|
||||
Clock block strings include, but not limited to, one of the:
|
||||
* "fsl,p2041-clockgen"
|
||||
* "fsl,p3041-clockgen"
|
||||
* "fsl,p4080-clockgen"
|
||||
* "fsl,p5020-clockgen"
|
||||
* "fsl,p5040-clockgen"
|
||||
* "fsl,t4240-clockgen"
|
||||
* "fsl,b4420-clockgen"
|
||||
* "fsl,b4860-clockgen"
|
||||
Chassis clock strings include:
|
||||
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
|
||||
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
|
||||
- reg: Describes the address of the device's resources within the
|
||||
address space defined by its parent bus, and resource zero
|
||||
represents the clock register set
|
||||
- clock-frequency: Input system clock frequency
|
||||
|
||||
Recommended properties:
|
||||
- ranges: Allows valid translation between child's address space and
|
||||
parent's. Must be present if the device has sub-nodes.
|
||||
- #address-cells: Specifies the number of cells used to represent
|
||||
physical base addresses. Must be present if the device has
|
||||
sub-nodes and set to 1 if present
|
||||
- #size-cells: Specifies the number of cells used to represent
|
||||
the size of an address. Must be present if the device has
|
||||
sub-nodes and set to 1 if present
|
||||
|
||||
2. Clock Provider/Consumer Binding
|
||||
|
||||
Most of the bindings are from the common clock binding[1].
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : Should include one of the following:
|
||||
* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
|
||||
* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
|
||||
* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
|
||||
* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
|
||||
* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
|
||||
It takes parent's clock-frequency as its clock.
|
||||
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
|
||||
It takes parent's clock-frequency as its clock.
|
||||
- #clock-cells: From common clock binding. The number of cells in a
|
||||
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
|
||||
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
|
||||
For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
|
||||
clock-specifier cell may take the following values:
|
||||
* 0 - equal to the PLL frequency
|
||||
* 1 - equal to the PLL frequency divided by 2
|
||||
* 2 - equal to the PLL frequency divided by 4
|
||||
|
||||
Recommended properties:
|
||||
- clocks: Should be the phandle of input parent clock
|
||||
- clock-names: From common clock binding, indicates the clock name
|
||||
- clock-output-names: From common clock binding, indicates the names of
|
||||
output clocks
|
||||
- reg: Should be the offset and length of clock block base address.
|
||||
The length should be 4.
|
||||
|
||||
Example for clock block and clock provider:
|
||||
/ {
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
clock-frequency = <133333333>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
};
|
||||
}
|
||||
|
||||
Example for clock consumer:
|
||||
|
||||
/ {
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
...
|
||||
clocks = <&mux0>;
|
||||
...
|
||||
};
|
||||
}
|
41
Bindings/clock/renesas,r8a7740-cpg-clocks.txt
Normal file
41
Bindings/clock/renesas,r8a7740-cpg-clocks.txt
Normal file
@ -0,0 +1,41 @@
|
||||
These bindings should be considered EXPERIMENTAL for now.
|
||||
|
||||
* Renesas R8A7740 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
|
||||
and several fixed ratio and variable ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7740-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the three parent clocks
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
|
||||
"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
|
||||
|
||||
- renesas,mode: board-specific settings of the MD_CK* bits
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1",
|
||||
"pllc2", "r",
|
||||
"usb24s",
|
||||
"i", "zg", "b", "m1", "hp",
|
||||
"hpp", "usbp", "s", "zb", "m3",
|
||||
"cp";
|
||||
};
|
||||
|
||||
&cpg_clocks {
|
||||
renesas,mode = <0x05>;
|
||||
};
|
27
Bindings/clock/renesas,r8a7779-cpg-clocks.txt
Normal file
27
Bindings/clock/renesas,r8a7779-cpg-clocks.txt
Normal file
@ -0,0 +1,27 @@
|
||||
* Renesas R8A7779 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7779. It includes one PLL and
|
||||
several fixed ratio dividers
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7779-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clock
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "plla",
|
||||
"z", "zs", "s", "s1", "p", "b", "out".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7779-cpg-clocks";
|
||||
reg = <0 0xffc80000 0 0x30>;
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
|
||||
"b", "out";
|
||||
};
|
29
Bindings/clock/renesas,rz-cpg-clocks.txt
Normal file
29
Bindings/clock/renesas,rz-cpg-clocks.txt
Normal file
@ -0,0 +1,29 @@
|
||||
* Renesas RZ Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
|
||||
CPU and GPU clocks, and several fixed ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of
|
||||
- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
|
||||
- "renesas,rz-cpg-clocks" for the generic RZ CPG
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
- clocks: References to possible parent clocks. Order must match clock modes
|
||||
in the datasheet. For the r7s72100, this is extal, usb_x1.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "pll",
|
||||
"i", and "g"
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@fcfe0000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "renesas,r7s72100-cpg-clocks",
|
||||
"renesas,rz-cpg-clocks";
|
||||
reg = <0xfcfe0000 0x18>;
|
||||
clocks = <&extal_clk>, <&usb_x1_clk>;
|
||||
clock-output-names = "pll", "i", "g";
|
||||
};
|
61
Bindings/clock/rockchip,rk3188-cru.txt
Normal file
61
Bindings/clock/rockchip,rk3188-cru.txt
Normal file
@ -0,0 +1,61 @@
|
||||
* Rockchip RK3188/RK3066 Clock and Reset Unit
|
||||
|
||||
The RK3188/RK3066 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
|
||||
"rockchip,rk3066a-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "xin27m" - 27mhz crystal input on rk3066 - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_cif0" - external camera clock - optional,
|
||||
- "ext_rmii" - external RMII clock - optional,
|
||||
- "ext_jtag" - externalJTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
61
Bindings/clock/rockchip,rk3288-cru.txt
Normal file
61
Bindings/clock/rockchip,rk3288-cru.txt
Normal file
@ -0,0 +1,61 @@
|
||||
* Rockchip RK3288 Clock and Reset Unit
|
||||
|
||||
The RK3288 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3288-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
50
Bindings/clock/samsung,s3c2410-clock.txt
Normal file
50
Bindings/clock/samsung,s3c2410-clock.txt
Normal file
@ -0,0 +1,50 @@
|
||||
* Samsung S3C2410 Clock Controller
|
||||
|
||||
The S3C2410 clock controller generates and supplies clock to various controllers
|
||||
within the SoC. The clock binding described here is applicable to the s3c2410,
|
||||
s3c2440 and s3c2442 SoCs in the s3c24x family.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
|
||||
- "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
|
||||
- "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Some of the clocks are available only
|
||||
on a particular SoC.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s3c2410.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
The xti clock used as input for the plls is generated outside the SoC. It is
|
||||
expected that is are defined using standard clock bindings with a
|
||||
clock-output-names value of "xti".
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clocks: clock-controller@4c000000 {
|
||||
compatible = "samsung,s3c2410-clock";
|
||||
reg = <0x4c000000 0x20>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
serial@50004000 {
|
||||
compatible = "samsung,s3c2440-uart";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1 23 3 4>, <1 23 4 4>;
|
||||
clock-names = "uart", "clk_uart_baud2";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
50
Bindings/clock/samsung,s3c2412-clock.txt
Normal file
50
Bindings/clock/samsung,s3c2412-clock.txt
Normal file
@ -0,0 +1,50 @@
|
||||
* Samsung S3C2412 Clock Controller
|
||||
|
||||
The S3C2412 clock controller generates and supplies clock to various controllers
|
||||
within the SoC. The clock binding described here is applicable to the s3c2412
|
||||
and s3c2413 SoCs in the s3c24x family.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,s3c2412-clock"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Some of the clocks are available only
|
||||
on a particular SoC.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s3c2412.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xti" - crystal input - required,
|
||||
- "ext" - external clock source - optional,
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clocks: clock-controller@4c000000 {
|
||||
compatible = "samsung,s3c2412-clock";
|
||||
reg = <0x4c000000 0x20>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
serial@50004000 {
|
||||
compatible = "samsung,s3c2412-uart";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1 23 3 4>, <1 23 4 4>;
|
||||
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
|
||||
<&clocks SCLK_UART>;
|
||||
status = "disabled";
|
||||
};
|
56
Bindings/clock/samsung,s3c2443-clock.txt
Normal file
56
Bindings/clock/samsung,s3c2443-clock.txt
Normal file
@ -0,0 +1,56 @@
|
||||
* Samsung S3C2443 Clock Controller
|
||||
|
||||
The S3C2443 clock controller generates and supplies clock to various controllers
|
||||
within the SoC. The clock binding described here is applicable to all SoCs in
|
||||
the s3c24x family starting with the s3c2443.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
|
||||
- "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
|
||||
- "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Some of the clocks are available only
|
||||
on a particular SoC.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s3c2443.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xti" - crystal input - required,
|
||||
- "ext" - external clock source - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_uart" - external uart clock - optional,
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clocks: clock-controller@4c000000 {
|
||||
compatible = "samsung,s3c2416-clock";
|
||||
reg = <0x4c000000 0x40>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
serial@50004000 {
|
||||
compatible = "samsung,s3c2440-uart";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1 23 3 4>, <1 23 4 4>;
|
||||
clock-names = "uart", "clk_uart_baud2",
|
||||
"clk_uart_baud3";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
|
||||
<&clocks SCLK_UART>;
|
||||
status = "disabled";
|
||||
};
|
78
Bindings/clock/samsung,s5pv210-clock.txt
Normal file
78
Bindings/clock/samsung,s5pv210-clock.txt
Normal file
@ -0,0 +1,78 @@
|
||||
* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
|
||||
|
||||
Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
|
||||
controller, which generates and supplies clock to various controllers
|
||||
within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of following:
|
||||
- "samsung,s5pv210-clock" : for clock controller of Samsung
|
||||
S5PC110/S5PV210 SoCs,
|
||||
- "samsung,s5p6442-clock" : for clock controller of Samsung
|
||||
S5P6442 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xxti": external crystal oscillator connected to XXTI and XXTO pins of
|
||||
the SoC,
|
||||
- "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
|
||||
pins of the SoC,
|
||||
|
||||
A subset of above clocks available on given board shall be specified in
|
||||
board device tree, including the system base clock, as selected by XOM[0]
|
||||
pin of the SoC. Refer to generic fixed rate clock bindings
|
||||
documentation[1] for more information how to specify these clocks.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clock: clock-controller@7e00f000 {
|
||||
compatible = "samsung,s5pv210-clock";
|
||||
reg = <0x7e00f000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: Required external clocks:
|
||||
|
||||
xxti: clock-xxti {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xxti";
|
||||
clock-frequency = <24000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
xusbxti: clock-xusbxti {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
uart0: serial@e2900000 {
|
||||
compatible = "samsung,s5pv210-uart";
|
||||
reg = <0xe2900000 0x400>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <10>;
|
||||
clock-names = "uart", "clk_uart_baud0",
|
||||
"clk_uart_baud1";
|
||||
clocks = <&clocks UART0>, <&clocks UART0>,
|
||||
<&clocks SCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
49
Bindings/clock/st/st,clkgen-divmux.txt
Normal file
49
Bindings/clock/st/st,clkgen-divmux.txt
Normal file
@ -0,0 +1,49 @@
|
||||
Binding for a ST divider and multiplexer clock driver.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Base address is located to the parent node. See clock binding[2]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
|
||||
"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 1.
|
||||
|
||||
- clocks : From common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
||||
clockgen-a@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
clk_m_a1_div1: clk-m-a1-div1 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c32-odf1",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&clk_m_a1_osc_prediv>,
|
||||
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
|
||||
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
|
||||
|
||||
clock-output-names = "clk-m-rx-icn-ts",
|
||||
"clk-m-rx-icn-vdp-0",
|
||||
"", /* unused */
|
||||
"clk-m-prv-t1-bus",
|
||||
"clk-m-icn-reg-12",
|
||||
"clk-m-icn-reg-10",
|
||||
"", /* unused */
|
||||
"clk-m-icn-st231";
|
||||
};
|
||||
};
|
||||
|
36
Bindings/clock/st/st,clkgen-mux.txt
Normal file
36
Bindings/clock/st/st,clkgen-mux.txt
Normal file
@ -0,0 +1,36 @@
|
||||
Binding for a ST multiplexed clock driver.
|
||||
|
||||
This binding supports only simple indexed multiplexers, it does not
|
||||
support table based parent index to hardware value translations.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
|
||||
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
|
||||
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
- clocks : from common clock binding
|
||||
|
||||
Example:
|
||||
|
||||
clk_m_hva: clk-m-hva@fd690868 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
|
||||
reg = <0xfd690868 4>;
|
||||
|
||||
clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
|
||||
};
|
51
Bindings/clock/st/st,clkgen-pll.txt
Normal file
51
Bindings/clock/st/st,clkgen-pll.txt
Normal file
@ -0,0 +1,51 @@
|
||||
Binding for a ST pll clock driver.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Base address is located to the parent node. See clock binding[2]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgena-prediv-c65", "st,clkgena-prediv"
|
||||
"st,clkgena-prediv-c32", "st,clkgena-prediv"
|
||||
|
||||
"st,clkgena-plls-c65"
|
||||
"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
|
||||
"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
|
||||
"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
|
||||
|
||||
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 1.
|
||||
|
||||
- clocks : From common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
||||
clockgen-a@fee62000 {
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
};
|
||||
};
|
36
Bindings/clock/st/st,clkgen-prediv.txt
Normal file
36
Bindings/clock/st/st,clkgen-prediv.txt
Normal file
@ -0,0 +1,36 @@
|
||||
Binding for a ST pre-divider clock driver.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Base address is located to the parent node. See clock binding[2]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgena-prediv-c65", "st,clkgena-prediv"
|
||||
"st,clkgena-prediv-c32", "st,clkgena-prediv"
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 0.
|
||||
|
||||
- clocks : From common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
||||
clockgen-a@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c32",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-m-a2-osc-prediv";
|
||||
};
|
||||
};
|
||||
|
61
Bindings/clock/st/st,clkgen-vcc.txt
Normal file
61
Bindings/clock/st/st,clkgen-vcc.txt
Normal file
@ -0,0 +1,61 @@
|
||||
Binding for a type of STMicroelectronics clock crossbar (VCC).
|
||||
|
||||
The crossbar can take up to 4 input clocks and control up to 16
|
||||
output clocks. Not all inputs or outputs have to be in use in a
|
||||
particular instantiation. Each output can be individually enabled,
|
||||
select any of the input clocks and apply a divide (by 1,2,4 or 8) to
|
||||
that selected clock.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,stih416-clkgenc", "st,vcc"
|
||||
"st,stih416-clkgenf", "st,vcc"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
- clocks : from common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding. The block has 16
|
||||
clock outputs but not all of them in a specific instance
|
||||
have to be used in the SoC. If a clock name is left as
|
||||
an empty string then no clock will be created for the
|
||||
output associated with that string index. If fewer than
|
||||
16 strings are provided then no clocks will be created
|
||||
for the remaining outputs.
|
||||
|
||||
Example:
|
||||
|
||||
clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
|
||||
reg = <0xfe8308ac 12>;
|
||||
|
||||
clocks = <&clk_s_vcc_hd>,
|
||||
<&clockgen_c 1>,
|
||||
<&clk_s_tmds_fromphy>,
|
||||
<&clockgen_c 2>;
|
||||
|
||||
clock-output-names = "clk-s-pix-hdmi",
|
||||
"clk-s-pix-dvo",
|
||||
"clk-s-out-dvo",
|
||||
"clk-s-pix-hd",
|
||||
"clk-s-hddac",
|
||||
"clk-s-denc",
|
||||
"clk-s-sddac",
|
||||
"clk-s-pix-main",
|
||||
"clk-s-pix-aux",
|
||||
"clk-s-stfe-frc-0",
|
||||
"clk-s-ref-mcru",
|
||||
"clk-s-slave-mcru",
|
||||
"clk-s-tmds-hdmi",
|
||||
"clk-s-hdmi-reject-pll",
|
||||
"clk-s-thsens";
|
||||
};
|
||||
|
100
Bindings/clock/st/st,clkgen.txt
Normal file
100
Bindings/clock/st/st,clkgen.txt
Normal file
@ -0,0 +1,100 @@
|
||||
Binding for a Clockgen hardware block found on
|
||||
certain STMicroelectronics consumer electronics SoC devices.
|
||||
|
||||
A Clockgen node can contain pll, diviser or multiplexer nodes.
|
||||
|
||||
We will find only the base address of the Clockgen, this base
|
||||
address is common of all subnode.
|
||||
|
||||
clockgen_node {
|
||||
reg = <>;
|
||||
|
||||
pll_node {
|
||||
...
|
||||
};
|
||||
|
||||
prediv_node {
|
||||
...
|
||||
};
|
||||
|
||||
divmux_node {
|
||||
...
|
||||
};
|
||||
|
||||
quadfs_node {
|
||||
...
|
||||
};
|
||||
|
||||
mux_node {
|
||||
...
|
||||
};
|
||||
|
||||
vcc_node {
|
||||
...
|
||||
};
|
||||
|
||||
flexgen_node {
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Each subnode should use the binding discribe in [2]..[7]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
|
||||
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
|
||||
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
|
||||
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
|
||||
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
|
||||
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
|
||||
|
||||
|
||||
Required properties:
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
Example:
|
||||
|
||||
clockgen-a@fee62000 {
|
||||
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&clk-sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
};
|
||||
|
||||
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c65",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-osc-prediv";
|
||||
};
|
||||
|
||||
clk_s_a0_hs: clk-s-a0-hs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c65-hs",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&clk-s_a0_osc_prediv>,
|
||||
<&clk-s_a0_pll 0>, /* pll0 hs */
|
||||
<&clk-s_a0_pll 2>; /* pll1 */
|
||||
|
||||
clock-output-names = "clk-s-fdma-0",
|
||||
"clk-s-fdma-1",
|
||||
""; /* clk-s-jit-sense */
|
||||
/* fourth output unused */
|
||||
};
|
||||
};
|
||||
|
119
Bindings/clock/st/st,flexgen.txt
Normal file
119
Bindings/clock/st/st,flexgen.txt
Normal file
@ -0,0 +1,119 @@
|
||||
Binding for a type of flexgen structure found on certain
|
||||
STMicroelectronics consumer electronics SoC devices
|
||||
|
||||
This structure includes:
|
||||
- a clock cross bar (represented by a mux element)
|
||||
- a pre and final dividers (represented by a divider and gate elements)
|
||||
|
||||
Flexgen structure is a part of Clockgen[1].
|
||||
|
||||
Please find an example below:
|
||||
|
||||
Clockgen block diagram
|
||||
-------------------------------------------------------------------
|
||||
| Flexgen stucture |
|
||||
| --------------------------------------------- |
|
||||
| | ------- -------- -------- | |
|
||||
clk_sysin | | | | | | | | |
|
||||
---|-----------------|-->| | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | | |Pre | |Final | | |
|
||||
| | |PLL0 | | | | |Dividers| |Dividers| | |
|
||||
| |->| | | | | | x32 | | x32 | | |
|
||||
| | | odf_0|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | Clock | | | | | | |
|
||||
| | |PLL1 | | | | | | | | | |
|
||||
| |->| | | | Cross | | | | | | |
|
||||
| | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
|
||||
| | | | | | Bar |====>| |====>| |===|=========>
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | |QUADFS | | | | | | | | | |
|
||||
| |->| ch0|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | |
|
||||
| | ch1|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | |
|
||||
| | ch2|----|-->| | | DIV | | DIV | | |
|
||||
| | | | | | | 1 to | | 1 to | | |
|
||||
| | ch3|----|-->| | | 1024 | | 64 | | |
|
||||
| ------- | | | | | | | | |
|
||||
| | ------- -------- -------- | |
|
||||
| -------------------------------------------- |
|
||||
| |
|
||||
-------------------------------------------------------------------
|
||||
|
||||
This binding uses the common clock binding[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,flexgen"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
|
||||
outputs).
|
||||
|
||||
- clocks : must be set to the parent's phandle. it's could be output clocks of
|
||||
a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
|
||||
|
||||
- clock-output-names : List of strings used to name the clock outputs.
|
||||
|
||||
Example:
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_c0_pll0 0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
<&clk_s_c0_quadfs 0>,
|
||||
<&clk_s_c0_quadfs 1>,
|
||||
<&clk_s_c0_quadfs 2>,
|
||||
<&clk_s_c0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-icn-gpu",
|
||||
"clk-fdma",
|
||||
"clk-nand",
|
||||
"clk-hva",
|
||||
"clk-proc-stfe",
|
||||
"clk-proc-tp",
|
||||
"clk-rx-icn-dmu",
|
||||
"clk-rx-icn-hva",
|
||||
"clk-icn-cpu",
|
||||
"clk-tx-icn-dmu",
|
||||
"clk-mmc-0",
|
||||
"clk-mmc-1",
|
||||
"clk-jpegdec",
|
||||
"clk-ext2fa9",
|
||||
"clk-ic-bdisp-0",
|
||||
"clk-ic-bdisp-1",
|
||||
"clk-pp-dmu",
|
||||
"clk-vid-dmu",
|
||||
"clk-dss-lpc",
|
||||
"clk-st231-aud-0",
|
||||
"clk-st231-gp-1",
|
||||
"clk-st231-dmu",
|
||||
"clk-icn-lmi",
|
||||
"clk-tx-icn-disp-1",
|
||||
"clk-icn-sbc",
|
||||
"clk-stfe-frc2",
|
||||
"clk-eth-phy",
|
||||
"clk-eth-ref-phyclk",
|
||||
"clk-flash-promip",
|
||||
"clk-main-disp",
|
||||
"clk-aux-disp",
|
||||
"clk-compo-dvp";
|
||||
};
|
48
Bindings/clock/st/st,quadfs.txt
Normal file
48
Bindings/clock/st/st,quadfs.txt
Normal file
@ -0,0 +1,48 @@
|
||||
Binding for a type of quad channel digital frequency synthesizer found on
|
||||
certain STMicroelectronics consumer electronics SoC devices.
|
||||
|
||||
This version contains a programmable PLL which can generate up to 216, 432
|
||||
or 660MHz (from a 30MHz oscillator input) as the input to the digital
|
||||
synthesizers.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,stih416-quadfs216", "st,quadfs"
|
||||
"st,stih416-quadfs432", "st,quadfs"
|
||||
"st,stih416-quadfs660-E", "st,quadfs"
|
||||
"st,stih416-quadfs660-F", "st,quadfs"
|
||||
"st,stih407-quadfs660-C", "st,quadfs"
|
||||
"st,stih407-quadfs660-D", "st,quadfs"
|
||||
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
- clocks : from common clock binding
|
||||
|
||||
- clock-output-names : From common clock binding. The block has 4
|
||||
clock outputs but not all of them in a specific instance
|
||||
have to be used in the SoC. If a clock name is left as
|
||||
an empty string then no clock will be created for the
|
||||
output associated with that string index. If fewer than
|
||||
4 strings are provided then no clocks will be created
|
||||
for the remaining outputs.
|
||||
|
||||
Example:
|
||||
|
||||
clockgen_e: clockgen-e@fd3208bc {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-quadfs660-E", "st,quadfs";
|
||||
reg = <0xfd3208bc 0xB0>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
clock-output-names = "clk-m-pix-mdtp-0",
|
||||
"clk-m-pix-mdtp-1",
|
||||
"clk-m-pix-mdtp-2",
|
||||
"clk-m-mpelpc";
|
||||
};
|
20
Bindings/clock/ti-keystone-pllctrl.txt
Normal file
20
Bindings/clock/ti-keystone-pllctrl.txt
Normal file
@ -0,0 +1,20 @@
|
||||
* Device tree bindings for Texas Instruments keystone pll controller
|
||||
|
||||
The main pll controller used to drive theC66x CorePacs, the switch fabric,
|
||||
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
|
||||
the NETCP modules) requires a PLL Controller to manage the various clock
|
||||
divisions, gating, and synchronization.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "ti,keystone-pllctrl", "syscon"
|
||||
|
||||
- reg: contains offset/length value for pll controller
|
||||
registers space.
|
||||
|
||||
Example:
|
||||
|
||||
pllctrl: pll-controller@0x02310000 {
|
||||
compatible = "ti,keystone-pllctrl", "syscon";
|
||||
reg = <0x02310000 0x200>;
|
||||
};
|
96
Bindings/clock/ti/dra7-atl.txt
Normal file
96
Bindings/clock/ti/dra7-atl.txt
Normal file
@ -0,0 +1,96 @@
|
||||
Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
|
||||
|
||||
The ATL IP is used to generate clock to be used to synchronize baseband and
|
||||
audio codec. A single ATL IP provides four ATL clock instances sharing the same
|
||||
functional clock but can be configured to provide different clocks.
|
||||
ATL can maintain a clock averages to some desired frequency based on the bws/aws
|
||||
signals - can compensate the drift between the two ws signal.
|
||||
|
||||
In order to provide the support for ATL and it's output clocks (which can be used
|
||||
internally within the SoC or external components) two sets of bindings is needed:
|
||||
|
||||
Clock tree binding:
|
||||
This binding uses the common clock binding[1].
|
||||
To be able to integrate the ATL clocks with DT clock tree.
|
||||
Provides ccf level representation of the ATL clocks to be used by drivers.
|
||||
Since the clock instances are part of a single IP this binding is used as a node
|
||||
for the DT clock tree, the IP driver is needed to handle the actual configuration
|
||||
of the IP.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dra7-atl-clock"
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles to functional clock of ATL
|
||||
|
||||
Binding for the IP driver:
|
||||
This binding is used to configure the IP driver which is going to handle the
|
||||
configuration of the IP for the ATL clock instances.
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dra7-atl"
|
||||
- reg : base address for the ATL IP
|
||||
- ti,provided-clocks : List of phandles to the clocks associated with the ATL
|
||||
- clocks : link phandles to functional clock of ATL
|
||||
- clock-names : Shall be set to "fck"
|
||||
- ti,hwmods : Shall be set to "atl"
|
||||
|
||||
Optional properties:
|
||||
Configuration of ATL instances:
|
||||
- atl{0/1/2/3} {
|
||||
- bws : Baseband word select signal selection
|
||||
- aws : Audio word select signal selection
|
||||
};
|
||||
|
||||
For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include
|
||||
file.
|
||||
|
||||
Examples:
|
||||
/* clock bindings for atl provided clocks */
|
||||
atl_clkin0_ck: atl_clkin0_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin1_ck: atl_clkin1_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin2_ck: atl_clkin2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin3_ck: atl_clkin3_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
/* binding for the IP */
|
||||
atl: atl@4843c000 {
|
||||
compatible = "ti,dra7-atl";
|
||||
reg = <0x4843c000 0x3ff>;
|
||||
ti,hwmods = "atl";
|
||||
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
|
||||
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
#include <dt-bindings/clk/ti-dra7-atl.h>
|
||||
|
||||
&atl {
|
||||
status = "okay";
|
||||
|
||||
atl2 {
|
||||
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
||||
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
||||
};
|
||||
};
|
19
Bindings/crypto/amd-ccp.txt
Normal file
19
Bindings/crypto/amd-ccp.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* AMD Cryptographic Coprocessor driver (ccp)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "amd,ccp-seattle-v1a"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupt-parent: Should be the phandle for the interrupt controller
|
||||
that services interrupts for this device
|
||||
- interrupts: Should contain the CCP interrupt
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: Present if dma operations are coherent
|
||||
|
||||
Example:
|
||||
ccp@e0100000 {
|
||||
compatible = "amd,ccp-seattle-v1a";
|
||||
reg = <0 0xe0100000 0 0x10000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 3 4>;
|
||||
};
|
25
Bindings/crypto/qcom-qce.txt
Normal file
25
Bindings/crypto/qcom-qce.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Qualcomm crypto engine driver
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "qcom,crypto-v5.1"
|
||||
- reg : specifies base physical address and size of the registers map
|
||||
- clocks : phandle to clock-controller plus clock-specifier pair
|
||||
- clock-names : "iface" clocks register interface
|
||||
"bus" clocks data transfer interface
|
||||
"core" clocks rest of the crypto block
|
||||
- dmas : DMA specifiers for tx and rx dma channels. For more see
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names : DMA request names should be "rx" and "tx"
|
||||
|
||||
Example:
|
||||
crypto@fd45a000 {
|
||||
compatible = "qcom,crypto-v5.1";
|
||||
reg = <0xfd45a000 0x6000>;
|
||||
clocks = <&gcc GCC_CE2_AHB_CLK>,
|
||||
<&gcc GCC_CE2_AXI_CLK>,
|
||||
<&gcc GCC_CE2_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
dmas = <&cryptobam 2>, <&cryptobam 3>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
34
Bindings/crypto/samsung-sss.txt
Normal file
34
Bindings/crypto/samsung-sss.txt
Normal file
@ -0,0 +1,34 @@
|
||||
Samsung SoC SSS (Security SubSystem) module
|
||||
|
||||
The SSS module in S5PV210 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES)
|
||||
-- Data Encryption Standard (DES)/3DES
|
||||
-- Public Key Accelerator (PKA)
|
||||
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
|
||||
-- PRNG: Pseudo Random Number Generator
|
||||
|
||||
The SSS module in Exynos4 (Exynos4210) and
|
||||
Exynos5 (Exynos5420 and Exynos5250) SoCs
|
||||
supports the following also:
|
||||
-- ARCFOUR (ARC4)
|
||||
-- True Random Number Generator (TRNG)
|
||||
-- Secure Key Manager
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
SSS versions:
|
||||
- "samsung,s5pv210-secss" for S5PV210 SoC.
|
||||
- "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
|
||||
Exynos5260 and Exynos5420 SoCs.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SSS module interrupts, should contain
|
||||
following entries:
|
||||
- first : feed control interrupt (required for all variants),
|
||||
- second : hash interrupt (required only for samsung,s5pv210-secss).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
- clock-names : list of device clock input names; should contain one entry
|
||||
"secss".
|
76
Bindings/dma/fsl-edma.txt
Normal file
76
Bindings/dma/fsl-edma.txt
Normal file
@ -0,0 +1,76 @@
|
||||
* Freescale enhanced Direct Memory Access(eDMA) Controller
|
||||
|
||||
The eDMA channels have multiplex capability by programmble memory-mapped
|
||||
registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,
|
||||
specific DMA request source can only be multiplexed by any channel of certain
|
||||
group, DMAMUX0 or DMAMUX1, but not both.
|
||||
|
||||
* eDMA Controller
|
||||
Required properties:
|
||||
- compatible :
|
||||
- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
|
||||
- reg : Specifies base physical address(s) and size of the eDMA registers.
|
||||
The 1st region is eDMA control register's address and size.
|
||||
The 2nd and the 3rd regions are programmable channel multiplexing
|
||||
control register's address and size.
|
||||
- interrupts : A list of interrupt-specifiers, one for each entry in
|
||||
interrupt-names.
|
||||
- interrupt-names : Should contain:
|
||||
"edma-tx" - the transmission interrupt
|
||||
"edma-err" - the error interrupt
|
||||
- #dma-cells : Must be <2>.
|
||||
The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
|
||||
Specific request source can only be multiplexed by specific channels
|
||||
group called DMAMUX.
|
||||
The 2nd cell specifies the request source(slot) ID.
|
||||
See the SoC's reference manual for all the supported request sources.
|
||||
- dma-channels : Number of channels supported by the controller
|
||||
- clock-names : A list of channel group clock names. Should contain:
|
||||
"dmamux0" - clock name of mux0 group
|
||||
"dmamux1" - clock name of mux1 group
|
||||
- clocks : A list of phandle and clock-specifier pairs, one for each entry in
|
||||
clock-names.
|
||||
|
||||
Optional properties:
|
||||
- big-endian: If present registers and hardware scatter/gather descriptors
|
||||
of the eDMA are implemented in big endian mode, otherwise in little
|
||||
mode.
|
||||
|
||||
|
||||
Examples:
|
||||
|
||||
edma0: dma-controller@40018000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x40018000 0x2000>,
|
||||
<0x40024000 0x1000>,
|
||||
<0x40025000 0x1000>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clks VF610_CLK_DMAMUX0>,
|
||||
<&clks VF610_CLK_DMAMUX1>;
|
||||
};
|
||||
|
||||
|
||||
* DMA clients
|
||||
DMA client drivers that uses the DMA function must use the format described
|
||||
in the dma.txt file, using a two-cell specifier for each channel: the 1st
|
||||
specifies the channel group(DMAMUX) in which this request can be multiplexed,
|
||||
and the 2nd specifies the request source.
|
||||
|
||||
Examples:
|
||||
|
||||
sai2: sai@40031000 {
|
||||
compatible = "fsl,vf610-sai";
|
||||
reg = <0x40031000 0x1000>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "sai";
|
||||
clocks = <&clks VF610_CLK_SAI2>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 0 21>,
|
||||
<&edma0 0 20>;
|
||||
status = "disabled";
|
||||
};
|
29
Bindings/dma/mpc512x-dma.txt
Normal file
29
Bindings/dma/mpc512x-dma.txt
Normal file
@ -0,0 +1,29 @@
|
||||
* Freescale MPC512x and MPC8308 DMA Controller
|
||||
|
||||
The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
|
||||
blocks of memory contents between memory and peripherals or
|
||||
from memory to memory.
|
||||
|
||||
Refer to "Generic DMA Controller and DMA request bindings" in
|
||||
the dma/dma.txt file for a more detailed description of binding.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
|
||||
- reg: should contain the DMA controller registers location and length;
|
||||
- interrupt for the DMA controller: syntax of interrupt client node
|
||||
is described in interrupt-controller/interrupts.txt file.
|
||||
- #dma-cells: the length of the DMA specifier, must be <1>.
|
||||
Each channel of this DMA controller has a peripheral request line,
|
||||
the assignment is fixed in hardware. This one cell
|
||||
in dmas property of a client device represents the channel number.
|
||||
|
||||
Example:
|
||||
|
||||
dma0: dma@14000 {
|
||||
compatible = "fsl,mpc5121-dma";
|
||||
reg = <0x14000 0x1800>;
|
||||
interrupts = <65 0x8>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
DMA clients must use the format described in dma/dma.txt file.
|
61
Bindings/dma/nbpfaxi.txt
Normal file
61
Bindings/dma/nbpfaxi.txt
Normal file
@ -0,0 +1,61 @@
|
||||
* Renesas "Type-AXI" NBPFAXI* DMA controllers
|
||||
|
||||
* DMA controller
|
||||
|
||||
Required properties
|
||||
|
||||
- compatible: must be one of
|
||||
"renesas,nbpfaxi64dmac1b4"
|
||||
"renesas,nbpfaxi64dmac1b8"
|
||||
"renesas,nbpfaxi64dmac1b16"
|
||||
"renesas,nbpfaxi64dmac4b4"
|
||||
"renesas,nbpfaxi64dmac4b8"
|
||||
"renesas,nbpfaxi64dmac4b16"
|
||||
"renesas,nbpfaxi64dmac8b4"
|
||||
"renesas,nbpfaxi64dmac8b8"
|
||||
"renesas,nbpfaxi64dmac8b16"
|
||||
- #dma-cells: must be 2: the first integer is a terminal number, to which this
|
||||
slave is connected, the second one is flags. Flags is a bitmask
|
||||
with the following bits defined:
|
||||
|
||||
#define NBPF_SLAVE_RQ_HIGH 1
|
||||
#define NBPF_SLAVE_RQ_LOW 2
|
||||
#define NBPF_SLAVE_RQ_LEVEL 4
|
||||
|
||||
Optional properties:
|
||||
|
||||
You can use dma-channels and dma-requests as described in dma.txt, although they
|
||||
won't be used, this information is derived from the compatibility string.
|
||||
|
||||
Example:
|
||||
|
||||
dma: dma-controller@48000000 {
|
||||
compatible = "renesas,nbpfaxi64dmac8b4";
|
||||
reg = <0x48000000 0x400>;
|
||||
interrupts = <0 12 0x4
|
||||
0 13 0x4
|
||||
0 14 0x4
|
||||
0 15 0x4
|
||||
0 16 0x4
|
||||
0 17 0x4
|
||||
0 18 0x4
|
||||
0 19 0x4>;
|
||||
#dma-cells = <2>;
|
||||
dma-channels = <8>;
|
||||
dma-requests = <8>;
|
||||
};
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
|
||||
dmas and dma-names are required, as described in dma.txt.
|
||||
|
||||
Example:
|
||||
|
||||
#include <dt-bindings/dma/nbpfaxi.h>
|
||||
|
||||
...
|
||||
dmas = <&dma 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)
|
||||
&dma 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
|
||||
dma-names = "rx", "tx";
|
41
Bindings/dma/qcom_bam_dma.txt
Normal file
41
Bindings/dma/qcom_bam_dma.txt
Normal file
@ -0,0 +1,41 @@
|
||||
QCOM BAM DMA controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must contain "qcom,bam-v1.4.0" for MSM8974
|
||||
- reg: Address range for DMA registers
|
||||
- interrupts: Should contain the one interrupt shared by all channels
|
||||
- #dma-cells: must be <1>, the cell in the dmas property of the client device
|
||||
represents the channel number
|
||||
- clocks: required clock
|
||||
- clock-names: must contain "bam_clk" entry
|
||||
- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
|
||||
the secure world.
|
||||
|
||||
Example:
|
||||
|
||||
uart-bam: dma@f9984000 = {
|
||||
compatible = "qcom,bam-v1.4.0";
|
||||
reg = <0xf9984000 0x15000>;
|
||||
interrupts = <0 94 0>;
|
||||
clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
DMA clients must use the format described in the dma.txt file, using a two cell
|
||||
specifier for each channel.
|
||||
|
||||
Example:
|
||||
serial@f991e000 {
|
||||
compatible = "qcom,msm-uart";
|
||||
reg = <0xf991e000 0x1000>
|
||||
<0xf9944000 0x19000>;
|
||||
interrupts = <0 108 0>;
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
|
||||
dmas = <&uart-bam 0>, <&uart-bam 1>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
29
Bindings/dma/rcar-audmapp.txt
Normal file
29
Bindings/dma/rcar-audmapp.txt
Normal file
@ -0,0 +1,29 @@
|
||||
* R-Car Audio DMAC peri peri Device Tree bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "renesas,rcar-audmapp"
|
||||
- #dma-cells: should be <1>, see "dmas" property below
|
||||
|
||||
Example:
|
||||
audmapp: audio-dma-pp@0xec740000 {
|
||||
compatible = "renesas,rcar-audmapp";
|
||||
#dma-cells = <1>;
|
||||
|
||||
reg = <0 0xec740000 0 0x200>;
|
||||
};
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[DMA multiplexer phandle] [SRS/DRS value]> pairs,
|
||||
where SRS/DRS values are fixed handles, specified in the SoC
|
||||
manual as the value that would be written into the PDMACHCR.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
|
||||
dmas = <&audmapp 0x2d00
|
||||
&audmapp 0x3700>;
|
||||
dma-names = "src0_ssiu0",
|
||||
"dvc0_ssiu0";
|
98
Bindings/dma/renesas,rcar-dmac.txt
Normal file
98
Bindings/dma/renesas,rcar-dmac.txt
Normal file
@ -0,0 +1,98 @@
|
||||
* Renesas R-Car DMA Controller Device Tree bindings
|
||||
|
||||
Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA
|
||||
controller instances named DMAC capable of serving multiple clients. Channels
|
||||
can be dedicated to specific clients or shared between a large number of
|
||||
clients.
|
||||
|
||||
DMA clients are connected to the DMAC ports referenced by an 8-bit identifier
|
||||
called MID/RID.
|
||||
|
||||
Each DMA client is connected to one dedicated port of the DMAC, identified by
|
||||
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
|
||||
256 clients in total. When the number of hardware channels is lower than the
|
||||
number of clients to be served, channels must be shared between multiple DMA
|
||||
clients. The association of DMA clients to DMAC channels is fully dynamic and
|
||||
not described in these device tree bindings.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: must contain "renesas,rcar-dmac"
|
||||
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
|
||||
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
||||
interrupt-names.
|
||||
- interrupt-names: one entry per channel, named "ch%u", where %u is the
|
||||
channel number ranging from zero to the number of channels minus one.
|
||||
|
||||
- clock-names: "fck" for the functional clock
|
||||
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
||||
in clock-names.
|
||||
- clock-names: must contain "fck" for the functional clock.
|
||||
|
||||
- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
|
||||
connected to the DMA client
|
||||
- dma-channels: number of DMA channels
|
||||
|
||||
Example: R8A7790 (R-Car H2) SYS-DMACs
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x20000>;
|
||||
interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
|
||||
0 200 IRQ_TYPE_LEVEL_HIGH
|
||||
0 201 IRQ_TYPE_LEVEL_HIGH
|
||||
0 202 IRQ_TYPE_LEVEL_HIGH
|
||||
0 203 IRQ_TYPE_LEVEL_HIGH
|
||||
0 204 IRQ_TYPE_LEVEL_HIGH
|
||||
0 205 IRQ_TYPE_LEVEL_HIGH
|
||||
0 206 IRQ_TYPE_LEVEL_HIGH
|
||||
0 207 IRQ_TYPE_LEVEL_HIGH
|
||||
0 208 IRQ_TYPE_LEVEL_HIGH
|
||||
0 209 IRQ_TYPE_LEVEL_HIGH
|
||||
0 210 IRQ_TYPE_LEVEL_HIGH
|
||||
0 211 IRQ_TYPE_LEVEL_HIGH
|
||||
0 212 IRQ_TYPE_LEVEL_HIGH
|
||||
0 213 IRQ_TYPE_LEVEL_HIGH
|
||||
0 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e6720000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
reg = <0 0xe6720000 0 0x20000>;
|
||||
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
|
||||
0 216 IRQ_TYPE_LEVEL_HIGH
|
||||
0 217 IRQ_TYPE_LEVEL_HIGH
|
||||
0 218 IRQ_TYPE_LEVEL_HIGH
|
||||
0 219 IRQ_TYPE_LEVEL_HIGH
|
||||
0 308 IRQ_TYPE_LEVEL_HIGH
|
||||
0 309 IRQ_TYPE_LEVEL_HIGH
|
||||
0 310 IRQ_TYPE_LEVEL_HIGH
|
||||
0 311 IRQ_TYPE_LEVEL_HIGH
|
||||
0 312 IRQ_TYPE_LEVEL_HIGH
|
||||
0 313 IRQ_TYPE_LEVEL_HIGH
|
||||
0 314 IRQ_TYPE_LEVEL_HIGH
|
||||
0 315 IRQ_TYPE_LEVEL_HIGH
|
||||
0 316 IRQ_TYPE_LEVEL_HIGH
|
||||
0 317 IRQ_TYPE_LEVEL_HIGH
|
||||
0 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
43
Bindings/dma/sirfsoc-dma.txt
Normal file
43
Bindings/dma/sirfsoc-dma.txt
Normal file
@ -0,0 +1,43 @@
|
||||
* CSR SiRFSoC DMA controller
|
||||
|
||||
See dma.txt first
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "sirf,prima2-dmac" or "sirf,marco-dmac"
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- interrupts: Should contain one interrupt shared by all channel
|
||||
- #dma-cells: must be <1>. used to represent the number of integer
|
||||
cells in the dmas property of client device.
|
||||
- clocks: clock required
|
||||
|
||||
Example:
|
||||
|
||||
Controller:
|
||||
dmac0: dma-controller@b00b0000 {
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb00b0000 0x10000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&clks 24>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Client:
|
||||
Fill the specific dma request line in dmas. In the below example, spi0 read
|
||||
channel request line is 9 of the 2nd dma controller, while write channel uses
|
||||
4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st
|
||||
dma controller, while write channel uses 13 of the 1st dma controller:
|
||||
|
||||
spi0: spi@b00d0000 {
|
||||
compatible = "sirf,prima2-spi";
|
||||
dmas = <&dmac1 9>,
|
||||
<&dmac1 4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
spi1: spi@b0170000 {
|
||||
compatible = "sirf,prima2-spi";
|
||||
dmas = <&dmac0 12>,
|
||||
<&dmac0 13>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
45
Bindings/dma/sun6i-dma.txt
Normal file
45
Bindings/dma/sun6i-dma.txt
Normal file
@ -0,0 +1,45 @@
|
||||
Allwinner A31 DMA Controller
|
||||
|
||||
This driver follows the generic DMA bindings defined in dma.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "allwinner,sun6i-a31-dma"
|
||||
- reg: Should contain the registers base address and length
|
||||
- interrupts: Should contain a reference to the interrupt used by this device
|
||||
- clocks: Should contain a reference to the parent AHB clock
|
||||
- resets: Should contain a reference to the reset controller asserting
|
||||
this device in reset
|
||||
- #dma-cells : Should be 1, a single cell holding a line request number
|
||||
|
||||
Example:
|
||||
dma: dma-controller@01c02000 {
|
||||
compatible = "allwinner,sun6i-a31-dma";
|
||||
reg = <0x01c02000 0x1000>;
|
||||
interrupts = <0 50 4>;
|
||||
clocks = <&ahb1_gates 6>;
|
||||
resets = <&ahb1_rst 6>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
Clients:
|
||||
|
||||
DMA clients connected to the A31 DMA controller must use the format
|
||||
described in the dma.txt file, using a two-cell specifier for each
|
||||
channel: a phandle plus one integer cells.
|
||||
The two cells in order are:
|
||||
|
||||
1. A phandle pointing to the DMA controller.
|
||||
2. The port ID as specified in the datasheet
|
||||
|
||||
Example:
|
||||
spi2: spi@01c6a000 {
|
||||
compatible = "allwinner,sun6i-a31-spi";
|
||||
reg = <0x01c6a000 0x1000>;
|
||||
interrupts = <0 67 4>;
|
||||
clocks = <&ahb1_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 25>, <&dma 25>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ahb1_rst 22>;
|
||||
};
|
75
Bindings/dma/xilinx/xilinx_vdma.txt
Normal file
75
Bindings/dma/xilinx/xilinx_vdma.txt
Normal file
@ -0,0 +1,75 @@
|
||||
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
|
||||
It can be configured to have one channel or two channels. If configured
|
||||
as two channels, one is to transmit to the video device and another is
|
||||
to receive from the video device.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "xlnx,axi-vdma-1.00.a"
|
||||
- #dma-cells: Should be <1>, see "dmas" property below
|
||||
- reg: Should contain VDMA registers location and length.
|
||||
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
|
||||
- dma-channel child node: Should have at least one channel and can have up to
|
||||
two channels per device. This node specifies the properties of each
|
||||
DMA channel (see child node properties below).
|
||||
|
||||
Optional properties:
|
||||
- xlnx,include-sg: Tells configured for Scatter-mode in
|
||||
the hardware.
|
||||
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
|
||||
It takes following values:
|
||||
{1}, flush both channels
|
||||
{2}, flush mm2s channel
|
||||
{3}, flush s2mm channel
|
||||
|
||||
Required child node properties:
|
||||
- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
|
||||
"xlnx,axi-vdma-s2mm-channel".
|
||||
- interrupts: Should contain per channel VDMA interrupts.
|
||||
- xlnx,data-width: Should contain the stream data width, take values
|
||||
{32,64...1024}.
|
||||
|
||||
Optional child node properties:
|
||||
- xlnx,include-dre: Tells hardware is configured for Data
|
||||
Realignment Engine.
|
||||
- xlnx,genlock-mode: Tells Genlock synchronization is
|
||||
enabled/disabled in hardware.
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
axi_vdma_0: axivdma@40030000 {
|
||||
compatible = "xlnx,axi-vdma-1.00.a";
|
||||
#dma_cells = <1>;
|
||||
reg = < 0x40030000 0x10000 >;
|
||||
xlnx,num-fstores = <0x8>;
|
||||
xlnx,flush-fsync = <0x1>;
|
||||
dma-channel@40030000 {
|
||||
compatible = "xlnx,axi-vdma-mm2s-channel";
|
||||
interrupts = < 0 54 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
dma-channel@40030030 {
|
||||
compatible = "xlnx,axi-vdma-s2mm-channel";
|
||||
interrupts = < 0 53 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
} ;
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
|
||||
where Channel ID is '0' for write/tx and '1' for read/rx
|
||||
channel.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
vdmatest_0: vdmatest@0 {
|
||||
compatible ="xlnx,axi-vdma-test-1.00.a";
|
||||
dmas = <&axi_vdma_0 0
|
||||
&axi_vdma_0 1>;
|
||||
dma-names = "vdma0", "vdma1";
|
||||
} ;
|
30
Bindings/drm/armada/marvell,dove-lcd.txt
Normal file
30
Bindings/drm/armada/marvell,dove-lcd.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Device Tree bindings for Armada DRM CRTC driver
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "marvell,dove-lcd".
|
||||
- reg: base address and size of the LCD controller
|
||||
- interrupts: single interrupt number for the LCD controller
|
||||
- port: video output port with endpoints, as described by graph.txt
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks: as described by clock-bindings.txt
|
||||
- clock-names: as described by clock-bindings.txt
|
||||
"axiclk" - axi bus clock for pixel clock
|
||||
"plldivider" - pll divider clock for pixel clock
|
||||
"ext_ref_clk0" - external clock 0 for pixel clock
|
||||
"ext_ref_clk1" - external clock 1 for pixel clock
|
||||
|
||||
Note: all clocks are optional but at least one must be specified.
|
||||
Further clocks may be added in the future according to requirements of
|
||||
different SoCs.
|
||||
|
||||
Example:
|
||||
|
||||
lcd0: lcd-controller@820000 {
|
||||
compatible = "marvell,dove-lcd";
|
||||
reg = <0x820000 0x1000>;
|
||||
interrupts = <47>;
|
||||
clocks = <&si5351 0>;
|
||||
clock-names = "ext_ref_clk_1";
|
||||
};
|
27
Bindings/drm/bridge/ptn3460.txt
Normal file
27
Bindings/drm/bridge/ptn3460.txt
Normal file
@ -0,0 +1,27 @@
|
||||
ptn3460 bridge bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "nxp,ptn3460"
|
||||
- reg: i2c address of the bridge
|
||||
- powerdown-gpio: OF device-tree gpio specification
|
||||
- reset-gpio: OF device-tree gpio specification
|
||||
- edid-emulation: The EDID emulation entry to use
|
||||
+-------+------------+------------------+
|
||||
| Value | Resolution | Description |
|
||||
| 0 | 1024x768 | NXP Generic |
|
||||
| 1 | 1920x1080 | NXP Generic |
|
||||
| 2 | 1920x1080 | NXP Generic |
|
||||
| 3 | 1600x900 | Samsung LTM200KT |
|
||||
| 4 | 1920x1080 | Samsung LTM230HT |
|
||||
| 5 | 1366x768 | NXP Generic |
|
||||
| 6 | 1600x900 | ChiMei M215HGE |
|
||||
+-------+------------+------------------+
|
||||
|
||||
Example:
|
||||
lvds-bridge@20 {
|
||||
compatible = "nxp,ptn3460";
|
||||
reg = <0x20>;
|
||||
powerdown-gpio = <&gpy2 5 1 0 0>;
|
||||
reset-gpio = <&gpx1 5 1 0 0>;
|
||||
edid-emulation = <5>;
|
||||
};
|
29
Bindings/drm/i2c/tda998x.txt
Normal file
29
Bindings/drm/i2c/tda998x.txt
Normal file
@ -0,0 +1,29 @@
|
||||
Device-Tree bindings for the NXP TDA998x HDMI transmitter
|
||||
|
||||
Required properties;
|
||||
- compatible: must be "nxp,tda998x"
|
||||
|
||||
- reg: I2C address
|
||||
|
||||
Optional properties:
|
||||
- interrupts: interrupt number and trigger type
|
||||
default: polling
|
||||
|
||||
- pinctrl-0: pin control group to be used for
|
||||
screen plug/unplug interrupt.
|
||||
|
||||
- pinctrl-names: must contain a "default" entry.
|
||||
|
||||
- video-ports: 24 bits value which defines how the video controller
|
||||
output is wired to the TDA998x input - default: <0x230145>
|
||||
|
||||
Example:
|
||||
|
||||
tda998x: hdmi-encoder {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <27 2>; /* falling edge */
|
||||
pinctrl-0 = <&pmx_camera>;
|
||||
pinctrl-names = "default";
|
||||
};
|
52
Bindings/drm/msm/gpu.txt
Normal file
52
Bindings/drm/msm/gpu.txt
Normal file
@ -0,0 +1,52 @@
|
||||
Qualcomm adreno/snapdragon GPU
|
||||
|
||||
Required properties:
|
||||
- compatible: "qcom,adreno-3xx"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the gpu.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "mem_iface_clk"
|
||||
- qcom,chipid: gpu chip-id. Note this may become optional for future
|
||||
devices if we can reliably read the chipid from hw
|
||||
- qcom,gpu-pwrlevels: list of operating points
|
||||
- compatible: "qcom,gpu-pwrlevels"
|
||||
- for each qcom,gpu-pwrlevel:
|
||||
- qcom,gpu-freq: requested gpu clock speed
|
||||
- NOTE: downstream android driver defines additional parameters to
|
||||
configure memory bandwidth scaling per OPP.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
gpu: qcom,kgsl-3d0@4300000 {
|
||||
compatible = "qcom,adreno-3xx";
|
||||
reg = <0x04300000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <GIC_SPI 80 0>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"mem_iface_clk";
|
||||
clocks =
|
||||
<&mmcc GFX3D_CLK>,
|
||||
<&mmcc GFX3D_AHB_CLK>,
|
||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||
qcom,chipid = <0x03020100>;
|
||||
qcom,gpu-pwrlevels {
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
qcom,gpu-freq = <450000000>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
qcom,gpu-freq = <27000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
46
Bindings/drm/msm/hdmi.txt
Normal file
46
Bindings/drm/msm/hdmi.txt
Normal file
@ -0,0 +1,46 @@
|
||||
Qualcomm adreno/snapdragon hdmi output
|
||||
|
||||
Required properties:
|
||||
- compatible: one of the following
|
||||
* "qcom,hdmi-tx-8660"
|
||||
* "qcom,hdmi-tx-8960"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- reg-names: "core_physical"
|
||||
- interrupts: The interrupt signal from the hdmi block.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
|
||||
- qcom,hdmi-tx-ddc-data-gpio: ddc data pin
|
||||
- qcom,hdmi-tx-hpd-gpio: hpd pin
|
||||
- core-vdda-supply: phandle to supply regulator
|
||||
- hdmi-mux-supply: phandle to mux regulator
|
||||
|
||||
Optional properties:
|
||||
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
|
||||
- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdmi: qcom,hdmi-tx-8960@4a00000 {
|
||||
compatible = "qcom,hdmi-tx-8960";
|
||||
reg-names = "core_physical";
|
||||
reg = <0x04a00000 0x1000>;
|
||||
interrupts = <GIC_SPI 79 0>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"master_iface_clk",
|
||||
"slave_iface_clk";
|
||||
clocks =
|
||||
<&mmcc HDMI_APP_CLK>,
|
||||
<&mmcc HDMI_M_AHB_CLK>,
|
||||
<&mmcc HDMI_S_AHB_CLK>;
|
||||
qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
|
||||
qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
|
||||
qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
|
||||
core-vdda-supply = <&pm8921_hdmi_mvs>;
|
||||
hdmi-mux-supply = <&ext_3p3v>;
|
||||
};
|
||||
};
|
48
Bindings/drm/msm/mdp.txt
Normal file
48
Bindings/drm/msm/mdp.txt
Normal file
@ -0,0 +1,48 @@
|
||||
Qualcomm adreno/snapdragon display controller
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp" - mdp4
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- connectors: array of phandles for output device(s)
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "lut_clk"
|
||||
* "src_clk"
|
||||
* "hdmi_clk"
|
||||
* "mpd_clk"
|
||||
|
||||
Optional properties:
|
||||
- gpus: phandle for gpu device
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdp: qcom,mdp@5100000 {
|
||||
compatible = "qcom,mdp";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
connectors = <&hdmi>;
|
||||
gpus = <&gpu>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"src_clk",
|
||||
"hdmi_clk",
|
||||
"mdp_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_SRC>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc TV_SRC>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
};
|
||||
};
|
23
Bindings/extcon/extcon-sm5502.txt
Normal file
23
Bindings/extcon/extcon-sm5502.txt
Normal file
@ -0,0 +1,23 @@
|
||||
|
||||
* SM5502 MUIC (Micro-USB Interface Controller) device
|
||||
|
||||
The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device
|
||||
which can detect the state of external accessory when external accessory is
|
||||
attached or detached and button is pressed or released. It is interfaced to
|
||||
the host controller using an I2C interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "siliconmitus,sm5502-muic"
|
||||
- reg: Specifies the I2C slave address of the MUIC block. It should be 0x25
|
||||
- interrupt-parent: Specifies the phandle of the interrupt controller to which
|
||||
the interrupts from sm5502 are delivered to.
|
||||
- interrupts: Interrupt specifiers for detection interrupt sources.
|
||||
|
||||
Example:
|
||||
|
||||
sm5502@25 {
|
||||
compatible = "siliconmitus,sm5502-muic";
|
||||
interrupt-parent = <&gpx1>;
|
||||
interrupts = <5 0>;
|
||||
reg = <0x25>;
|
||||
};
|
40
Bindings/fuse/nvidia,tegra20-fuse.txt
Normal file
40
Bindings/fuse/nvidia,tegra20-fuse.txt
Normal file
@ -0,0 +1,40 @@
|
||||
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be:
|
||||
"nvidia,tegra20-efuse"
|
||||
"nvidia,tegra30-efuse"
|
||||
"nvidia,tegra114-efuse"
|
||||
"nvidia,tegra124-efuse"
|
||||
Details:
|
||||
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
|
||||
due to a hardware bug. Tegra20 also lacks certain information which is
|
||||
available in later generations such as fab code, lot code, wafer id,..
|
||||
nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
|
||||
The differences between these SoCs are the size of the efuse array,
|
||||
the location of the spare (OEM programmable) bits and the location of
|
||||
the speedo data.
|
||||
- reg: Should contain 1 entry: the entry gives the physical address and length
|
||||
of the fuse registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- fuse
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- fuse
|
||||
|
||||
Example:
|
||||
|
||||
fuse@7000f800 {
|
||||
compatible = "nvidia,tegra20-efuse";
|
||||
reg = <0x7000F800 0x400>,
|
||||
<0x70000000 0x400>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
|
17
Bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
Normal file
17
Bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
Normal file
@ -0,0 +1,17 @@
|
||||
* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "cirrus,clps711x-mctrl-gpio".
|
||||
- gpio-controller: Marks the device node as a gpio controller.
|
||||
- #gpio-cells: Should be two. The first cell is the pin number and
|
||||
the second cell is used to specify the gpio polarity:
|
||||
0 = Active high,
|
||||
1 = Active low.
|
||||
|
||||
Example:
|
||||
sysgpio: sysgpio {
|
||||
compatible = "cirrus,ep7312-mctrl-gpio",
|
||||
"cirrus,clps711x-mctrl-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
16
Bindings/gpio/gpio-zevio.txt
Normal file
16
Bindings/gpio/gpio-zevio.txt
Normal file
@ -0,0 +1,16 @@
|
||||
Zevio GPIO controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "lsi,zevio-gpio"
|
||||
- reg: Address and length of the register set for the device
|
||||
- #gpio-cells: Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters (currently unused).
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
|
||||
Example:
|
||||
gpio: gpio@90000000 {
|
||||
compatible = "lsi,zevio-gpio";
|
||||
reg = <0x90000000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
26
Bindings/gpio/gpio-zynq.txt
Normal file
26
Bindings/gpio/gpio-zynq.txt
Normal file
@ -0,0 +1,26 @@
|
||||
Xilinx Zynq GPIO controller Device Tree Bindings
|
||||
-------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- #gpio-cells : Should be two
|
||||
- First cell is the GPIO line number
|
||||
- Second cell is used to specify optional
|
||||
parameters (unused)
|
||||
- compatible : Should be "xlnx,zynq-gpio-1.0"
|
||||
- clocks : Clock specifier (see clock bindings for details)
|
||||
- gpio-controller : Marks the device node as a GPIO controller.
|
||||
- interrupts : Interrupt specifier (see interrupt bindings for
|
||||
details)
|
||||
- interrupt-parent : Must be core interrupt controller
|
||||
- reg : Address and length of the register set for the device
|
||||
|
||||
Example:
|
||||
gpio@e000a000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "xlnx,zynq-gpio-1.0";
|
||||
clocks = <&clkc 42>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 20 4>;
|
||||
reg = <0xe000a000 0x1000>;
|
||||
};
|
60
Bindings/gpio/snps-dwapb-gpio.txt
Normal file
60
Bindings/gpio/snps-dwapb-gpio.txt
Normal file
@ -0,0 +1,60 @@
|
||||
* Synopsys DesignWare APB GPIO controller
|
||||
|
||||
Required properties:
|
||||
- compatible : Should contain "snps,dw-apb-gpio"
|
||||
- reg : Address and length of the register set for the device.
|
||||
- #address-cells : should be 1 (for addressing port subnodes).
|
||||
- #size-cells : should be 0 (port subnodes).
|
||||
|
||||
The GPIO controller has a configurable number of ports, each of which are
|
||||
represented as child nodes with the following properties:
|
||||
|
||||
Required properties:
|
||||
- compatible : "snps,dw-apb-gpio-port"
|
||||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and
|
||||
the second cell is used to specify the gpio polarity:
|
||||
0 = active high
|
||||
1 = active low
|
||||
- reg : The integer port index of the port, a single cell.
|
||||
|
||||
Optional properties:
|
||||
- interrupt-controller : The first port may be configured to be an interrupt
|
||||
controller.
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt. Shall be set to 2. The first cell defines the interrupt number,
|
||||
the second encodes the triger flags encoded as described in
|
||||
Documentation/devicetree/bindings/interrupts.txt
|
||||
- interrupt-parent : The parent interrupt controller.
|
||||
- interrupts : The interrupt to the parent controller raised when GPIOs
|
||||
generate the interrupts.
|
||||
- snps,nr-gpios : The number of pins in the port, a single cell.
|
||||
|
||||
Example:
|
||||
|
||||
gpio: gpio@20000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x20000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
|
||||
portb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
43
Bindings/gpu/nvidia,gk20a.txt
Normal file
43
Bindings/gpu/nvidia,gk20a.txt
Normal file
@ -0,0 +1,43 @@
|
||||
NVIDIA GK20A Graphics Processing Unit
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,<chip>-<gpu>"
|
||||
Currently recognized values:
|
||||
- nvidia,tegra124-gk20a
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
Must contain two entries:
|
||||
- first entry for bar0
|
||||
- second entry for bar1
|
||||
- interrupts: Must contain an entry for each entry in interrupt-names.
|
||||
See ../interrupt-controller/interrupts.txt for details.
|
||||
- interrupt-names: Must include the following entries:
|
||||
- stall
|
||||
- nonstall
|
||||
- vdd-supply: regulator for supply voltage.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- gpu
|
||||
- pwr
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- gpu
|
||||
|
||||
Example:
|
||||
|
||||
gpu@0,57000000 {
|
||||
compatible = "nvidia,gk20a";
|
||||
reg = <0x0 0x57000000 0x0 0x01000000>,
|
||||
<0x0 0x58000000 0x0 0x01000000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
vdd-supply = <&vdd_gpu>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_GPU>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
|
||||
clock-names = "gpu", "pwr";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
status = "disabled";
|
||||
};
|
189
Bindings/gpu/st,stih4xx.txt
Normal file
189
Bindings/gpu/st,stih4xx.txt
Normal file
@ -0,0 +1,189 @@
|
||||
STMicroelectronics stih4xx platforms
|
||||
|
||||
- sti-vtg: video timing generator
|
||||
Required properties:
|
||||
- compatible: "st,vtg"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
Optional properties:
|
||||
- interrupts : VTG interrupt number to the CPU.
|
||||
- st,slave: phandle on a slave vtg
|
||||
|
||||
- sti-vtac: video timing advanced inter dye communication Rx and TX
|
||||
Required properties:
|
||||
- compatible: "st,vtac-main" or "st,vtac-aux"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
|
||||
- sti-display-subsystem: Master device for DRM sub-components
|
||||
This device must be the parent of all the sub-components and is responsible
|
||||
of bind them.
|
||||
Required properties:
|
||||
- compatible: "st,sti-display-subsystem"
|
||||
- ranges: to allow probing of subdevices
|
||||
|
||||
- sti-compositor: frame compositor engine
|
||||
must be a child of sti-display-subsystem
|
||||
Required properties:
|
||||
- compatible: "st,stih<chip>-compositor"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
- resets: resets to be used by the device
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: names of the resets listed in resets property in the same
|
||||
order.
|
||||
- st,vtg: phandle(s) on vtg device (main and aux) nodes.
|
||||
|
||||
- sti-tvout: video out hardware block
|
||||
must be a child of sti-display-subsystem
|
||||
Required properties:
|
||||
- compatible: "st,stih<chip>-tvout"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- reg-names: names of the mapped memory regions listed in regs property in
|
||||
the same order.
|
||||
- resets: resets to be used by the device
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: names of the resets listed in resets property in the same
|
||||
order.
|
||||
- ranges: to allow probing of subdevices
|
||||
|
||||
- sti-hdmi: hdmi output block
|
||||
must be a child of sti-tvout
|
||||
Required properties:
|
||||
- compatible: "st,stih<chip>-hdmi";
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- reg-names: names of the mapped memory regions listed in regs property in
|
||||
the same order.
|
||||
- interrupts : HDMI interrupt number to the CPU.
|
||||
- interrupt-names: name of the interrupts listed in interrupts property in
|
||||
the same order
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
- hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
|
||||
|
||||
sti-hda:
|
||||
Required properties:
|
||||
must be a child of sti-tvout
|
||||
- compatible: "st,stih<chip>-hda"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- reg-names: names of the mapped memory regions listed in regs property in
|
||||
the same order.
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
vtg_main_slave: sti-vtg-main-slave@fe85A800 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfe85A800 0x300>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
vtg_main: sti-vtg-main-master@fd348000 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfd348000 0x400>;
|
||||
st,slave = <&vtg_main_slave>;
|
||||
};
|
||||
|
||||
vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfe858200 0x300>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
vtg_aux: sti-vtg-aux-master@fd348400 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfd348400 0x400>;
|
||||
st,slave = <&vtg_aux_slave>;
|
||||
};
|
||||
|
||||
|
||||
sti-vtac-rx-main@fee82800 {
|
||||
compatible = "st,vtac-main";
|
||||
reg = <0xfee82800 0x200>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
|
||||
};
|
||||
|
||||
sti-vtac-rx-aux@fee82a00 {
|
||||
compatible = "st,vtac-aux";
|
||||
reg = <0xfee82a00 0x200>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
|
||||
};
|
||||
|
||||
sti-vtac-tx-main@fd349000 {
|
||||
compatible = "st,vtac-main";
|
||||
reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
|
||||
};
|
||||
|
||||
sti-vtac-tx-aux@fd349200 {
|
||||
compatible = "st,vtac-aux";
|
||||
reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
|
||||
};
|
||||
|
||||
sti-display-subsystem {
|
||||
compatible = "st,sti-display-subsystem";
|
||||
ranges;
|
||||
|
||||
sti-compositor@fd340000 {
|
||||
compatible = "st,stih416-compositor";
|
||||
reg = <0xfd340000 0x1000>;
|
||||
clock-names = "compo_main", "compo_aux",
|
||||
"pix_main", "pix_aux";
|
||||
clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
|
||||
<&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
|
||||
reset-names = "compo-main", "compo-aux";
|
||||
resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
|
||||
st,vtg = <&vtg_main>, <&vtg_aux>;
|
||||
};
|
||||
|
||||
sti-tvout@fe000000 {
|
||||
compatible = "st,stih416-tvout";
|
||||
reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
|
||||
reg-names = "tvout-reg", "hda-reg", "syscfg";
|
||||
reset-names = "tvout";
|
||||
resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
|
||||
ranges;
|
||||
|
||||
sti-hdmi@fe85c000 {
|
||||
compatible = "st,stih416-hdmi";
|
||||
reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
|
||||
reg-names = "hdmi-reg", "syscfg";
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "irq";
|
||||
clock-names = "pix", "tmds", "phy", "audio";
|
||||
clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
|
||||
hdmi,hpd-gpio = <&PIO2 5>;
|
||||
};
|
||||
|
||||
sti-hda@fe85a000 {
|
||||
compatible = "st,stih416-hda";
|
||||
reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
|
||||
reg-names = "hda-reg", "video-dacs-ctrl";
|
||||
clock-names = "pix", "hddac";
|
||||
clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
129
Bindings/graph.txt
Normal file
129
Bindings/graph.txt
Normal file
@ -0,0 +1,129 @@
|
||||
Common bindings for device graphs
|
||||
|
||||
General concept
|
||||
---------------
|
||||
|
||||
The hierarchical organisation of the device tree is well suited to describe
|
||||
control flow to devices, but there can be more complex connections between
|
||||
devices that work together to form a logical compound device, following an
|
||||
arbitrarily complex graph.
|
||||
There already is a simple directed graph between devices tree nodes using
|
||||
phandle properties pointing to other nodes to describe connections that
|
||||
can not be inferred from device tree parent-child relationships. The device
|
||||
tree graph bindings described herein abstract more complex devices that can
|
||||
have multiple specifiable ports, each of which can be linked to one or more
|
||||
ports of other devices.
|
||||
|
||||
These common bindings do not contain any information about the direction or
|
||||
type of the connections, they just map their existence. Specific properties
|
||||
may be described by specialized bindings depending on the type of connection.
|
||||
|
||||
To see how this binding applies to video pipelines, for example, see
|
||||
Documentation/device-tree/bindings/media/video-interfaces.txt.
|
||||
Here the ports describe data interfaces, and the links between them are
|
||||
the connecting data buses. A single port with multiple connections can
|
||||
correspond to multiple devices being connected to the same physical bus.
|
||||
|
||||
Organisation of ports and endpoints
|
||||
-----------------------------------
|
||||
|
||||
Ports are described by child 'port' nodes contained in the device node.
|
||||
Each port node contains an 'endpoint' subnode for each remote device port
|
||||
connected to this port. If a single port is connected to more than one
|
||||
remote device, an 'endpoint' child node must be provided for each link.
|
||||
If more than one port is present in a device node or there is more than one
|
||||
endpoint at a port, or a port node needs to be associated with a selected
|
||||
hardware interface, a common scheme using '#address-cells', '#size-cells'
|
||||
and 'reg' properties is used number the nodes.
|
||||
|
||||
device {
|
||||
...
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
endpoint@0 {
|
||||
reg = <0>;
|
||||
...
|
||||
};
|
||||
endpoint@1 {
|
||||
reg = <1>;
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint { ... };
|
||||
};
|
||||
};
|
||||
|
||||
All 'port' nodes can be grouped under an optional 'ports' node, which
|
||||
allows to specify #address-cells, #size-cells properties for the 'port'
|
||||
nodes independently from any other child device nodes a device might
|
||||
have.
|
||||
|
||||
device {
|
||||
...
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
...
|
||||
endpoint@0 { ... };
|
||||
endpoint@1 { ... };
|
||||
};
|
||||
|
||||
port@1 { ... };
|
||||
};
|
||||
};
|
||||
|
||||
Links between endpoints
|
||||
-----------------------
|
||||
|
||||
Each endpoint should contain a 'remote-endpoint' phandle property that points
|
||||
to the corresponding endpoint in the port of the remote device. In turn, the
|
||||
remote endpoint should contain a 'remote-endpoint' property. If it has one,
|
||||
it must not point to another than the local endpoint. Two endpoints with their
|
||||
'remote-endpoint' phandles pointing at each other form a link between the
|
||||
containing ports.
|
||||
|
||||
device-1 {
|
||||
port {
|
||||
device_1_output: endpoint {
|
||||
remote-endpoint = <&device_2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
device-2 {
|
||||
port {
|
||||
device_2_input: endpoint {
|
||||
remote-endpoint = <&device_1_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
If there is more than one 'port' or more than one 'endpoint' node or 'reg'
|
||||
property is present in port and/or endpoint nodes the following properties
|
||||
are required in a relevant parent node:
|
||||
|
||||
- #address-cells : number of cells required to define port/endpoint
|
||||
identifier, should be 1.
|
||||
- #size-cells : should be zero.
|
||||
|
||||
Optional endpoint properties
|
||||
----------------------------
|
||||
|
||||
- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
|
||||
|
44
Bindings/hsi/client-devices.txt
Normal file
44
Bindings/hsi/client-devices.txt
Normal file
@ -0,0 +1,44 @@
|
||||
Each HSI port is supposed to have one child node, which
|
||||
symbols the remote device connected to the HSI port. The
|
||||
following properties are standardized for HSI clients:
|
||||
|
||||
Required HSI configuration properties:
|
||||
|
||||
- hsi-channel-ids: A list of channel ids
|
||||
|
||||
- hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame")
|
||||
- hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame")
|
||||
- hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if
|
||||
the transmission mode is the same for receiver and
|
||||
transmitter
|
||||
- hsi-speed-kbps: Max bit transmission speed in kbit/s
|
||||
- hsi-flow: RX flow type ("synchronized" or "pipeline")
|
||||
- hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority")
|
||||
|
||||
Optional HSI configuration properties:
|
||||
|
||||
- hsi-channel-names: A list with one name per channel specified in the
|
||||
hsi-channel-ids property
|
||||
|
||||
|
||||
Device Tree node example for an HSI client:
|
||||
|
||||
hsi-controller {
|
||||
hsi-port {
|
||||
modem: hsi-client {
|
||||
compatible = "nokia,n900-modem";
|
||||
|
||||
hsi-channel-ids = <0>, <1>, <2>, <3>;
|
||||
hsi-channel-names = "mcsaab-control",
|
||||
"speech-control",
|
||||
"speech-data",
|
||||
"mcsaab-data";
|
||||
hsi-speed-kbps = <55000>;
|
||||
hsi-mode = "frame";
|
||||
hsi-flow = "synchronized";
|
||||
hsi-arb-mode = "round-robin";
|
||||
|
||||
/* more client specific properties */
|
||||
};
|
||||
};
|
||||
};
|
57
Bindings/hsi/nokia-modem.txt
Normal file
57
Bindings/hsi/nokia-modem.txt
Normal file
@ -0,0 +1,57 @@
|
||||
Nokia modem client bindings
|
||||
|
||||
The Nokia modem HSI client follows the common HSI client binding
|
||||
and inherits all required properties. The following additional
|
||||
properties are needed by the Nokia modem HSI client:
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
"nokia,n900-modem"
|
||||
- hsi-channel-names: Should contain the following strings
|
||||
"mcsaab-control"
|
||||
"speech-control"
|
||||
"speech-data"
|
||||
"mcsaab-data"
|
||||
- gpios: Should provide a GPIO handler for each GPIO listed in
|
||||
gpio-names
|
||||
- gpio-names: Should contain the following strings
|
||||
"cmt_apeslpx"
|
||||
"cmt_rst_rq"
|
||||
"cmt_en"
|
||||
"cmt_rst"
|
||||
"cmt_bsi"
|
||||
- interrupts: Should be IRQ handle for modem's reset indication
|
||||
|
||||
Example:
|
||||
|
||||
&ssi_port {
|
||||
modem: hsi-client {
|
||||
compatible = "nokia,n900-modem";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&modem_pins>;
|
||||
|
||||
hsi-channel-ids = <0>, <1>, <2>, <3>;
|
||||
hsi-channel-names = "mcsaab-control",
|
||||
"speech-control",
|
||||
"speech-data",
|
||||
"mcsaab-data";
|
||||
hsi-speed-kbps = <55000>;
|
||||
hsi-mode = "frame";
|
||||
hsi-flow = "synchronized";
|
||||
hsi-arb-mode = "round-robin";
|
||||
|
||||
interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
|
||||
|
||||
gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
|
||||
<&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
|
||||
<&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
|
||||
<&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
|
||||
<&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
|
||||
gpio-names = "cmt_apeslpx",
|
||||
"cmt_rst_rq",
|
||||
"cmt_en",
|
||||
"cmt_rst",
|
||||
"cmt_bsi";
|
||||
};
|
||||
};
|
97
Bindings/hsi/omap-ssi.txt
Normal file
97
Bindings/hsi/omap-ssi.txt
Normal file
@ -0,0 +1,97 @@
|
||||
OMAP SSI controller bindings
|
||||
|
||||
OMAP Synchronous Serial Interface (SSI) controller implements a legacy
|
||||
variant of MIPI's High Speed Synchronous Serial Interface (HSI).
|
||||
|
||||
Required properties:
|
||||
- compatible: Should include "ti,omap3-ssi".
|
||||
- reg-names: Contains the values "sys" and "gdd" (in this order).
|
||||
- reg: Contains a matching register specifier for each entry
|
||||
in reg-names.
|
||||
- interrupt-names: Contains the value "gdd_mpu".
|
||||
- interrupts: Contains matching interrupt information for each entry
|
||||
in interrupt-names.
|
||||
- ranges: Represents the bus address mapping between the main
|
||||
controller node and the child nodes below.
|
||||
- clock-names: Must include the following entries:
|
||||
"ssi_ssr_fck": The OMAP clock of that name
|
||||
"ssi_sst_fck": The OMAP clock of that name
|
||||
"ssi_ick": The OMAP clock of that name
|
||||
- clocks: Contains a matching clock specifier for each entry in
|
||||
clock-names.
|
||||
- #address-cells: Should be set to <1>
|
||||
- #size-cells: Should be set to <1>
|
||||
|
||||
Each port is represented as a sub-node of the ti,omap3-ssi device.
|
||||
|
||||
Required Port sub-node properties:
|
||||
- compatible: Should be set to the following value
|
||||
ti,omap3-ssi-port (applicable to OMAP34xx devices)
|
||||
- reg-names: Contains the values "tx" and "rx" (in this order).
|
||||
- reg: Contains a matching register specifier for each entry
|
||||
in reg-names.
|
||||
- interrupt-parent Should be a phandle for the interrupt controller
|
||||
- interrupts: Should contain interrupt specifiers for mpu interrupts
|
||||
0 and 1 (in this order).
|
||||
- ti,ssi-cawake-gpio: Defines which GPIO pin is used to signify CAWAKE
|
||||
events for the port. This is an optional board-specific
|
||||
property. If it's missing the port will not be
|
||||
enabled.
|
||||
|
||||
Example for Nokia N900:
|
||||
|
||||
ssi-controller@48058000 {
|
||||
compatible = "ti,omap3-ssi";
|
||||
|
||||
/* needed until hwmod is updated to use the compatible string */
|
||||
ti,hwmods = "ssi";
|
||||
|
||||
reg = <0x48058000 0x1000>,
|
||||
<0x48059000 0x1000>;
|
||||
reg-names = "sys",
|
||||
"gdd";
|
||||
|
||||
interrupts = <55>;
|
||||
interrupt-names = "gdd_mpu";
|
||||
|
||||
clocks = <&ssi_ssr_fck>,
|
||||
<&ssi_sst_fck>,
|
||||
<&ssi_ick>;
|
||||
clock-names = "ssi_ssr_fck",
|
||||
"ssi_sst_fck",
|
||||
"ssi_ick";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
ssi-port@4805a000 {
|
||||
compatible = "ti,omap3-ssi-port";
|
||||
|
||||
reg = <0x4805a000 0x800>,
|
||||
<0x4805a800 0x800>;
|
||||
reg-names = "tx",
|
||||
"rx";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <67>,
|
||||
<68>;
|
||||
|
||||
ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
|
||||
}
|
||||
|
||||
ssi-port@4805a000 {
|
||||
compatible = "ti,omap3-ssi-port";
|
||||
|
||||
reg = <0x4805b000 0x800>,
|
||||
<0x4805b800 0x800>;
|
||||
reg-names = "tx",
|
||||
"rx";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <69>,
|
||||
<70>;
|
||||
|
||||
status = "disabled"; /* second port is not used on N900 */
|
||||
}
|
||||
}
|
23
Bindings/hwmon/ibmpowernv.txt
Normal file
23
Bindings/hwmon/ibmpowernv.txt
Normal file
@ -0,0 +1,23 @@
|
||||
IBM POWERNV platform sensors
|
||||
----------------------------
|
||||
|
||||
Required node properties:
|
||||
- compatible: must be one of
|
||||
"ibm,opal-sensor-cooling-fan"
|
||||
"ibm,opal-sensor-amb-temp"
|
||||
"ibm,opal-sensor-power-supply"
|
||||
"ibm,opal-sensor-power"
|
||||
- sensor-id: an opaque id provided by the firmware to the kernel, identifies a
|
||||
given sensor and its attribute data
|
||||
|
||||
Example sensors node:
|
||||
|
||||
cooling-fan#8-data {
|
||||
sensor-id = <0x7052107>;
|
||||
compatible = "ibm,opal-sensor-cooling-fan";
|
||||
};
|
||||
|
||||
amb-temp#1-thrs {
|
||||
sensor-id = <0x5096000>;
|
||||
compatible = "ibm,opal-sensor-amb-temp";
|
||||
};
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user