According to SATA specification, when Serial ATA Enclosure Management Bridge
(SEMB) is unable to communicate to Storage Enclosure Processor (SEP), in response to hard and soft resets it should among other things return value 0x7F in Status register. The weird side is that it means DRQ bit set, which tells that reset request is not completed. It would be fine if SEMB was the only device on port. But if SEMB connected to PMP or built into it, it may block access to other devices sharing same SATA port. Make some tunings/fixes to soft-reset handling to workaround the issue: - ahci(4): request CLO on the port after soft reset to ignore DRQ bit; - siis(4): gracefully reinitialize port after soft reset timeout (hardware doesn't detect reset request completion in this case); - mvs(4): if PMP is used, send dummy soft-reset to the PMP port to make it clear DRQ bit for us. For now this makes quirks in ata_pmp.c, hiding SEMB ports of SiI3726/SiI4726 PMPs, less important. Further, if hardware permit, I hope to implement real SEMB support.
This commit is contained in:
parent
ceef8f2477
commit
08c8fde007
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=222285
@ -1835,9 +1835,11 @@ ahci_execute_transaction(struct ahci_slot *slot)
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if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
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break;
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if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) {
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#if 0
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device_printf(ch->dev,
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"Poll error on slot %d, TFD: %04x\n",
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slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
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#endif
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et = AHCI_ERR_TFE;
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break;
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}
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@ -1877,14 +1879,12 @@ ahci_execute_transaction(struct ahci_slot *slot)
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}
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}
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}
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ahci_end_transaction(slot, et);
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/* Kick controller into sane state and enable FBS. */
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if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
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(ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
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(ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
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ahci_stop(ch->dev);
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ahci_start(ch->dev, 1);
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}
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(ccb->ataio.cmd.control & ATA_A_RESET) == 0)
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ch->eslots |= (1 << slot->slot);
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ahci_end_transaction(slot, et);
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return;
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}
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/* Start command execution timeout */
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@ -2169,13 +2169,6 @@ ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
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ch->numhslots++;
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} else
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xpt_done(ccb);
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/* Unfreeze frozen command. */
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if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
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union ccb *fccb = ch->frozen;
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ch->frozen = NULL;
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ahci_begin_transaction(dev, fccb);
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xpt_release_simq(ch->sim, TRUE);
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}
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/* If we have no other active commands, ... */
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if (ch->rslots == 0) {
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/* if there was fatal error - reset port. */
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@ -2185,6 +2178,7 @@ ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
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/* if we have slots in error, we can reinit port. */
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if (ch->eslots != 0) {
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ahci_stop(dev);
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ahci_clo(dev);
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ahci_start(dev, 1);
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}
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/* if there commands on hold, we can do READ LOG. */
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@ -2195,6 +2189,13 @@ ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
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} else if ((ch->rslots & ~ch->toslots) == 0 &&
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et != AHCI_ERR_TIMEOUT)
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ahci_rearm_timeout(dev);
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/* Unfreeze frozen command. */
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if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
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union ccb *fccb = ch->frozen;
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ch->frozen = NULL;
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ahci_begin_transaction(dev, fccb);
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xpt_release_simq(ch->sim, TRUE);
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}
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/* Start PM timer. */
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if (ch->numrslots == 0 && ch->pm_level > 3 &&
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(ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
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@ -1738,13 +1738,6 @@ mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et)
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ch->numhslots++;
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} else
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xpt_done(ccb);
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/* Unfreeze frozen command. */
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if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) {
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union ccb *fccb = ch->frozen;
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ch->frozen = NULL;
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mvs_begin_transaction(dev, fccb);
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xpt_release_simq(ch->sim, TRUE);
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}
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/* If we have no other active commands, ... */
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if (ch->rslots == 0) {
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/* if there was fatal error - reset port. */
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@ -1764,6 +1757,13 @@ mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et)
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} else if ((ch->rslots & ~ch->toslots) == 0 &&
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et != MVS_ERR_TIMEOUT)
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mvs_rearm_timeout(dev);
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/* Unfreeze frozen command. */
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if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) {
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union ccb *fccb = ch->frozen;
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ch->frozen = NULL;
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mvs_begin_transaction(dev, fccb);
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xpt_release_simq(ch->sim, TRUE);
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}
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/* Start PM timer. */
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if (ch->numrslots == 0 && ch->pm_level > 3 &&
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(ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
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@ -2080,7 +2080,8 @@ mvs_softreset(device_t dev, union ccb *ccb)
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{
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struct mvs_channel *ch = device_get_softc(dev);
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int port = ccb->ccb_h.target_id & 0x0f;
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int i;
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int i, stuck;
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uint8_t status;
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mvs_set_edma_mode(dev, MVS_EDMA_OFF);
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ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
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@ -2089,12 +2090,35 @@ mvs_softreset(device_t dev, union ccb *ccb)
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ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
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ccb->ccb_h.status &= ~CAM_STATUS_MASK;
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/* Wait for clearing busy status. */
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if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout)) < 0) {
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if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) {
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ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
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stuck = 1;
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} else {
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ccb->ccb_h.status |= CAM_REQ_CMP;
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status = mvs_getstatus(dev, 0);
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if (status & ATA_S_ERROR)
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ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
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else
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ccb->ccb_h.status |= CAM_REQ_CMP;
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if (status & ATA_S_DRQ)
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stuck = 1;
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else
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stuck = 0;
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}
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mvs_tfd_read(dev, ccb);
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/*
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* XXX: If some device on PMP failed to soft-reset,
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* try to recover by sending dummy soft-reset to PMP.
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*/
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if (stuck && ch->pm_present && port != 15) {
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ATA_OUTB(ch->r_mem, SATA_SATAICTL,
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15 << SATA_SATAICTL_PMPTX_SHIFT);
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ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
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DELAY(10000);
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ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
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mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout);
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}
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xpt_done(ccb);
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}
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@ -1178,11 +1178,22 @@ siis_timeout(struct siis_slot *slot)
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{
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device_t dev = slot->dev;
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struct siis_channel *ch = device_get_softc(dev);
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union ccb *ccb = slot->ccb;
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mtx_assert(&ch->mtx, MA_OWNED);
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/* Check for stale timeout. */
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if (slot->state < SIIS_SLOT_RUNNING)
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return;
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/* Handle soft-reset timeouts without doing hard-reset. */
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if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
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(ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
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(ccb->ataio.cmd.control & ATA_A_RESET)) {
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xpt_freeze_simq(ch->sim, ch->numrslots);
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siis_end_transaction(slot, SIIS_ERR_TFE);
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return;
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}
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device_printf(dev, "Timeout on slot %d\n", slot->slot);
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device_printf(dev, "%s is %08x ss %08x rs %08x es %08x sts %08x serr %08x\n",
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__func__, ATA_INL(ch->r_mem, SIIS_P_IS),
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@ -1331,13 +1342,6 @@ siis_end_transaction(struct siis_slot *slot, enum siis_err_type et)
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ch->numhslots++;
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} else
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xpt_done(ccb);
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/* Unfreeze frozen command. */
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if (ch->frozen && !siis_check_collision(dev, ch->frozen)) {
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union ccb *fccb = ch->frozen;
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ch->frozen = NULL;
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siis_begin_transaction(dev, fccb);
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xpt_release_simq(ch->sim, TRUE);
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}
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/* If we have no other active commands, ... */
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if (ch->rslots == 0) {
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/* if there were timeouts or fatal error - reset port. */
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@ -1355,6 +1359,13 @@ siis_end_transaction(struct siis_slot *slot, enum siis_err_type et)
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} else if ((ch->rslots & ~ch->toslots) == 0 &&
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et != SIIS_ERR_TIMEOUT)
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siis_rearm_timeout(dev);
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/* Unfreeze frozen command. */
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if (ch->frozen && !siis_check_collision(dev, ch->frozen)) {
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union ccb *fccb = ch->frozen;
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ch->frozen = NULL;
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siis_begin_transaction(dev, fccb);
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xpt_release_simq(ch->sim, TRUE);
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}
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}
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static void
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