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Sync instruction cache's after writing user breakpoints on MIPS.

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Add an implementation for pmaps_sync_icache() on MIPS that sync's the
instruction cache on all CPUs via smp_rendezvous() after a debugger
inserts a breakpoint via ptrace(PT_IO).

Tested by:	kan (on Creator CI20 running Ingenic JZ4780 SOC)
MFC after:	2 weeks
Sponsored by:	DARPA / AFRL
This commit is contained in:
John Baldwin 2016-11-15 17:01:48 +00:00
parent 4352999e0e
commit 08dc89a621
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=308690
1 changed files with 10 additions and 4 deletions
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14
sys/mips/mips/pmap.c
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@ -74,11 +74,7 @@ __FBSDID("$FreeBSD$");
#include <sys/proc.h>
#include <sys/rwlock.h>
#include <sys/sched.h>
#ifdef SMP
#include <sys/smp.h>
#else
#include <sys/cpuset.h>
#endif
#include <sys/sysctl.h>
#include <sys/vmmeter.h>
@ -3266,9 +3262,19 @@ pmap_activate(struct thread *td)
critical_exit();
}
static void
pmap_sync_icache_one(void *arg __unused)
{
mips_icache_sync_all();
mips_dcache_wbinv_all();
}
void
pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
{
smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
}
/*