riscv/sifive: add SiFive FU540 PRCI driver
The SiFive FU540 Power Reset Clocking Interrupt block contains a PLL that turns the input crystal (33.3MHz) into a 1-1.5GHz clock. This clock in turn is divided by two to produce the tlclk, which is fed into devices such as the SPI and I2C controllers. Register a new clock device for the PRCI so that those devices can read the correct clock through the clk framework. Submitted by: kp Sponsored by: Axiado
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=355920
3
sys/riscv/sifive/files.sifive
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3
sys/riscv/sifive/files.sifive
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# $FreeBSD$
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riscv/sifive/fu540_prci.c standard
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268
sys/riscv/sifive/fu540_prci.c
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268
sys/riscv/sifive/fu540_prci.c
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Axiado Corporation
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* All rights reserved.
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*
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* This software was developed in part by Kristof Provost under contract for
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* Axiado Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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static struct resource_spec prci_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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RESOURCE_SPEC_END
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};
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struct prci_softc {
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device_t dev;
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struct mtx mtx;
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struct clkdom *clkdom;
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struct resource *res;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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};
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struct prci_clk_pll_sc {
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struct prci_softc *parent_sc;
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};
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#define PRCI_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define PRCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define PRCI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
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#define PRCI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
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#define PRCI_COREPLL 0x4
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#define PRCI_COREPLL_DIVR_MASK 0x3f
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#define PRCI_COREPLL_DIVR_SHIFT 0
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#define PRCI_COREPLL_DIVF_MASK 0x7fc0
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#define PRCI_COREPLL_DIVF_SHIFT 6
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#define PRCI_COREPLL_DIVQ_MASK 0x38000
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#define PRCI_COREPLL_DIVQ_SHIFT 15
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#define PRCI_READ(_sc, _reg) \
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bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
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static int
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prci_clk_pll_init(struct clknode *clk, device_t dev)
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{
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static int
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prci_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct prci_clk_pll_sc *sc;
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struct clknode *parent_clk;
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uint32_t val;
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uint64_t refclk, divf, divq, divr;
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int err;
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KASSERT(freq != NULL, ("freq cannot be NULL"));
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sc = clknode_get_softc(clk);
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PRCI_LOCK(sc->parent_sc);
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/* Get refclock frequency. */
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parent_clk = clknode_get_parent(clk);
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err = clknode_get_freq(parent_clk, &refclk);
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if (err) {
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device_printf(sc->parent_sc->dev,
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"Failed to get refclk frequency\n");
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PRCI_UNLOCK(sc->parent_sc);
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return (err);
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}
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/* Calculate the PLL output */
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val = PRCI_READ(sc->parent_sc, PRCI_COREPLL);
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divf = (val & PRCI_COREPLL_DIVF_MASK) >> PRCI_COREPLL_DIVF_SHIFT;
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divq = (val & PRCI_COREPLL_DIVQ_MASK) >> PRCI_COREPLL_DIVQ_SHIFT;
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divr = (val & PRCI_COREPLL_DIVR_MASK) >> PRCI_COREPLL_DIVR_SHIFT;
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*freq = refclk / (divr + 1) * (2 * (divf + 1)) / (1 << divq);
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PRCI_UNLOCK(sc->parent_sc);
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return (0);
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}
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static clknode_method_t prci_clk_pll_clknode_methods[] = {
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CLKNODEMETHOD(clknode_init, prci_clk_pll_init),
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CLKNODEMETHOD(clknode_recalc_freq, prci_clk_pll_recalc),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(prci_clk_pll_clknode, prci_clk_pll_clknode_class,
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prci_clk_pll_clknode_methods, sizeof(struct prci_clk_pll_sc),
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clknode_class);
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static int
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prci_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "sifive,aloeprci0"))
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return (ENXIO);
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device_set_desc(dev, "SiFive FU540 Power Reset Clocking Interrupt");
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return (BUS_PROBE_DEFAULT);
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}
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static void
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prci_pll_register(struct prci_softc *parent_sc, struct clknode_init_def *clkdef)
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{
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struct clknode *clk;
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struct prci_clk_pll_sc *sc;
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clk = clknode_create(parent_sc->clkdom, &prci_clk_pll_clknode_class,
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clkdef);
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if (clk == NULL)
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panic("Failed to create clknode");
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sc = clknode_get_softc(clk);
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sc->parent_sc = parent_sc;
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clknode_register(parent_sc->clkdom, clk);
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}
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static int
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prci_attach(device_t dev)
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{
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struct clknode_init_def clkdef;
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struct prci_softc *sc;
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clk_t clk_parent;
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phandle_t node;
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int i, ncells, error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
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error = bus_alloc_resources(dev, prci_spec, &sc->res);
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if (error) {
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device_printf(dev, "Couldn't allocate resources\n");
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goto fail;
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}
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sc->bst = rman_get_bustag(sc->res);
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sc->bsh = rman_get_bushandle(sc->res);
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node = ofw_bus_get_node(dev);
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error = ofw_bus_parse_xref_list_get_length(node, "clocks",
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"#clock-cells", &ncells);
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if (error != 0 || ncells != 1) {
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device_printf(dev, "couldn't find parent clock\n");
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goto fail;
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}
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bzero(&clkdef, sizeof(clkdef));
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clkdef.id = 0;
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clkdef.name = "coreclk";
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clkdef.parent_names = mallocarray(ncells, sizeof(char *), M_OFWPROP,
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M_WAITOK);
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for (i = 0; i < ncells; i++) {
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error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
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if (error != 0) {
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device_printf(dev, "cannot get clock %d\n", error);
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goto fail1;
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}
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clkdef.parent_names[i] = clk_get_name(clk_parent);
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if (bootverbose)
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device_printf(dev, "clk parent: %s\n",
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clkdef.parent_names[i]);
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clk_release(clk_parent);
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}
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clkdef.parent_cnt = ncells;
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sc->clkdom = clkdom_create(dev);
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if (sc->clkdom == NULL) {
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device_printf(dev, "Couldn't create clock domain\n");
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goto fail;
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}
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/* We can't free a clkdom, so from now on we cannot fail. */
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prci_pll_register(sc, &clkdef);
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error = clkdom_finit(sc->clkdom);
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if (error)
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panic("Couldn't finalise clock domain");
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return (0);
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fail1:
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free(clkdef.parent_names, M_OFWPROP);
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fail:
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bus_release_resources(dev, prci_spec, &sc->res);
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mtx_destroy(&sc->mtx);
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return (error);
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}
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static device_method_t prci_methods[] = {
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DEVMETHOD(device_probe, prci_probe),
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DEVMETHOD(device_attach, prci_attach),
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DEVMETHOD_END
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};
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static driver_t prci_driver = {
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"fu540prci",
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prci_methods,
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sizeof(struct prci_softc)
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};
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static devclass_t prci_devclass;
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EARLY_DRIVER_MODULE(fu540prci, simplebus, prci_driver, prci_devclass, 0, 0,
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BUS_PASS_BUS);
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3
sys/riscv/sifive/std.sifive
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3
sys/riscv/sifive/std.sifive
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# $FreeBSD$
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files "../sifive/files.sifive"
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