e1000: add missing register defines

Added defines for the EEC, SHADOWINF and FLFWUPDATE registers needed for
the nvmupd_validate_offset function to correctly validate the NVM update
offset.

Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>

Approved by:	imp
Obtained from:	DPDK (2c7fe65ab9a31e6ebf438dad7ccc59bcde83a89f)
MFC after:	1 week
This commit is contained in:
Guinan Sun 2020-07-06 08:12:08 +00:00 committed by Kevin Bowling
parent a6f0cc373f
commit 09888d4bc1

View File

@ -169,6 +169,8 @@
#define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */
/* Shadow Ram Write Register - RW */
#define E1000_SRWR 0x12018
#define E1000_EEC_REG 0x12010
#define E1000_I210_FLMNGCTL 0x12038
#define E1000_I210_FLMNGDATA 0x1203C
#define E1000_I210_FLMNGCNT 0x12040
@ -179,6 +181,9 @@
#define E1000_I210_FLA 0x1201C
#define E1000_SHADOWINF 0x12068
#define E1000_FLFWUPDATE 0x12108
#define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
#define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */