Update llvm and clang to release_38 branch r261684.
This commit is contained in:
commit
09a17a1e45
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang380-import/; revision=296011
@ -1002,11 +1002,13 @@ void RAFast::AllocateBasicBlock() {
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unsigned DefOpEnd = MI->getNumOperands();
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if (MI->isCall()) {
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// Spill all virtregs before a call. This serves two purposes: 1. If an
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// Spill all virtregs before a call. This serves one purpose: If an
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// exception is thrown, the landing pad is going to expect to find
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// registers in their spill slots, and 2. we don't have to wade through
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// all the <imp-def> operands on the call instruction.
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DefOpEnd = VirtOpEnd;
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// registers in their spill slots.
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// Note: although this is appealing to just consider all definitions
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// as call-clobbered, this is not correct because some of those
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// definitions may be used later on and we do not want to reuse
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// those for virtual registers in between.
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DEBUG(dbgs() << " Spilling remaining registers before call.\n");
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spillAll(MI);
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@ -275,6 +275,18 @@ static bool isCSSave(MachineInstr *MBBI) {
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MBBI->getOpcode() == AArch64::STPDpre;
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}
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bool AArch64FrameLowering::canUseAsPrologue(
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const MachineBasicBlock &MBB) const {
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const MachineFunction *MF = MBB.getParent();
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const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
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const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
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// Don't need a scratch register if we're not going to re-align the stack.
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// Otherwise, we may need a scratch register to be available and we do not
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// support that for now.
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return !RegInfo->needsStackRealignment(*MF);
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}
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void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.begin();
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@ -37,6 +37,8 @@ class AArch64FrameLowering : public TargetFrameLowering {
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const override;
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int resolveFrameIndexReference(const MachineFunction &MF, int FI,
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@ -556,16 +556,42 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
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}
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}
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bool PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
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/* This function will do the following:
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- If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
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respectively (defaults recommended by the ABI) and return true
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- If MBB is not an entry block, initialize the register scavenger and look
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for available registers.
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- If the defaults (R0/R12) are available, return true
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- If TwoUniqueRegsRequired is set to true, it looks for two unique
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registers. Otherwise, look for a single available register.
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- If the required registers are found, set SR1 and SR2 and return true.
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- If the required registers are not found, set SR2 or both SR1 and SR2 to
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PPC::NoRegister and return false.
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Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired
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is not set, this function will attempt to find two different registers, but
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still return true if only one register is available (and set SR1 == SR2).
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*/
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bool
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PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
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bool UseAtEnd,
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unsigned *ScratchRegister) const {
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bool TwoUniqueRegsRequired,
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unsigned *SR1,
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unsigned *SR2) const {
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RegScavenger RS;
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unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
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unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
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if (ScratchRegister)
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*ScratchRegister = R0;
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// Set the defaults for the two scratch registers.
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if (SR1)
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*SR1 = R0;
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// If MBB is an entry or exit block, use R0 as the scratch register
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if (SR2) {
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assert (SR1 && "Asking for the second scratch register but not the first?");
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*SR2 = R12;
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}
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// If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
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if ((UseAtEnd && MBB->isReturnBlock()) ||
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(!UseAtEnd && (&MBB->getParent()->front() == MBB)))
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return true;
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@ -573,8 +599,8 @@ bool PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
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RS.enterBasicBlock(MBB);
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if (UseAtEnd && !MBB->empty()) {
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// The scratch register will be used at the end of the block, so must consider
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// all registers used within the block
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// The scratch register will be used at the end of the block, so must
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// consider all registers used within the block
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MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator();
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// If no terminator, back iterator up to previous instruction.
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@ -585,34 +611,85 @@ bool PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
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RS.forward(MBBI);
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}
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if (!RS.isRegUsed(R0))
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// If the two registers are available, we're all good.
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// Note that we only return here if both R0 and R12 are available because
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// although the function may not require two unique registers, it may benefit
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// from having two so we should try to provide them.
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if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
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return true;
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unsigned Reg = RS.FindUnusedReg(Subtarget.isPPC64() ? &PPC::G8RCRegClass
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: &PPC::GPRCRegClass);
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// Get the list of callee-saved registers for the target.
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const PPCRegisterInfo *RegInfo =
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static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
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const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
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// Make sure the register scavenger was able to find an available register
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// If not, use R0 but return false to indicate no register was available and
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// R0 must be used (as recommended by the ABI)
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if (Reg == 0)
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// Get all the available registers in the block.
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BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
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&PPC::GPRCRegClass);
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// We shouldn't use callee-saved registers as scratch registers as they may be
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// available when looking for a candidate block for shrink wrapping but not
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// available when the actual prologue/epilogue is being emitted because they
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// were added as live-in to the prologue block by PrologueEpilogueInserter.
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for (int i = 0; CSRegs[i]; ++i)
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BV.reset(CSRegs[i]);
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// Set the first scratch register to the first available one.
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if (SR1) {
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int FirstScratchReg = BV.find_first();
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*SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
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}
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// If there is another one available, set the second scratch register to that.
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// Otherwise, set it to either PPC::NoRegister if this function requires two
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// or to whatever SR1 is set to if this function doesn't require two.
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if (SR2) {
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int SecondScratchReg = BV.find_next(*SR1);
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if (SecondScratchReg != -1)
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*SR2 = SecondScratchReg;
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else
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*SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
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}
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// Now that we've done our best to provide both registers, double check
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// whether we were unable to provide enough.
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if (BV.count() < (TwoUniqueRegsRequired ? 2 : 1))
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return false;
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if (ScratchRegister)
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*ScratchRegister = Reg;
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return true;
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}
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// We need a scratch register for spilling LR and for spilling CR. By default,
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// we use two scratch registers to hide latency. However, if only one scratch
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// register is available, we can adjust for that by not overlapping the spill
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// code. However, if we need to realign the stack (i.e. have a base pointer)
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// and the stack frame is large, we need two scratch registers.
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bool
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PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
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const PPCRegisterInfo *RegInfo =
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static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
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MachineFunction &MF = *(MBB->getParent());
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bool HasBP = RegInfo->hasBasePointer(MF);
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unsigned FrameSize = determineFrameLayout(MF, false);
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int NegFrameSize = -FrameSize;
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bool IsLargeFrame = !isInt<16>(NegFrameSize);
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MachineFrameInfo *MFI = MF.getFrameInfo();
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unsigned MaxAlign = MFI->getMaxAlignment();
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return IsLargeFrame && HasBP && MaxAlign > 1;
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}
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bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {
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MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
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return findScratchRegister(TmpMBB, false, nullptr);
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return findScratchRegister(TmpMBB, false,
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twoUniqueScratchRegsRequired(TmpMBB));
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}
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bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
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MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
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return findScratchRegister(TmpMBB, true, nullptr);
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return findScratchRegister(TmpMBB, true);
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}
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void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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@ -664,6 +741,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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bool MustSaveLR = FI->mustSaveLR();
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const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
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bool MustSaveCR = !MustSaveCRs.empty();
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// Do we have a frame pointer and/or base pointer for this function?
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bool HasFP = hasFP(MF);
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bool HasBP = RegInfo->hasBasePointer(MF);
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@ -701,8 +779,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
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"FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
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findScratchRegister(&MBB, false, &ScratchReg);
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assert(ScratchReg && "No scratch register!");
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// Using the same bool variable as below to supress compiler warnings.
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bool SingleScratchReg =
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findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB),
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&ScratchReg, &TempReg);
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assert(SingleScratchReg &&
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"Required number of registers not available in this block");
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SingleScratchReg = ScratchReg == TempReg;
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int LROffset = getReturnSaveOffset();
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@ -748,13 +832,30 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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// indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
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bool isLargeFrame = !isInt<16>(NegFrameSize);
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assert((isPPC64 || !MustSaveCR) &&
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"Prologue CR saving supported only in 64-bit mode");
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// If we need to spill the CR and the LR but we don't have two separate
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// registers available, we must spill them one at a time
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if (MustSaveCR && SingleScratchReg && MustSaveLR) {
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// FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
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// If only one or two CR fields are clobbered, it could be more
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// efficient to use mfocrf to selectively save just those fields.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
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for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
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MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
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.addReg(TempReg, getKillRegState(true))
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.addImm(8)
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.addReg(SPReg);
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}
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
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assert((isPPC64 || MustSaveCRs.empty()) &&
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"Prologue CR saving supported only in 64-bit mode");
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if (!MustSaveCRs.empty()) { // will only occur for PPC64
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
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// FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
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// If only one or two CR fields are clobbered, it could be more
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// efficient to use mfocrf to selectively save just those fields.
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@ -792,7 +893,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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.addImm(LROffset)
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.addReg(SPReg);
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if (!MustSaveCRs.empty()) // will only occur for PPC64
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
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.addReg(TempReg, getKillRegState(true))
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.addImm(8)
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@ -811,6 +913,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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.addReg(SPReg);
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}
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// This condition must be kept in sync with canUseAsPrologue.
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if (HasBP && MaxAlign > 1) {
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if (isPPC64)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
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@ -828,6 +931,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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.addReg(ScratchReg, RegState::Kill)
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.addImm(NegFrameSize);
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} else {
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assert(!SingleScratchReg && "Only a single scratch reg available");
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BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
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.addImm(NegFrameSize >> 16);
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BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
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@ -951,7 +1055,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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// For SVR4, don't emit a move for the CR spill slot if we haven't
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// spilled CRs.
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if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
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&& MustSaveCRs.empty())
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&& !MustSaveCR)
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continue;
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// For 64-bit SVR4 when we have spilled CRs, the spill location
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@ -1005,6 +1109,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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bool MustSaveLR = FI->mustSaveLR();
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const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
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bool MustSaveCR = !MustSaveCRs.empty();
|
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// Do we have a frame pointer and/or base pointer for this function?
|
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bool HasFP = hasFP(MF);
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bool HasBP = RegInfo->hasBasePointer(MF);
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@ -1031,8 +1136,13 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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int FPOffset = 0;
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findScratchRegister(&MBB, true, &ScratchReg);
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assert(ScratchReg && "No scratch register!");
|
||||
// Using the same bool variable as below to supress compiler warnings.
|
||||
bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
|
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&TempReg);
|
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assert(SingleScratchReg &&
|
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"Could not find an available scratch register");
|
||||
|
||||
SingleScratchReg = ScratchReg == TempReg;
|
||||
|
||||
if (HasFP) {
|
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if (isSVR4ABI) {
|
||||
@ -1130,15 +1240,27 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
|
||||
}
|
||||
}
|
||||
|
||||
assert((isPPC64 || !MustSaveCR) &&
|
||||
"Epilogue CR restoring supported only in 64-bit mode");
|
||||
|
||||
// If we need to save both the LR and the CR and we only have one available
|
||||
// scratch register, we must do them one at a time.
|
||||
if (MustSaveCR && SingleScratchReg && MustSaveLR) {
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
|
||||
.addImm(8)
|
||||
.addReg(SPReg);
|
||||
for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
|
||||
.addReg(TempReg, getKillRegState(i == e-1));
|
||||
}
|
||||
|
||||
if (MustSaveLR)
|
||||
BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
|
||||
.addImm(LROffset)
|
||||
.addReg(SPReg);
|
||||
|
||||
assert((isPPC64 || MustSaveCRs.empty()) &&
|
||||
"Epilogue CR restoring supported only in 64-bit mode");
|
||||
|
||||
if (!MustSaveCRs.empty()) // will only occur for PPC64
|
||||
if (MustSaveCR &&
|
||||
!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
|
||||
.addImm(8)
|
||||
.addReg(SPReg);
|
||||
@ -1160,7 +1282,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
|
||||
.addImm(BPOffset)
|
||||
.addReg(SPReg);
|
||||
|
||||
if (!MustSaveCRs.empty()) // will only occur for PPC64
|
||||
if (MustSaveCR &&
|
||||
!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
|
||||
for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
|
||||
.addReg(TempReg, getKillRegState(i == e-1));
|
||||
|
@ -30,28 +30,41 @@ class PPCFrameLowering: public TargetFrameLowering {
|
||||
const unsigned BasePointerSaveOffset;
|
||||
|
||||
/**
|
||||
* \brief Find a register that can be used in function prologue and epilogue
|
||||
* \brief Find register[s] that can be used in function prologue and epilogue
|
||||
*
|
||||
* Find a register that can be use as the scratch register in function
|
||||
* Find register[s] that can be use as scratch register[s] in function
|
||||
* prologue and epilogue to save various registers (Link Register, Base
|
||||
* Pointer, etc.). Prefer R0, if it is available. If it is not available,
|
||||
* then choose a different register.
|
||||
* Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever
|
||||
* register[s] are available.
|
||||
*
|
||||
* This method will return true if an available register was found (including
|
||||
* R0). If no available registers are found, the method returns false and sets
|
||||
* ScratchRegister to R0, as per the recommendation in the ABI.
|
||||
* This method will return true if it is able to find enough unique scratch
|
||||
* registers (1 or 2 depending on the requirement). If it is unable to find
|
||||
* enough available registers in the block, it will return false and set
|
||||
* any passed output parameter that corresponds to a required unique register
|
||||
* to PPC::NoRegister.
|
||||
*
|
||||
* \param[in] MBB The machine basic block to find an available register for
|
||||
* \param[in] UseAtEnd Specify whether the scratch register will be used at
|
||||
* the end of the basic block (i.e., will the scratch
|
||||
* register kill a register defined in the basic block)
|
||||
* \param[out] ScratchRegister The scratch register to use
|
||||
* \return true if a scratch register was found. false of a scratch register
|
||||
* was not found and R0 is being used as the default.
|
||||
* \param[in] TwoUniqueRegsRequired Specify whether this basic block will
|
||||
* require two unique scratch registers.
|
||||
* \param[out] SR1 The scratch register to use
|
||||
* \param[out] SR2 The second scratch register. If this pointer is not null
|
||||
* the function will attempt to set it to an available
|
||||
* register regardless of whether there is a hard requirement
|
||||
* for two unique scratch registers.
|
||||
* \return true if the required number of registers was found.
|
||||
* false if the required number of scratch register weren't available.
|
||||
* If either output parameter refers to a required scratch register
|
||||
* that isn't available, it will be set to an invalid value.
|
||||
*/
|
||||
bool findScratchRegister(MachineBasicBlock *MBB,
|
||||
bool UseAtEnd,
|
||||
unsigned *ScratchRegister) const;
|
||||
bool TwoUniqueRegsRequired = false,
|
||||
unsigned *SR1 = nullptr,
|
||||
unsigned *SR2 = nullptr) const;
|
||||
bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const;
|
||||
|
||||
public:
|
||||
PPCFrameLowering(const PPCSubtarget &STI);
|
||||
|
@ -22227,6 +22227,35 @@ X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
|
||||
return BB;
|
||||
}
|
||||
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitLoweredTLSAddr(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
// So, here we replace TLSADDR with the sequence:
|
||||
// adjust_stackdown -> TLSADDR -> adjust_stackup.
|
||||
// We need this because TLSADDR is lowered into calls
|
||||
// inside MC, therefore without the two markers shrink-wrapping
|
||||
// may push the prologue/epilogue pass them.
|
||||
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
MachineFunction &MF = *BB->getParent();
|
||||
|
||||
// Emit CALLSEQ_START right before the instruction.
|
||||
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
||||
MachineInstrBuilder CallseqStart =
|
||||
BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0);
|
||||
BB->insert(MachineBasicBlock::iterator(MI), CallseqStart);
|
||||
|
||||
// Emit CALLSEQ_END right after the instruction.
|
||||
// We don't call erase from parent because we want to keep the
|
||||
// original instruction around.
|
||||
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
|
||||
MachineInstrBuilder CallseqEnd =
|
||||
BuildMI(MF, DL, TII.get(AdjStackUp)).addImm(0).addImm(0);
|
||||
BB->insertAfter(MachineBasicBlock::iterator(MI), CallseqEnd);
|
||||
|
||||
return BB;
|
||||
}
|
||||
|
||||
MachineBasicBlock *
|
||||
X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
@ -22607,6 +22636,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
case X86::TCRETURNri64:
|
||||
case X86::TCRETURNmi64:
|
||||
return BB;
|
||||
case X86::TLS_addr32:
|
||||
case X86::TLS_addr64:
|
||||
case X86::TLS_base_addr32:
|
||||
case X86::TLS_base_addr64:
|
||||
return EmitLoweredTLSAddr(MI, BB);
|
||||
case X86::WIN_ALLOCA:
|
||||
return EmitLoweredWinAlloca(MI, BB);
|
||||
case X86::CATCHRET:
|
||||
|
@ -1129,6 +1129,9 @@ namespace llvm {
|
||||
MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
|
||||
MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
|
||||
MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
|
||||
|
@ -436,7 +436,7 @@ let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
|
||||
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
||||
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
||||
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
||||
Uses = [ESP] in {
|
||||
usesCustomInserter = 1, Uses = [ESP] in {
|
||||
def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
|
||||
"# TLS_addr32",
|
||||
[(X86tlsaddr tls32addr:$sym)]>,
|
||||
@ -456,7 +456,7 @@ let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
|
||||
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
||||
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
||||
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
||||
Uses = [RSP] in {
|
||||
usesCustomInserter = 1, Uses = [RSP] in {
|
||||
def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
|
||||
"# TLS_addr64",
|
||||
[(X86tlsaddr tls64addr:$sym)]>,
|
||||
|
@ -3475,6 +3475,7 @@ class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
|
||||
|
||||
Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
|
||||
QualType Ty) const {
|
||||
const unsigned OverflowLimit = 8;
|
||||
if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
|
||||
// TODO: Implement this. For now ignore.
|
||||
(void)CTy;
|
||||
@ -3517,7 +3518,7 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
|
||||
}
|
||||
|
||||
llvm::Value *CC =
|
||||
Builder.CreateICmpULT(NumRegs, Builder.getInt8(8), "cond");
|
||||
Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
|
||||
|
||||
llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
|
||||
llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
|
||||
@ -3569,6 +3570,8 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
|
||||
{
|
||||
CGF.EmitBlock(UsingOverflow);
|
||||
|
||||
Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
|
||||
|
||||
// Everything in the overflow area is rounded up to a size of at least 4.
|
||||
CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
|
||||
|
||||
|
@ -1365,10 +1365,13 @@ Sema::CreateGenericSelectionExpr(SourceLocation KeyLoc,
|
||||
|
||||
// Decay and strip qualifiers for the controlling expression type, and handle
|
||||
// placeholder type replacement. See committee discussion from WG14 DR423.
|
||||
{
|
||||
EnterExpressionEvaluationContext Unevaluated(*this, Sema::Unevaluated);
|
||||
ExprResult R = DefaultFunctionArrayLvalueConversion(ControllingExpr);
|
||||
if (R.isInvalid())
|
||||
return ExprError();
|
||||
ControllingExpr = R.get();
|
||||
}
|
||||
|
||||
// The controlling expression is an unevaluated operand, so side effects are
|
||||
// likely unintended.
|
||||
|
@ -7,4 +7,4 @@
|
||||
|
||||
#define CLANG_VENDOR "FreeBSD "
|
||||
|
||||
#define SVN_REVISION "261369"
|
||||
#define SVN_REVISION "261684"
|
||||
|
Loading…
Reference in New Issue
Block a user