sfxge(4): move port config to ef10 NIC board config
Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18184
This commit is contained in:
Andrew Rybchenko
parent
daf72d82e0
commit
09eac95749
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=341108
@ -1201,11 +1201,6 @@ ef10_get_privilege_mask(
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__in efx_nic_t *enp,
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__out uint32_t *maskp);
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extern __checkReturn efx_rc_t
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ef10_external_port_mapping(
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__in efx_nic_t *enp,
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__in uint32_t port,
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__out uint8_t *external_portp);
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#if EFSYS_OPT_RX_PACKED_STREAM
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@ -1494,7 +1494,7 @@ static struct ef10_external_port_map_s {
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},
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};
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__checkReturn efx_rc_t
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static __checkReturn efx_rc_t
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ef10_external_port_mapping(
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__in efx_nic_t *enp,
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__in uint32_t port,
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@ -1573,14 +1573,33 @@ ef10_nic_board_cfg(
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__in efx_nic_t *enp)
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{
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const efx_nic_ops_t *enop = enp->en_enop;
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efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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uint32_t port;
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efx_rc_t rc;
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/* Get the (zero-based) MCDI port number */
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if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
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goto fail1;
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/* EFX MCDI interface uses one-based port numbers */
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emip->emi_port = port + 1;
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if ((rc = ef10_external_port_mapping(enp, port,
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&encp->enc_external_port)) != 0)
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goto fail2;
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/* Get remaining controller-specific board config */
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if ((rc = enop->eno_board_cfg(enp)) != 0)
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if (rc != EACCES)
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goto fail1;
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goto fail3;
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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@ -103,13 +103,11 @@ hunt_nic_get_required_pcie_bandwidth(
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hunt_board_cfg(
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__in efx_nic_t *enp)
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{
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efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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uint8_t mac_addr[6] = { 0 };
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uint32_t board_type = 0;
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ef10_link_state_t els;
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efx_port_t *epp = &(enp->en_port);
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uint32_t port;
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uint32_t pf;
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uint32_t vf;
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uint32_t mask;
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@ -129,20 +127,6 @@ hunt_board_cfg(
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EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
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encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
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if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
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goto fail1;
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/*
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* NOTE: The MCDI protocol numbers ports from zero.
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* The common code MCDI interface numbers ports from one.
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*/
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emip->emi_port = port + 1;
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if ((rc = ef10_external_port_mapping(enp, port,
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&encp->enc_external_port)) != 0)
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goto fail2;
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/*
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* Get PCIe function number from firmware (used for
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* per-function privilege and dynamic config info).
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@ -150,7 +134,7 @@ hunt_board_cfg(
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* - PCIe VF: pf = parent PF, vf = VF number.
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*/
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if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
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goto fail3;
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goto fail1;
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encp->enc_pf = pf;
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encp->enc_vf = vf;
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@ -171,7 +155,7 @@ hunt_board_cfg(
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rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
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}
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if (rc != 0)
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goto fail4;
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goto fail2;
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EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
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@ -182,7 +166,7 @@ hunt_board_cfg(
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if (rc == EACCES)
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board_type = 0;
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else
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goto fail5;
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goto fail3;
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}
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encp->enc_board_type = board_type;
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@ -190,11 +174,11 @@ hunt_board_cfg(
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/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
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if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
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goto fail6;
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goto fail4;
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/* Obtain the default PHY advertised capabilities */
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if ((rc = ef10_phy_get_link(enp, &els)) != 0)
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goto fail7;
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goto fail5;
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epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
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epp->ep_adv_cap_mask = els.els_adv_cap_mask;
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@ -225,7 +209,7 @@ hunt_board_cfg(
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else if ((rc == ENOTSUP) || (rc == ENOENT))
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encp->enc_bug35388_workaround = B_FALSE;
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else
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goto fail8;
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goto fail6;
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/*
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* If the bug41750 workaround is enabled, then do not test interrupts,
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@ -244,7 +228,7 @@ hunt_board_cfg(
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} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
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encp->enc_bug41750_workaround = B_FALSE;
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} else {
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goto fail9;
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goto fail7;
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}
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if (EFX_PCI_FUNCTION_IS_VF(encp)) {
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/* Interrupt testing does not work for VFs. See bug50084. */
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@ -282,12 +266,12 @@ hunt_board_cfg(
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} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
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encp->enc_bug26807_workaround = B_FALSE;
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} else {
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goto fail10;
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goto fail8;
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}
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/* Get clock frequencies (in MHz). */
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if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
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goto fail11;
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goto fail9;
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/*
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* The Huntington timer quantum is 1536 sysclk cycles, documented for
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@ -306,7 +290,7 @@ hunt_board_cfg(
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/* Check capabilities of running datapath firmware */
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if ((rc = ef10_get_datapath_caps(enp)) != 0)
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goto fail12;
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goto fail10;
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/* Alignment for receive packet DMA buffers */
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encp->enc_rx_buf_align_start = 1;
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@ -356,13 +340,13 @@ hunt_board_cfg(
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* can result in time-of-check/time-of-use bugs.
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*/
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if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
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goto fail13;
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goto fail11;
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encp->enc_privilege_mask = mask;
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/* Get interrupt vector limits */
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if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
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if (EFX_PCI_FUNCTION_IS_PF(encp))
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goto fail14;
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goto fail12;
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/* Ignore error (cannot query vector limits from a VF). */
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base = 0;
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@ -378,7 +362,7 @@ hunt_board_cfg(
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encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
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if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
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goto fail15;
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goto fail13;
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encp->enc_required_pcie_bandwidth_mbps = bandwidth;
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/* All Huntington devices have a PCIe Gen3, 8 lane connector */
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@ -386,10 +370,6 @@ hunt_board_cfg(
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return (0);
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fail15:
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EFSYS_PROBE(fail15);
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fail14:
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EFSYS_PROBE(fail14);
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fail13:
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EFSYS_PROBE(fail13);
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fail12:
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@ -77,13 +77,11 @@ medford2_nic_get_required_pcie_bandwidth(
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medford2_board_cfg(
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__in efx_nic_t *enp)
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{
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efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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uint8_t mac_addr[6] = { 0 };
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uint32_t board_type = 0;
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ef10_link_state_t els;
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efx_port_t *epp = &(enp->en_port);
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uint32_t port;
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uint32_t pf;
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uint32_t vf;
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uint32_t mask;
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@ -107,19 +105,6 @@ medford2_board_cfg(
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encp->enc_vi_window_shift = vi_window_shift;
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if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
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goto fail1;
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/*
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* NOTE: The MCDI protocol numbers ports from zero.
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* The common code MCDI interface numbers ports from one.
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*/
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emip->emi_port = port + 1;
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if ((rc = ef10_external_port_mapping(enp, port,
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&encp->enc_external_port)) != 0)
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goto fail2;
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/*
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* Get PCIe function number from firmware (used for
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* per-function privilege and dynamic config info).
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@ -127,7 +112,7 @@ medford2_board_cfg(
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* - PCIe VF: pf = parent PF, vf = VF number.
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*/
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if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
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goto fail3;
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goto fail2;
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encp->enc_pf = pf;
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encp->enc_vf = vf;
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@ -156,7 +141,7 @@ medford2_board_cfg(
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rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
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}
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if (rc != 0)
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goto fail4;
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goto fail3;
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EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
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@ -167,7 +152,7 @@ medford2_board_cfg(
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if (rc == EACCES)
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board_type = 0;
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else
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goto fail5;
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goto fail4;
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}
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encp->enc_board_type = board_type;
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@ -175,11 +160,11 @@ medford2_board_cfg(
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/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
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if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
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goto fail6;
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goto fail5;
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/* Obtain the default PHY advertised capabilities */
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if ((rc = ef10_phy_get_link(enp, &els)) != 0)
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goto fail7;
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goto fail6;
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epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
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epp->ep_adv_cap_mask = els.els_adv_cap_mask;
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@ -223,11 +208,11 @@ medford2_board_cfg(
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else if ((rc == ENOTSUP) || (rc == ENOENT))
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encp->enc_bug61265_workaround = B_FALSE;
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else
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goto fail8;
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goto fail7;
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/* Get clock frequencies (in MHz). */
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if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
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goto fail9;
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goto fail8;
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/*
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* The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
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@ -239,7 +224,7 @@ medford2_board_cfg(
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/* Check capabilities of running datapath firmware */
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if ((rc = ef10_get_datapath_caps(enp)) != 0)
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goto fail10;
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goto fail9;
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/* Alignment for receive packet DMA buffers */
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encp->enc_rx_buf_align_start = 1;
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@ -247,7 +232,7 @@ medford2_board_cfg(
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/* Get the RX DMA end padding alignment configuration */
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if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
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if (rc != EACCES)
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goto fail11;
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goto fail10;
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/* Assume largest tail padding size supported by hardware */
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end_padding = 256;
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@ -299,13 +284,13 @@ medford2_board_cfg(
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* can result in time-of-check/time-of-use bugs.
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*/
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if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
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goto fail12;
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goto fail11;
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encp->enc_privilege_mask = mask;
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/* Get interrupt vector limits */
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if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
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if (EFX_PCI_FUNCTION_IS_PF(encp))
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goto fail13;
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goto fail12;
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/* Ignore error (cannot query vector limits from a VF). */
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base = 0;
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@ -328,14 +313,12 @@ medford2_board_cfg(
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rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
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if (rc != 0)
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goto fail14;
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goto fail13;
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encp->enc_required_pcie_bandwidth_mbps = bandwidth;
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encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
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return (0);
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fail14:
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EFSYS_PROBE(fail14);
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fail13:
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EFSYS_PROBE(fail13);
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fail12:
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@ -73,13 +73,11 @@ medford_nic_get_required_pcie_bandwidth(
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medford_board_cfg(
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__in efx_nic_t *enp)
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{
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efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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uint8_t mac_addr[6] = { 0 };
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uint32_t board_type = 0;
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ef10_link_state_t els;
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efx_port_t *epp = &(enp->en_port);
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uint32_t port;
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uint32_t pf;
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uint32_t vf;
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uint32_t mask;
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@ -104,20 +102,6 @@ medford_board_cfg(
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EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
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encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
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if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
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goto fail1;
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/*
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* NOTE: The MCDI protocol numbers ports from zero.
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* The common code MCDI interface numbers ports from one.
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*/
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emip->emi_port = port + 1;
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if ((rc = ef10_external_port_mapping(enp, port,
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&encp->enc_external_port)) != 0)
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goto fail2;
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/*
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* Get PCIe function number from firmware (used for
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* per-function privilege and dynamic config info).
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@ -125,7 +109,7 @@ medford_board_cfg(
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* - PCIe VF: pf = parent PF, vf = VF number.
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*/
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if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
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goto fail3;
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goto fail1;
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encp->enc_pf = pf;
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encp->enc_vf = vf;
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@ -154,7 +138,7 @@ medford_board_cfg(
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rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
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}
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if (rc != 0)
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goto fail4;
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goto fail2;
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EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
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@ -165,7 +149,7 @@ medford_board_cfg(
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if (rc == EACCES)
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board_type = 0;
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else
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goto fail5;
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goto fail3;
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}
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encp->enc_board_type = board_type;
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@ -173,11 +157,11 @@ medford_board_cfg(
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/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
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if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
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goto fail6;
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goto fail4;
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/* Obtain the default PHY advertised capabilities */
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if ((rc = ef10_phy_get_link(enp, &els)) != 0)
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goto fail7;
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goto fail5;
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epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
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epp->ep_adv_cap_mask = els.els_adv_cap_mask;
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@ -221,11 +205,11 @@ medford_board_cfg(
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else if ((rc == ENOTSUP) || (rc == ENOENT))
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encp->enc_bug61265_workaround = B_FALSE;
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else
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goto fail8;
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goto fail6;
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/* Get clock frequencies (in MHz). */
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if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
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goto fail9;
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goto fail7;
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/*
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* The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
|
||||
@ -237,7 +221,7 @@ medford_board_cfg(
|
||||
|
||||
/* Check capabilities of running datapath firmware */
|
||||
if ((rc = ef10_get_datapath_caps(enp)) != 0)
|
||||
goto fail10;
|
||||
goto fail8;
|
||||
|
||||
/* Alignment for receive packet DMA buffers */
|
||||
encp->enc_rx_buf_align_start = 1;
|
||||
@ -245,7 +229,7 @@ medford_board_cfg(
|
||||
/* Get the RX DMA end padding alignment configuration */
|
||||
if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
|
||||
if (rc != EACCES)
|
||||
goto fail11;
|
||||
goto fail9;
|
||||
|
||||
/* Assume largest tail padding size supported by hardware */
|
||||
end_padding = 256;
|
||||
@ -297,13 +281,13 @@ medford_board_cfg(
|
||||
* can result in time-of-check/time-of-use bugs.
|
||||
*/
|
||||
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
|
||||
goto fail12;
|
||||
goto fail10;
|
||||
encp->enc_privilege_mask = mask;
|
||||
|
||||
/* Get interrupt vector limits */
|
||||
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
|
||||
if (EFX_PCI_FUNCTION_IS_PF(encp))
|
||||
goto fail13;
|
||||
goto fail11;
|
||||
|
||||
/* Ignore error (cannot query vector limits from a VF). */
|
||||
base = 0;
|
||||
@ -326,16 +310,12 @@ medford_board_cfg(
|
||||
|
||||
rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
|
||||
if (rc != 0)
|
||||
goto fail14;
|
||||
goto fail12;
|
||||
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
|
||||
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
|
||||
|
||||
return (0);
|
||||
|
||||
fail14:
|
||||
EFSYS_PROBE(fail14);
|
||||
fail13:
|
||||
EFSYS_PROBE(fail13);
|
||||
fail12:
|
||||
EFSYS_PROBE(fail12);
|
||||
fail11:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user