From 0a57279ba458ebd60081fdeac66abc1ec16b4092 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Tue, 3 Apr 2018 21:38:11 +0000 Subject: [PATCH] Split get_sar_value function for Marvell ArmadaXP and Armada38X get_sar_value is implemented only for ArmadaXP and Armada38X. Splitting it for two different functions and change registers names result in more generic code. Submitted by: Rafal Kozik Reviewed by: andrew Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14736 --- sys/arm/mv/armada38x/armada38x.c | 18 +++++++++++++++--- sys/arm/mv/armadaxp/armadaxp.c | 15 ++++++++++++++- sys/arm/mv/mv_common.c | 25 ------------------------- sys/arm/mv/mvreg.h | 15 ++++++--------- sys/arm/mv/mvvar.h | 1 - 5 files changed, 35 insertions(+), 39 deletions(-) diff --git a/sys/arm/mv/armada38x/armada38x.c b/sys/arm/mv/armada38x/armada38x.c index a72d31432eb1..7591d2694888 100644 --- a/sys/arm/mv/armada38x/armada38x.c +++ b/sys/arm/mv/armada38x/armada38x.c @@ -43,11 +43,23 @@ int armada38x_open_bootrom_win(void); int armada38x_scu_enable(void); int armada38x_win_set_iosync_barrier(void); int armada38x_mbus_optimization(void); +static uint64_t get_sar_value_armada38x(void); static int hw_clockrate; SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, &hw_clockrate, 0, "CPU instruction clock rate"); +static uint64_t +get_sar_value_armada38x(void) +{ + uint32_t sar_low, sar_high; + + sar_high = 0; + sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, + SAMPLE_AT_RESET_ARMADA38X); + return (((uint64_t)sar_high << 32) | sar_low); +} + uint32_t get_tclk(void) { @@ -57,8 +69,8 @@ get_tclk(void) * On Armada38x TCLK can be configured to 250 MHz or 200 MHz. * Current setting is read from Sample At Reset register. */ - sar = (uint32_t)get_sar_value(); - sar = (sar & TCLK_MASK) >> TCLK_SHIFT; + sar = (uint32_t)get_sar_value_armada38x(); + sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X; if (sar == 0) return (TCLK_250MHZ); else @@ -78,7 +90,7 @@ get_cpu_freq(void) 1866, 0, 0, 2000 }; - sar = (uint32_t)get_sar_value(); + sar = (uint32_t)get_sar_value_armada38x(); sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT; if (sar >= nitems(cpu_frequencies)) return (0); diff --git a/sys/arm/mv/armadaxp/armadaxp.c b/sys/arm/mv/armadaxp/armadaxp.c index afb028079ad4..e1a4618ec811 100644 --- a/sys/arm/mv/armadaxp/armadaxp.c +++ b/sys/arm/mv/armadaxp/armadaxp.c @@ -55,6 +55,7 @@ static uint32_t count_l2clk(void); void armadaxp_l2_init(void); void armadaxp_init_coher_fabric(void); int platform_get_ncpus(void); +static uint64_t get_sar_value_armadaxp(void); #define ARMADAXP_L2_BASE (MV_BASE + 0x8000) #define ARMADAXP_L2_CTRL 0x100 @@ -124,6 +125,18 @@ static uint16_t cpu_clock_table[] = { 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600, 2133, 2200, 2400 }; +static uint64_t +get_sar_value_armadaxp(void) +{ + uint32_t sar_low, sar_high; + + sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, + SAMPLE_AT_RESET_HI); + sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, + SAMPLE_AT_RESET_LO); + return (((uint64_t)sar_high << 32) | sar_low); +} + uint32_t get_tclk(void) { @@ -153,7 +166,7 @@ count_l2clk(void) uint8_t sar_cpu_freq, sar_fab_freq, array_size; /* Get value of the SAR register and process it */ - sar_reg = get_sar_value(); + sar_reg = get_sar_value_armadaxp(); sar_cpu_freq = CPU_FREQ_FIELD(sar_reg); sar_fab_freq = FAB_FREQ_FIELD(sar_reg); diff --git a/sys/arm/mv/mv_common.c b/sys/arm/mv/mv_common.c index 74fa0cfa552b..8d81df4c5e31 100644 --- a/sys/arm/mv/mv_common.c +++ b/sys/arm/mv/mv_common.c @@ -2664,28 +2664,3 @@ fdt_pic_decode_t fdt_pic_table[] = { NULL }; #endif - -uint64_t -get_sar_value(void) -{ - uint32_t sar_low, sar_high; - -#if defined(SOC_MV_ARMADAXP) - sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, - SAMPLE_AT_RESET_HI); - sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, - SAMPLE_AT_RESET_LO); -#elif defined(SOC_MV_ARMADA38X) - sar_high = 0; - sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, - SAMPLE_AT_RESET); -#else - /* - * TODO: Add getting proper values for other SoC configurations - */ - sar_high = 0; - sar_low = 0; -#endif - - return (((uint64_t)sar_high << 32) | sar_low); -} diff --git a/sys/arm/mv/mvreg.h b/sys/arm/mv/mvreg.h index b5cc5a6c9467..68a2b510834f 100644 --- a/sys/arm/mv/mvreg.h +++ b/sys/arm/mv/mvreg.h @@ -327,13 +327,10 @@ #define SAMPLE_AT_RESET 0x10 #elif defined(SOC_MV_KIRKWOOD) #define SAMPLE_AT_RESET 0x30 -#elif defined(SOC_MV_ARMADA38X) -#define SAMPLE_AT_RESET 0x400 -#endif -#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_ARMADAXP) -#define SAMPLE_AT_RESET_LO 0x30 -#define SAMPLE_AT_RESET_HI 0x34 #endif +#define SAMPLE_AT_RESET_ARMADA38X 0x400 +#define SAMPLE_AT_RESET_LO 0x30 +#define SAMPLE_AT_RESET_HI 0x34 /* * Clocks @@ -344,11 +341,11 @@ #elif defined(SOC_MV_DISCOVERY) #define TCLK_MASK 0x00000180 #define TCLK_SHIFT 0x07 -#elif defined(SOC_MV_ARMADA38X) -#define TCLK_MASK 0x00008000 -#define TCLK_SHIFT 15 #endif +#define TCLK_MASK_ARMADA38X 0x00008000 +#define TCLK_SHIFT_ARMADA38X 15 + #define TCLK_100MHZ 100000000 #define TCLK_125MHZ 125000000 #define TCLK_133MHZ 133333333 diff --git a/sys/arm/mv/mvvar.h b/sys/arm/mv/mvvar.h index a26c1cc5537e..9ee9cb628f1c 100644 --- a/sys/arm/mv/mvvar.h +++ b/sys/arm/mv/mvvar.h @@ -89,7 +89,6 @@ void soc_id(uint32_t *dev, uint32_t *rev); void soc_dump_decode_win(void); uint32_t soc_power_ctrl_get(uint32_t mask); void soc_power_ctrl_set(uint32_t mask); -uint64_t get_sar_value(void); int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, vm_paddr_t remap);