Our existing Cyrix cache-disable code was short-cutting the steps for
setting the control register. Make the read and write operations two completely separate steps. While we're at it, pull in the whole set of Cyrix cache control options from NetBSD-current, since a few motherboards do the right thing with the Cyrix chip. There is no option to disable the internal cache completely (yet). Reviewed by: pst Obtained from: NetBSD
This commit is contained in:
Paul Traina
parent
87c66f4cc7
commit
0b4a1769be
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=10826
@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)locore.s 7.3 (Berkeley) 5/13/91
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* $Id: locore.s,v 1.54 1995/08/29 23:45:20 bde Exp $
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* $Id: locore.s,v 1.55 1995/09/15 02:13:18 davidg Exp $
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*/
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/*
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@ -372,14 +372,62 @@ got_common_bi_size:
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movl $0x69727943,_cpu_vendor-KERNBASE # store vendor string
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movw $0x0078,_cpu_vendor-KERNBASE+4
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invd # Start with guaranteed clean cache
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#ifndef CYRIX_CACHE_WORKS
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/* Disable caching of the ISA hole only. */
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invd
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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inb $0x23,%al
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orb $(CCR0_NC1|CCR0_BARB),%al
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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invd
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#else /* CYRIX_CACHE_WORKS */
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/* Set cache parameters */
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invd # Start with guaranteed clean cache
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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andb $~CCR0_NC0,%al
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#ifndef CYRIX_CACHE_REALLY_WORKS
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orb $(CCR0_NC1|CCR0_BARB),%al
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#else
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orb $CCR0_NC1,%al
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#endif
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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/* clear non-cacheable region 1 */
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movb $(NCR1+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 2 */
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movb $(NCR2+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 3 */
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movb $(NCR3+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 4 */
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movb $(NCR4+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* enable caching in CR0 */
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movl %cr0,%eax
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andl $~(CR0_CD|CR0_NW),%eax
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movl %eax,%cr0
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invd
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#endif /* CYRIX_CACHE_WORKS */
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jmp 2f
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1: /* Use the `cpuid' instruction. */
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)locore.s 7.3 (Berkeley) 5/13/91
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* $Id: locore.s,v 1.54 1995/08/29 23:45:20 bde Exp $
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* $Id: locore.s,v 1.55 1995/09/15 02:13:18 davidg Exp $
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*/
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/*
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@ -372,14 +372,62 @@ got_common_bi_size:
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movl $0x69727943,_cpu_vendor-KERNBASE # store vendor string
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movw $0x0078,_cpu_vendor-KERNBASE+4
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invd # Start with guaranteed clean cache
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#ifndef CYRIX_CACHE_WORKS
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/* Disable caching of the ISA hole only. */
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invd
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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inb $0x23,%al
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orb $(CCR0_NC1|CCR0_BARB),%al
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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invd
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#else /* CYRIX_CACHE_WORKS */
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/* Set cache parameters */
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invd # Start with guaranteed clean cache
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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andb $~CCR0_NC0,%al
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#ifndef CYRIX_CACHE_REALLY_WORKS
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orb $(CCR0_NC1|CCR0_BARB),%al
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#else
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orb $CCR0_NC1,%al
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#endif
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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/* clear non-cacheable region 1 */
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movb $(NCR1+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 2 */
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movb $(NCR2+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 3 */
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movb $(NCR3+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 4 */
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movb $(NCR4+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* enable caching in CR0 */
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movl %cr0,%eax
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andl $~(CR0_CD|CR0_NW),%eax
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movl %eax,%cr0
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invd
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#endif /* CYRIX_CACHE_WORKS */
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jmp 2f
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1: /* Use the `cpuid' instruction. */
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)locore.s 7.3 (Berkeley) 5/13/91
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* $Id: locore.s,v 1.54 1995/08/29 23:45:20 bde Exp $
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* $Id: locore.s,v 1.55 1995/09/15 02:13:18 davidg Exp $
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*/
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/*
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@ -372,14 +372,62 @@ got_common_bi_size:
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movl $0x69727943,_cpu_vendor-KERNBASE # store vendor string
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movw $0x0078,_cpu_vendor-KERNBASE+4
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invd # Start with guaranteed clean cache
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#ifndef CYRIX_CACHE_WORKS
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/* Disable caching of the ISA hole only. */
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invd
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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inb $0x23,%al
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orb $(CCR0_NC1|CCR0_BARB),%al
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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invd
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#else /* CYRIX_CACHE_WORKS */
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/* Set cache parameters */
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invd # Start with guaranteed clean cache
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movb $CCR0,%al # Configuration Register index (CCR0)
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outb %al,$0x22
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inb $0x23,%al
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andb $~CCR0_NC0,%al
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#ifndef CYRIX_CACHE_REALLY_WORKS
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orb $(CCR0_NC1|CCR0_BARB),%al
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#else
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orb $CCR0_NC1,%al
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#endif
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movb %al,%ah
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movb $CCR0,%al
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outb %al,$0x22
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movb %ah,%al
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outb %al,$0x23
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/* clear non-cacheable region 1 */
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movb $(NCR1+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 2 */
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movb $(NCR2+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 3 */
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movb $(NCR3+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* clear non-cacheable region 4 */
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movb $(NCR4+2),%al
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outb %al,$0x22
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movb $NCR_SIZE_0K,%al
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outb %al,$0x23
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/* enable caching in CR0 */
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movl %cr0,%eax
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andl $~(CR0_CD|CR0_NW),%eax
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movl %eax,%cr0
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invd
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#endif /* CYRIX_CACHE_WORKS */
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jmp 2f
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1: /* Use the `cpuid' instruction. */
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