The general conesnsus on irc was that pci bios for config registers
and such was just a bad idea and one that users should be forced to enable if they want it. This patch introduces a hw.pci.enable_pcibios tunable for those people. This does not impact the pcibios interrupt routing at all. Approved by: peter, msmith
This commit is contained in:
parent
868d3ce781
commit
0b9427de88
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=82035
@ -207,6 +207,7 @@ struct bios_args {
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/*
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* PCI BIOS functions
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*/
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#define PCIBIOS_BIOS_PRESENT 0xb101
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#define PCIBIOS_READ_CONFIG_BYTE 0xb108
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#define PCIBIOS_READ_CONFIG_WORD 0xb109
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#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
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@ -55,6 +55,9 @@
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int enable_pcibios = 0;
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TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios);
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static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
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static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
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@ -449,14 +452,34 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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static u_int16_t
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pcibios_get_version(void)
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{
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struct bios_regs args;
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args.eax = PCIBIOS_BIOS_PRESENT;
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if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)))
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return (0x0000);
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if (args.edx != 0x20494350)
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return (0x0000);
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return (args.ebx & 0xffff);
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}
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/*
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* Determine whether there is a PCI BIOS present
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*/
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static int
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pcibios_cfgopen(void)
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{
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/* check for a found entrypoint */
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return(PCIbios.entry != 0);
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u_int16_t v = 0;
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if (PCIbios.entry != 0 && enable_pcibios) {
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v = pcibios_get_version();
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if (v > 0)
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printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
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v & 0xff);
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}
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return (v > 0);
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}
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/*
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@ -207,6 +207,7 @@ struct bios_args {
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/*
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* PCI BIOS functions
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*/
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#define PCIBIOS_BIOS_PRESENT 0xb101
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#define PCIBIOS_READ_CONFIG_BYTE 0xb108
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#define PCIBIOS_READ_CONFIG_WORD 0xb109
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#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
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@ -55,6 +55,9 @@
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int enable_pcibios = 0;
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TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios);
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static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
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static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
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@ -449,14 +452,34 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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static u_int16_t
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pcibios_get_version(void)
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{
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struct bios_regs args;
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args.eax = PCIBIOS_BIOS_PRESENT;
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if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)))
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return (0x0000);
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if (args.edx != 0x20494350)
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return (0x0000);
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return (args.ebx & 0xffff);
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}
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/*
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* Determine whether there is a PCI BIOS present
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*/
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static int
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pcibios_cfgopen(void)
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{
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/* check for a found entrypoint */
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return(PCIbios.entry != 0);
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u_int16_t v = 0;
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if (PCIbios.entry != 0 && enable_pcibios) {
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v = pcibios_get_version();
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if (v > 0)
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printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
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v & 0xff);
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}
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return (v > 0);
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}
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/*
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@ -55,6 +55,9 @@
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int enable_pcibios = 0;
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TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios);
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static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
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static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
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@ -449,14 +452,34 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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static u_int16_t
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pcibios_get_version(void)
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{
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struct bios_regs args;
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args.eax = PCIBIOS_BIOS_PRESENT;
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if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)))
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return (0x0000);
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if (args.edx != 0x20494350)
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return (0x0000);
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return (args.ebx & 0xffff);
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}
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/*
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* Determine whether there is a PCI BIOS present
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*/
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static int
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pcibios_cfgopen(void)
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{
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/* check for a found entrypoint */
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return(PCIbios.entry != 0);
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u_int16_t v = 0;
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if (PCIbios.entry != 0 && enable_pcibios) {
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v = pcibios_get_version();
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if (v > 0)
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printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
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v & 0xff);
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}
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return (v > 0);
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}
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/*
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