Change the default FPU control word so that exceptions for new
processes are now masked until set by fpsetmask(3). Submitted by: bde Approved by: jkh, bde
This commit is contained in:
Martin Cracauer
parent
4b25ed423f
commit
0c14a6606b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=57890
@ -87,54 +87,24 @@ struct save87 {
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u_char sv_pad[64]; /* padding; used by emulators */
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};
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/* Intel prefers long real (53 bit) precision */
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#define __iBCS_NPXCW__ 0x262
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/* wfj prefers temporary real (64 bit) precision */
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#define __386BSD_NPXCW__ 0x362
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/*
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* bde prefers 53 bit precision and all exceptions masked.
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*
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* The standard control word from finit is 0x37F, giving:
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* The hardware default control word for i387's and later coprocessors is
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* 0x37F, giving:
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*
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* Now I want:
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* We modify the affine mode bit and precision bits in this to give:
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*
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* affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
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* 53-bit precision (2 in bitfield 3<<8)
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* overflow exception unmasked (0 in bitfield 1<<3)
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* zero divide exception unmasked (0 in bitfield 1<<2)
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* invalid-operand exception unmasked (0 in bitfield 1<<0).
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*
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* 64-bit precision often gives bad results with high level languages
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* because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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*
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* The "Intel" and wfj control words have:
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*
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* underflow exception unmasked (0 in bitfield 1<<4)
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*
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* but that causes an unexpected exception in the test program 'paranoia'
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* and makes denormals useless (DBL_MIN / 2 underflows). It doesn't make
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* a lot of sense to trap underflow without trapping denormals.
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*
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* Later I will want the IEEE default of all exceptions masked. See the
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* 0.0 math manpage for why this is better. The 0.1 math manpage is empty.
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*/
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#define __BDE_NPXCW__ 0x1272
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#define __BETTER_BDE_NPXCW__ 0x127f
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#ifdef __BROKEN_NPXCW__
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#ifdef __FreeBSD__
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#define __INITIAL_NPXCW__ __386BSD_NPXCW__
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#else
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#define __INITIAL_NPXCW__ __iBCS_NPXCW__
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#endif
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#else
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#define __INITIAL_NPXCW__ __BDE_NPXCW__
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#endif
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#define __INITIAL_NPXCW__ 0x127F
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#ifdef _KERNEL
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#ifndef npxproc
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@ -87,54 +87,24 @@ struct save87 {
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u_char sv_pad[64]; /* padding; used by emulators */
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};
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/* Intel prefers long real (53 bit) precision */
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#define __iBCS_NPXCW__ 0x262
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/* wfj prefers temporary real (64 bit) precision */
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#define __386BSD_NPXCW__ 0x362
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/*
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* bde prefers 53 bit precision and all exceptions masked.
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*
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* The standard control word from finit is 0x37F, giving:
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* The hardware default control word for i387's and later coprocessors is
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* 0x37F, giving:
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*
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* Now I want:
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* We modify the affine mode bit and precision bits in this to give:
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*
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* affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
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* 53-bit precision (2 in bitfield 3<<8)
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* overflow exception unmasked (0 in bitfield 1<<3)
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* zero divide exception unmasked (0 in bitfield 1<<2)
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* invalid-operand exception unmasked (0 in bitfield 1<<0).
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*
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* 64-bit precision often gives bad results with high level languages
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* because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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*
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* The "Intel" and wfj control words have:
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*
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* underflow exception unmasked (0 in bitfield 1<<4)
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*
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* but that causes an unexpected exception in the test program 'paranoia'
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* and makes denormals useless (DBL_MIN / 2 underflows). It doesn't make
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* a lot of sense to trap underflow without trapping denormals.
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*
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* Later I will want the IEEE default of all exceptions masked. See the
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* 0.0 math manpage for why this is better. The 0.1 math manpage is empty.
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*/
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#define __BDE_NPXCW__ 0x1272
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#define __BETTER_BDE_NPXCW__ 0x127f
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#ifdef __BROKEN_NPXCW__
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#ifdef __FreeBSD__
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#define __INITIAL_NPXCW__ __386BSD_NPXCW__
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#else
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#define __INITIAL_NPXCW__ __iBCS_NPXCW__
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#endif
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#else
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#define __INITIAL_NPXCW__ __BDE_NPXCW__
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#endif
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#define __INITIAL_NPXCW__ 0x127F
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#ifdef _KERNEL
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#ifndef npxproc
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@ -87,54 +87,24 @@ struct save87 {
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u_char sv_pad[64]; /* padding; used by emulators */
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};
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/* Intel prefers long real (53 bit) precision */
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#define __iBCS_NPXCW__ 0x262
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/* wfj prefers temporary real (64 bit) precision */
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#define __386BSD_NPXCW__ 0x362
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/*
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* bde prefers 53 bit precision and all exceptions masked.
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*
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* The standard control word from finit is 0x37F, giving:
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* The hardware default control word for i387's and later coprocessors is
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* 0x37F, giving:
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*
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* Now I want:
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* We modify the affine mode bit and precision bits in this to give:
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*
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* affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
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* 53-bit precision (2 in bitfield 3<<8)
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* overflow exception unmasked (0 in bitfield 1<<3)
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* zero divide exception unmasked (0 in bitfield 1<<2)
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* invalid-operand exception unmasked (0 in bitfield 1<<0).
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*
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* 64-bit precision often gives bad results with high level languages
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* because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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*
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* The "Intel" and wfj control words have:
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*
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* underflow exception unmasked (0 in bitfield 1<<4)
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*
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* but that causes an unexpected exception in the test program 'paranoia'
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* and makes denormals useless (DBL_MIN / 2 underflows). It doesn't make
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* a lot of sense to trap underflow without trapping denormals.
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*
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* Later I will want the IEEE default of all exceptions masked. See the
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* 0.0 math manpage for why this is better. The 0.1 math manpage is empty.
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*/
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#define __BDE_NPXCW__ 0x1272
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#define __BETTER_BDE_NPXCW__ 0x127f
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#ifdef __BROKEN_NPXCW__
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#ifdef __FreeBSD__
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#define __INITIAL_NPXCW__ __386BSD_NPXCW__
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#else
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#define __INITIAL_NPXCW__ __iBCS_NPXCW__
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#endif
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#else
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#define __INITIAL_NPXCW__ __BDE_NPXCW__
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#endif
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#define __INITIAL_NPXCW__ 0x127F
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#ifdef _KERNEL
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#ifndef npxproc
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