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Since we are quite unlikely to ever face another platform which

Browse Source 
uses the i8237 without trying to emulate the PC architecture move
the register definitions for the i8237 chip into the central include
file for the chip, except for the PC98 case which is magic.

Add new isa_dmatc() function which tells us as cheaply as possible
if the terminal count has been reached for a given channel.
This commit is contained in:
Poul-Henning Kamp 2005-02-06 13:46:39 +00:00
parent 32b8035467
commit 0c3c54da63
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=141391
7 changed files with 89 additions and 76 deletions
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31
sys/alpha/isa/isa_dma.c
View File

@ -60,24 +60,6 @@ __FBSDID("$FreeBSD$");
#include <dev/ic/i8237.h>
#include <machine/bus.h>
/*
** Register definitions for DMA controller 1 (channels 0..3):
*/
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
/*
** Register definitions for DMA controller 2 (channels 4..7):
*/
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
static bus_dma_tag_t dma_tag[8];
static bus_dmamap_t dma_map[8];
static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */
@ -486,6 +468,19 @@ isa_dmastatus(int chan)
return(cnt);
}
/*
* Reached terminal count yet ?
*/
int
isa_dmatc(int chan)
{
if (chan < 4)
return(inb(DMA1_STATUS) & (1 << chan));
else
return(inb(DMA2_STATUS) & (1 << (chan & 3)));
}
/*
* Stop a DMA transfer currently in progress.
*/

29
sys/amd64/isa/isa_dma.c
View File

@ -61,22 +61,6 @@ __FBSDID("$FreeBSD$");
#include <dev/ic/i8237.h>
#include <isa/isavar.h>
/*
** Register definitions for DMA controller 1 (channels 0..3):
*/
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
/*
** Register definitions for DMA controller 2 (channels 4..7):
*/
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
#define ISARAM_END 0x1000000
static int isa_dmarangecheck(caddr_t va, u_int length, int chan);
@ -488,6 +472,19 @@ isa_dmastatus(int chan)
return(cnt);
}
/*
* Reached terminal count yet ?
*/
int
isa_dmatc(int chan)
{
if (chan < 4)
return(inb(DMA1_STATUS) & (1 << chan));
else
return(inb(DMA2_STATUS) & (1 << (chan & 3)));
}
/*
* Stop a DMA transfer currently in progress.
*/

22
sys/dev/ic/i8237.h
View File

@ -10,3 +10,25 @@
#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */
#define DMA37MD_READ 0x08 /* write the device, read memory operation */
#ifndef PC98
/*
** Register definitions for DMA controller 1 (channels 0..3):
*/
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
#define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
/*
** Register definitions for DMA controller 2 (channels 4..7):
*/
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
#endif

29
sys/i386/isa/isa_dma.c
View File

@ -61,22 +61,6 @@ __FBSDID("$FreeBSD$");
#include <dev/ic/i8237.h>
#include <isa/isavar.h>
/*
** Register definitions for DMA controller 1 (channels 0..3):
*/
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
/*
** Register definitions for DMA controller 2 (channels 4..7):
*/
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
static int isa_dmarangecheck(caddr_t va, u_int length, int chan);
static caddr_t dma_bouncebuf[8];
@ -487,6 +471,19 @@ isa_dmastatus(int chan)
return(cnt);
}
/*
* Reached terminal count yet ?
*/
int
isa_dmatc(int chan)
{
if (chan < 4)
return(inb(DMA1_STATUS) & (1 << chan));
else
return(inb(DMA2_STATUS) & (1 << (chan & 3)));
}
/*
* Stop a DMA transfer currently in progress.
*/

31
sys/ia64/isa/isa_dma.c
View File

@ -58,24 +58,6 @@
#include <dev/ic/i8237.h>
#include <machine/bus.h>
/*
** Register definitions for DMA controller 1 (channels 0..3):
*/
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
/*
** Register definitions for DMA controller 2 (channels 4..7):
*/
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
static bus_dma_tag_t dma_tag[8];
static bus_dmamap_t dma_map[8];
static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */
@ -489,6 +471,19 @@ isa_dmastatus(int chan)
return(cnt);
}
/*
* Reached terminal count yet ?
*/
int
isa_dmatc(int chan)
{
if (chan < 4)
return(inb(DMA1_STATUS) & (1 << chan));
else
return(inb(DMA2_STATUS) & (1 << (chan & 3)));
}
/*
* Stop a DMA transfer currently in progress.
*/

17
sys/isa/isavar.h
View File

@ -159,14 +159,15 @@ extern devclass_t isab_devclass;
extern intrmask_t isa_irq_pending(void);
extern void isa_probe_children(device_t dev);
extern void isa_dmacascade(int chan);
extern void isa_dmadone(int flags, caddr_t addr, int nbytes, int chan);
extern int isa_dma_init(int chan, u_int bouncebufsize, int flag);
extern void isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan);
extern int isa_dma_acquire(int chan);
extern void isa_dma_release(int chan);
extern int isa_dmastatus(int chan);
extern int isa_dmastop(int chan);
void isa_dmacascade(int chan);
void isa_dmadone(int flags, caddr_t addr, int nbytes, int chan);
int isa_dma_init(int chan, u_int bouncebufsize, int flag);
void isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan);
int isa_dma_acquire(int chan);
void isa_dma_release(int chan);
int isa_dmastatus(int chan);
int isa_dmastop(int chan);
int isa_dmatc(int chan);
#define isa_dmainit(chan, size) do { \
if (isa_dma_init(chan, size, M_NOWAIT)) \

6
sys/sparc64/isa/isa_dma.c
View File

@ -83,6 +83,12 @@ isa_dmastatus(int chan)
return (0);
}
int
isa_dmatc(int chan)
{
return (0);
}
int
isa_dmastop(int chan)
{