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Sponsored by:	The FreeBSD Foundation
This commit is contained in:
Glen Barber 2016-01-13 04:11:04 +00:00
commit 0ca935a8f0
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/release-pkg/; revision=293803
40 changed files with 1763 additions and 560 deletions
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5
UPDATING
View File

@ -31,6 +31,11 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW:
disable the most expensive debugging functionality run
"ln -s 'abort:false,junk:false' /etc/malloc.conf".)
20160113:
With the addition of ypldap(8), a new _ypldap user is now required
during installworld. "mergemaster -p" can be used to add the user
prior to installworld, as documented in the handbook.
20151216:
The tftp loader (pxeboot) now uses the option root-path directive. As a
consequence it no longer looks for a pxeboot.4th file on the tftp

1
etc/master.passwd
View File

@ -22,5 +22,6 @@ uucp:*:66:66::0:0:UUCP pseudo-user:/var/spool/uucppublic:/usr/local/libexec/uucp
pop:*:68:6::0:0:Post Office Owner:/nonexistent:/usr/sbin/nologin
auditdistd:*:78:77::0:0:Auditdistd unprivileged user:/var/empty:/usr/sbin/nologin
www:*:80:80::0:0:World Wide Web Owner:/nonexistent:/usr/sbin/nologin
_ypldap:*:93:93::0:0:YP Ldap unprivileged user:/var/empty:/usr/sbin/nologin
hast:*:845:845::0:0:HAST unprivileged user:/var/empty:/usr/sbin/nologin
nobody:*:65534:65534::0:0:Unprivileged user:/nonexistent:/usr/sbin/nologin

5
lib/libc/sys/futimens.c
View File

@ -42,8 +42,11 @@ futimens(int fd, const struct timespec times[2])
{
struct timeval now, tv[2], *tvp;
struct stat sb;
int osreldate;
if (__getosreldate() >= 1100056)
osreldate = __getosreldate();
if (osreldate >= 1100056 ||
(osreldate >= 1002506 && osreldate < 1100000))
return (__sys_futimens(fd, times));
if (times == NULL || (times[0].tv_nsec == UTIME_NOW &&

4
lib/libc/sys/utimensat.2
View File

@ -31,7 +31,7 @@
.\" @(#)utimes.2 8.1 (Berkeley) 6/4/93
.\" $FreeBSD$
.\"
.Dd January 23, 2015
.Dd January 12, 2016
.Dt UTIMENSAT 2
.Os
.Sh NAME
@ -289,4 +289,4 @@ The
and
.Fn utimensat
system calls appeared in
.Fx 11.0 .
.Fx 10.3 .

5
lib/libc/sys/utimensat.c
View File

@ -42,8 +42,11 @@ utimensat(int fd, const char *path, const struct timespec times[2], int flag)
{
struct timeval now, tv[2], *tvp;
struct stat sb;
int osreldate;
if (__getosreldate() >= 1100056)
osreldate = __getosreldate();
if (osreldate >= 1100056 ||
(osreldate >= 1002506 && osreldate < 1100000))
return (__sys_utimensat(fd, path, times, flag));
if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0) {

40
share/examples/ypldap/ypldap.conf Normal file
View File

@ -0,0 +1,40 @@
$FreeBSD$
domain "freebsd.org"
interval 60
provide map "passwd.byname"
provide map "passwd.byuid"
provide map "group.byname"
provide map "group.bygid"
provide map "netid.byname"
directory "127.0.0.1" {
# directory options
binddn "cn=ldap,dc=freebsd,dc=org"
bindcred "secret"
basedn "dc=freebsd.,dc=org"
# starting point for groups directory search, default to basedn
groupdn "ou=Groups,dc=freebsd,dc=org"
# passwd maps configuration (RFC 2307 posixAccount object class)
passwd filter "(objectClass=posixAccount)"
attribute name maps to "uid"
fixed attribute passwd "*"
attribute uid maps to "uidNumber"
attribute gid maps to "gidNumber"
attribute gecos maps to "cn"
attribute home maps to "homeDirectory"
attribute shell maps to "loginShell"
fixed attribute change "0"
fixed attribute expire "0"
fixed attribute class ""
# group maps configuration (RFC 2307 posixGroup object class)
group filter "(objectClass=posixGroup)"
attribute groupname maps to "cn"
fixed attribute grouppasswd "*"
attribute groupgid maps to "gidNumber"
# memberUid returns multiple group members
list groupmembers maps to "memberUid"
}

53
share/man/man4/uart.4
View File

@ -25,7 +25,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd August 10, 2015
.Dd December 9, 2015
.Dt UART 4
.Os
.Sh NAME
@ -160,7 +160,9 @@ The API, accessed via
is available on the tty device.
To use the PPS capture feature with
.Xr ntpd 8 ,
symlink the tty device to
symlink the tty callout device
.Va /dev/cuau?
to
.Va /dev/pps0.
.Pp
The
@ -175,15 +177,54 @@ it can be set in
.Xr loader.conf 5
or
.Xr sysctl.conf 5 .
.Pp
The following capture modes are available:
.Bl -tag -compact -offset "mmmm" -width "mmmm"
.It 0
.It 0x00
Capture disabled.
.It 1
.It 0x01
Capture pulses on the CTS line.
.It 2
Capture pulses on the DCD line (default).
.It 0x02
Capture pulses on the DCD line.
.El
.Pp
The following values may be ORed with the capture mode to configure
capture processing options:
.Bl -tag -compact -offset "mmmm" -width "mmmm"
.It 0x10
Invert the pulse (RS-232 logic low = ASSERT, high = CLEAR).
.It 0x20
Attempt to capture narrow pulses.
.El
.Pp
Add the narrow pulse option when the incoming PPS pulse width is small
enough to prevent reliable capture in normal mode.
In narrow mode the driver uses the hardware's ability to latch a line
state change; not all hardware has this capability.
The hardware latch provides a reliable indication that a pulse occurred,
but prevents distinguishing between the CLEAR and ASSERT edges of the pulse.
For each detected pulse, the driver synthesizes both an ASSERT and a CLEAR
event, using the same timestamp for each.
To prevent spurious events when the hardware is intermittently able to
see both edges of a pulse, the driver will not generate a new pair of
events within a half second of the prior pair.
Both normal and narrow pulse modes work with
.Xr ntpd 8 .
.Pp
Add the invert option when the connection to the uart device uses TTL
level signals, or when the PPS source emits inverted pulses.
RFC 2783 defines an ASSERT event as a higher-voltage line level, and a CLEAR
event as a lower-voltage line level, in the context of the RS-232 protocol.
The modem control signals on a TTL-level connection are typically
inverted from the RS-232 levels.
For example, carrier presence is indicated by a high signal on an RS-232
DCD line, and by a low signal on a TTL DCD line.
This is due to the use of inverting line driver buffers to convert between
TTL and RS-232 line levels in most hardware designs.
Generally speaking, a connection to a DB-9 style connector is an RS-232
level signal at up to 12 volts.
A connection to header pins or an edge-connector on an embedded board
is typically a TTL signal at 3.3 or 5 volts.
.Sh FILES
.Bl -tag -width ".Pa /dev/ttyu?.init" -compact
.It Pa /dev/ttyu?

2
sys/arm/arm/pmap-v6-new.c
View File

@ -1109,7 +1109,7 @@ pmap_bootstrap(vm_offset_t firstaddr)
* mapping of pages.
*/
#define SYSMAP(c, p, v, n) do { \
v = (c)pmap_preboot_reserve_pages(1); \
v = (c)pmap_preboot_reserve_pages(n); \
p = pt2map_entry((vm_offset_t)v); \
} while (0)

2
sys/boot/efi/libefi/libefi.c
View File

@ -179,7 +179,7 @@ efi_main(EFI_HANDLE image_handle, EFI_SYSTEM_TABLE *system_table)
argv = malloc((argc + 1) * sizeof(CHAR16*));
argc = 0;
if (addprog)
argv[argc++] = (CHAR16 *)"loader.efi";
argv[argc++] = (CHAR16 *)L"loader.efi";
argp = args;
while (argp != NULL && *argp != 0) {
argp = arg_skipsep(argp);

2
sys/boot/uboot/lib/copy.c
View File

@ -100,7 +100,7 @@ uboot_loadaddr(u_int type, void *data, uint64_t addr)
biggest_block = 0;
biggest_size = 0;
subldr = rounddown2((uint64_t)(uintptr_t)_start, KERN_ALIGN);
subldr = rounddown2((uintptr_t)_start, KERN_ALIGN);
eubldr = roundup2((uint64_t)uboot_heap_end, KERN_ALIGN);
for (i = 0; i < si->mr_no; i++) {
if (si->mr[i].flags != MR_ATTR_DRAM)

9
sys/dev/sfxge/common/efx.h
View File

@ -505,13 +505,6 @@ efx_mac_fcntl_get(
__out unsigned int *fcntl_wantedp,
__out unsigned int *fcntl_linkp);
#define EFX_MAC_HASH_BITS (1 << 8)
extern __checkReturn efx_rc_t
efx_mac_hash_set(
__in efx_nic_t *enp,
__in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
#if EFSYS_OPT_MAC_STATS
@ -1923,8 +1916,6 @@ efx_psuedo_hdr_pkt_length_get(
typedef enum efx_rxq_type_e {
EFX_RXQ_TYPE_DEFAULT,
EFX_RXQ_TYPE_SPLIT_HEADER,
EFX_RXQ_TYPE_SPLIT_PAYLOAD,
EFX_RXQ_TYPE_SCATTER,
EFX_RXQ_NTYPES
} efx_rxq_type_t;

22
sys/dev/sfxge/common/efx_check.h
View File

@ -61,9 +61,6 @@
/* Decode fatal errors */
#if EFSYS_OPT_DECODE_INTR_FATAL
# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA)
# if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
# error "INTR_FATAL not supported on HUNTINGTON or MEDFORD"
# endif
# error "INTR_FATAL requires FALCON or SIENA"
# endif
#endif /* EFSYS_OPT_DECODE_INTR_FATAL */
@ -138,9 +135,6 @@
/* Support management controller messages */
#if EFSYS_OPT_MCDI
# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
# if EFSYS_OPT_FALCON
# error "MCDI not supported on FALCON"
# endif
# error "MCDI requires SIENA or HUNTINGTON or MEDFORD"
# endif
#endif /* EFSYS_OPT_MCDI */
@ -186,14 +180,14 @@
# endif
#endif /* EFSYS_OPT_MON_NULL */
/* Support Siena monitor */
/* Obsolete option */
#ifdef EFSYS_OPT_MON_SIENA
# error "MON_SIENA is obsolete use MON_MCDI"
# error "MON_SIENA is obsolete (replaced by MON_MCDI)."
#endif /* EFSYS_OPT_MON_SIENA*/
/* Support Huntington monitor */
/* Obsolete option */
#ifdef EFSYS_OPT_MON_HUNTINGTON
# error "MON_HUNTINGTON is obsolete use MON_MCDI"
# error "MON_HUNTINGTON is obsolete (replaced by MON_MCDI)."
#endif /* EFSYS_OPT_MON_HUNTINGTON*/
/* Support monitor statistics (voltage/temperature) */
@ -265,9 +259,9 @@
# endif
#endif /* EFSYS_OPT_PCIE_TUNE */
/* Support PHY BIST diagnostics */
/* Obsolete option */
#if EFSYS_OPT_PHY_BIST
# error "PHY_BIST is obsolete. It has been replaced by the BIST option."
# error "PHY_BIST is obsolete (replaced by BIST)."
#endif /* EFSYS_OPT_PHY_BIST */
/* Support PHY flags */
@ -379,7 +373,7 @@
/* Obsolete option */
#ifdef EFSYS_OPT_STAT_NAME
# error "EFSYS_OPT_STAT_NAME is obsolete (replaced by EFSYS_OPT_NAMES)."
# error "STAT_NAME is obsolete (replaced by NAMES)."
#endif
/* Support PCI Vital Product Data (VPD) */
@ -399,7 +393,7 @@
/* Obsolete option */
#ifdef EFSYS_OPT_MCAST_FILTER_LIST
# error "MCAST_FILTER_LIST is obsolete and not supported"
# error "MCAST_FILTER_LIST is obsolete and is not supported"
#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
/* Support BIST */

28
sys/dev/sfxge/common/efx_filter.c
View File

@ -97,17 +97,17 @@ static efx_filter_ops_t __efx_filter_siena_ops = {
};
#endif /* EFSYS_OPT_SIENA */
#if EFSYS_OPT_HUNTINGTON
static efx_filter_ops_t __efx_filter_hunt_ops = {
hunt_filter_init, /* efo_init */
hunt_filter_fini, /* efo_fini */
hunt_filter_restore, /* efo_restore */
hunt_filter_add, /* efo_add */
hunt_filter_delete, /* efo_delete */
hunt_filter_supported_filters, /* efo_supported_filters */
hunt_filter_reconfigure, /* efo_reconfigure */
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
static efx_filter_ops_t __efx_filter_ef10_ops = {
ef10_filter_init, /* efo_init */
ef10_filter_fini, /* efo_fini */
ef10_filter_restore, /* efo_restore */
ef10_filter_add, /* efo_add */
ef10_filter_delete, /* efo_delete */
ef10_filter_supported_filters, /* efo_supported_filters */
ef10_filter_reconfigure, /* efo_reconfigure */
};
#endif /* EFSYS_OPT_HUNTINGTON */
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
__checkReturn efx_rc_t
efx_filter_insert(
@ -189,10 +189,16 @@ efx_filter_init(
#if EFSYS_OPT_HUNTINGTON
case EFX_FAMILY_HUNTINGTON:
efop = (efx_filter_ops_t *)&__efx_filter_hunt_ops;
efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops;
break;
#endif /* EFSYS_OPT_HUNTINGTON */
#if EFSYS_OPT_MEDFORD
case EFX_FAMILY_MEDFORD:
efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops;
break;
#endif /* EFSYS_OPT_MEDFORD */
default:
EFSYS_ASSERT(0);
rc = ENOTSUP;

10
sys/dev/sfxge/common/efx_impl.h
View File

@ -342,6 +342,10 @@ typedef struct efx_intr_ops_s {
void (*eio_disable)(efx_nic_t *);
void (*eio_disable_unlocked)(efx_nic_t *);
efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
void (*eio_status_message)(efx_nic_t *, unsigned int,
boolean_t *);
void (*eio_fatal)(efx_nic_t *);
void (*eio_fini)(efx_nic_t *);
} efx_intr_ops_t;
@ -436,9 +440,9 @@ typedef struct efx_filter_s {
#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
falconsiena_filter_t *ef_falconsiena_filter;
#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
#if EFSYS_OPT_HUNTINGTON
hunt_filter_table_t *ef_hunt_filter_table;
#endif /* EFSYS_OPT_HUNTINGTON */
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
ef10_filter_table_t *ef_ef10_filter_table;
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
} efx_filter_t;
extern void

125
sys/dev/sfxge/common/efx_intr.c
View File

@ -67,14 +67,26 @@ static void
falconsiena_intr_fini(
__in efx_nic_t *enp);
static void
falconsiena_intr_status_line(
__in efx_nic_t *enp,
__out boolean_t *fatalp,
__out uint32_t *qmaskp);
static void
falconsiena_intr_status_message(
__in efx_nic_t *enp,
__in unsigned int message,
__out boolean_t *fatalp);
static void
falconsiena_intr_fatal(
__in efx_nic_t *enp);
static __checkReturn boolean_t
falconsiena_intr_check_fatal(
__in efx_nic_t *enp);
static void
falconsiena_intr_fatal(
__in efx_nic_t *enp);
#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
@ -86,6 +98,9 @@ static efx_intr_ops_t __efx_intr_falcon_ops = {
falconsiena_intr_disable, /* eio_disable */
falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */
falconsiena_intr_trigger, /* eio_trigger */
falconsiena_intr_status_line, /* eio_status_line */
falconsiena_intr_status_message, /* eio_status_message */
falconsiena_intr_fatal, /* eio_fatal */
falconsiena_intr_fini, /* eio_fini */
};
#endif /* EFSYS_OPT_FALCON */
@ -97,6 +112,9 @@ static efx_intr_ops_t __efx_intr_siena_ops = {
falconsiena_intr_disable, /* eio_disable */
falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */
falconsiena_intr_trigger, /* eio_trigger */
falconsiena_intr_status_line, /* eio_status_line */
falconsiena_intr_status_message, /* eio_status_message */
falconsiena_intr_fatal, /* eio_fatal */
falconsiena_intr_fini, /* eio_fini */
};
#endif /* EFSYS_OPT_SIENA */
@ -108,6 +126,9 @@ static efx_intr_ops_t __efx_intr_ef10_ops = {
ef10_intr_disable, /* eio_disable */
ef10_intr_disable_unlocked, /* eio_disable_unlocked */
ef10_intr_trigger, /* eio_trigger */
ef10_intr_status_line, /* eio_status_line */
ef10_intr_status_message, /* eio_status_message */
ef10_intr_fatal, /* eio_fatal */
ef10_intr_fini, /* eio_fini */
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
@ -261,35 +282,12 @@ efx_intr_status_line(
__out uint32_t *qmaskp)
{
efx_intr_t *eip = &(enp->en_intr);
efx_dword_t dword;
efx_intr_ops_t *eiop = eip->ei_eiop;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
/* Ensure Huntington and Falcon/Siena ISR at same location */
EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST ==
ER_DZ_BIU_INT_ISR_REG_OFST);
/*
* Read the queue mask and implicitly acknowledge the
* interrupt.
*/
EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
#if EFSYS_OPT_HUNTINGTON
if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
/* Huntington reports fatal errors via events */
*fatalp = B_FALSE;
return;
}
#endif
if (*qmaskp & (1U << eip->ei_level))
*fatalp = falconsiena_intr_check_fatal(enp);
else
*fatalp = B_FALSE;
eiop->eio_status_line(enp, fatalp, qmaskp);
}
void
@ -299,39 +297,25 @@ efx_intr_status_message(
__out boolean_t *fatalp)
{
efx_intr_t *eip = &(enp->en_intr);
efx_intr_ops_t *eiop = eip->ei_eiop;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
#if EFSYS_OPT_HUNTINGTON
if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
/* Huntington reports fatal errors via events */
*fatalp = B_FALSE;
return;
}
#endif
if (message == eip->ei_level)
*fatalp = falconsiena_intr_check_fatal(enp);
else
*fatalp = B_FALSE;
eiop->eio_status_message(enp, message, fatalp);
}
void
efx_intr_fatal(
__in efx_nic_t *enp)
{
efx_intr_t *eip = &(enp->en_intr);
efx_intr_ops_t *eiop = eip->ei_eiop;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
#if EFSYS_OPT_HUNTINGTON
if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
/* Huntington reports fatal errors via events */
return;
}
#endif
#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
falconsiena_intr_fatal(enp);
#endif
eiop->eio_fatal(enp);
}
@ -514,6 +498,51 @@ falconsiena_intr_check_fatal(
return (B_FALSE);
}
static void
falconsiena_intr_status_line(
__in efx_nic_t *enp,
__out boolean_t *fatalp,
__out uint32_t *qmaskp)
{
efx_intr_t *eip = &(enp->en_intr);
efx_dword_t dword;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
/*
* Read the queue mask and implicitly acknowledge the
* interrupt.
*/
EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
if (*qmaskp & (1U << eip->ei_level))
*fatalp = falconsiena_intr_check_fatal(enp);
else
*fatalp = B_FALSE;
}
static void
falconsiena_intr_status_message(
__in efx_nic_t *enp,
__in unsigned int message,
__out boolean_t *fatalp)
{
efx_intr_t *eip = &(enp->en_intr);
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
if (message == eip->ei_level)
*fatalp = falconsiena_intr_check_fatal(enp);
else
*fatalp = B_FALSE;
}
static void
falconsiena_intr_fatal(
__in efx_nic_t *enp)

51
sys/dev/sfxge/common/efx_mac.c
View File

@ -462,55 +462,6 @@ efx_mac_fcntl_get(
*fcntl_wantedp = wanted;
}
/*
* FIXME: efx_mac_hash_set() should be deleted once all its callers have been
* updated to use efx_mac_multicast_list_set().
* Then efx_port_t.ep_multicst_hash could be made Falcon/Siena specific as
* well.
*/
__checkReturn efx_rc_t
efx_mac_hash_set(
__in efx_nic_t *enp,
__in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket)
{
efx_port_t *epp = &(enp->en_port);
efx_mac_ops_t *emop = epp->ep_emop;
efx_oword_t old_hash[2];
unsigned int index;
efx_rc_t rc;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash));
/* Set the lower 128 bits of the hash */
EFX_ZERO_OWORD(epp->ep_multicst_hash[0]);
for (index = 0; index < 128; index++) {
if (bucket[index] != 0)
EFX_SET_OWORD_BIT(epp->ep_multicst_hash[0], index);
}
/* Set the upper 128 bits of the hash */
EFX_ZERO_OWORD(epp->ep_multicst_hash[1]);
for (index = 0; index < 128; index++) {
if (bucket[index + 128] != 0)
EFX_SET_OWORD_BIT(epp->ep_multicst_hash[1], index);
}
if ((rc = emop->emo_reconfigure(enp)) != 0)
goto fail1;
return (0);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash));
return (rc);
}
__checkReturn efx_rc_t
efx_mac_multicast_list_set(
__in efx_nic_t *enp,
@ -912,6 +863,8 @@ efx_mac_select(
#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
#define EFX_MAC_HASH_BITS (1 << 8)
/* Compute the multicast hash as used on Falcon and Siena. */
static void
falconsiena_mac_multicast_hash_compute(

3
sys/dev/sfxge/common/efx_mcdi.c
View File

@ -643,7 +643,6 @@ efx_mcdi_ev_cpl(
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
efx_nic_cfg_t *encp = &enp->en_nic_cfg;
efx_mcdi_req_t *emrp;
int state;
@ -668,7 +667,7 @@ efx_mcdi_ev_cpl(
emip->emi_pending_req = NULL;
EFSYS_UNLOCK(enp->en_eslp, state);
if (encp->enc_mcdi_max_payload_length > MCDI_CTL_SDU_LEN_MAX_V1) {
if (emip->emi_max_version >= 2) {
/* MCDIv2 response details do not fit into an event. */
efx_mcdi_read_response_header(enp, emrp);
} else {

1
sys/dev/sfxge/common/efx_mcdi.h
View File

@ -69,6 +69,7 @@ struct efx_mcdi_req_s {
typedef struct efx_mcdi_iface_s {
unsigned int emi_port;
unsigned int emi_max_version;
unsigned int emi_seq;
efx_mcdi_req_t *emi_pending_req;
boolean_t emi_ev_cpl;

920
sys/dev/sfxge/common/efx_regs_mcdi.h
View File

File diff suppressed because it is too large Load Diff

8
sys/dev/sfxge/common/efx_rx.c
View File

@ -1246,7 +1246,6 @@ falconsiena_rx_qcreate(
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_oword_t oword;
uint32_t size;
boolean_t split;
boolean_t jumbo;
efx_rc_t rc;
@ -1277,7 +1276,6 @@ falconsiena_rx_qcreate(
switch (type) {
case EFX_RXQ_TYPE_DEFAULT:
split = B_FALSE;
jumbo = B_FALSE;
break;
@ -1307,7 +1305,6 @@ falconsiena_rx_qcreate(
rc = EINVAL;
goto fail4;
}
split = B_FALSE;
jumbo = B_TRUE;
break;
#endif /* EFSYS_OPT_RX_SCATTER */
@ -1318,10 +1315,7 @@ falconsiena_rx_qcreate(
}
/* Set up the new descriptor queue */
EFX_POPULATE_OWORD_10(oword,
FRF_CZ_RX_HDR_SPLIT, split,
FRF_AZ_RX_ISCSI_DDIG_EN, 0,
FRF_AZ_RX_ISCSI_HDIG_EN, 0,
EFX_POPULATE_OWORD_7(oword,
FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
FRF_AZ_RX_DESCQ_OWNER_ID, 0,

5
sys/dev/sfxge/common/hunt_ev.c
View File

@ -499,7 +499,6 @@ ef10_ev_rx(
uint32_t l3_class;
uint32_t l4_class;
uint32_t next_read_lbits;
boolean_t soft1, soft2;
uint16_t flags;
boolean_t should_abort;
efx_evq_rxq_state_t *eersp;
@ -561,10 +560,6 @@ ef10_ev_rx(
flags |= EFX_DISCARD;
}
/* FIXME: do we need soft bits from RXDP firmware ? */
soft1 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT1) != 0);
soft2 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT2) != 0);
mcast = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
if (mcast == ESE_DZ_MAC_CLASS_UCAST)
flags |= EFX_PKT_UNICAST;

373
sys/dev/sfxge/common/hunt_filter.c
View File

@ -41,90 +41,91 @@ __FBSDID("$FreeBSD$");
#if EFSYS_OPT_FILTER
#define HFE_SPEC(hftp, index) ((hftp)->hft_entry[(index)].hfe_spec)
#define EFE_SPEC(eftp, index) ((eftp)->eft_entry[(index)].efe_spec)
static efx_filter_spec_t *
hunt_filter_entry_spec(
__in const hunt_filter_table_t *hftp,
ef10_filter_entry_spec(
__in const ef10_filter_table_t *eftp,
__in unsigned int index)
{
return ((efx_filter_spec_t *)(HFE_SPEC(hftp, index) &
~(uintptr_t)EFX_HUNT_FILTER_FLAGS));
return ((efx_filter_spec_t *)(EFE_SPEC(eftp, index) &
~(uintptr_t)EFX_EF10_FILTER_FLAGS));
}
static boolean_t
hunt_filter_entry_is_busy(
__in const hunt_filter_table_t *hftp,
ef10_filter_entry_is_busy(
__in const ef10_filter_table_t *eftp,
__in unsigned int index)
{
if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_BUSY)
if (EFE_SPEC(eftp, index) & EFX_EF10_FILTER_FLAG_BUSY)
return (B_TRUE);
else
return (B_FALSE);
}
static boolean_t
hunt_filter_entry_is_auto_old(
__in const hunt_filter_table_t *hftp,
ef10_filter_entry_is_auto_old(
__in const ef10_filter_table_t *eftp,
__in unsigned int index)
{
if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_AUTO_OLD)
if (EFE_SPEC(eftp, index) & EFX_EF10_FILTER_FLAG_AUTO_OLD)
return (B_TRUE);
else
return (B_FALSE);
}
static void
hunt_filter_set_entry(
__inout hunt_filter_table_t *hftp,
ef10_filter_set_entry(
__inout ef10_filter_table_t *eftp,
__in unsigned int index,
__in_opt const efx_filter_spec_t *efsp)
{
HFE_SPEC(hftp, index) = (uintptr_t)efsp;
EFE_SPEC(eftp, index) = (uintptr_t)efsp;
}
static void
hunt_filter_set_entry_busy(
__inout hunt_filter_table_t *hftp,
ef10_filter_set_entry_busy(
__inout ef10_filter_table_t *eftp,
__in unsigned int index)
{
HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY;
EFE_SPEC(eftp, index) |= (uintptr_t)EFX_EF10_FILTER_FLAG_BUSY;
}
static void
hunt_filter_set_entry_not_busy(
__inout hunt_filter_table_t *hftp,
ef10_filter_set_entry_not_busy(
__inout ef10_filter_table_t *eftp,
__in unsigned int index)
{
HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY;
EFE_SPEC(eftp, index) &= ~(uintptr_t)EFX_EF10_FILTER_FLAG_BUSY;
}
static void
hunt_filter_set_entry_auto_old(
__inout hunt_filter_table_t *hftp,
ef10_filter_set_entry_auto_old(
__inout ef10_filter_table_t *eftp,
__in unsigned int index)
{
EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL);
HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD;
EFSYS_ASSERT(ef10_filter_entry_spec(eftp, index) != NULL);
EFE_SPEC(eftp, index) |= (uintptr_t)EFX_EF10_FILTER_FLAG_AUTO_OLD;
}
static void
hunt_filter_set_entry_not_auto_old(
__inout hunt_filter_table_t *hftp,
ef10_filter_set_entry_not_auto_old(
__inout ef10_filter_table_t *eftp,
__in unsigned int index)
{
HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD;
EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL);
EFE_SPEC(eftp, index) &= ~(uintptr_t)EFX_EF10_FILTER_FLAG_AUTO_OLD;
EFSYS_ASSERT(ef10_filter_entry_spec(eftp, index) != NULL);
}
__checkReturn efx_rc_t
hunt_filter_init(
ef10_filter_init(
__in efx_nic_t *enp)
{
efx_rc_t rc;
hunt_filter_table_t *hftp;
ef10_filter_table_t *eftp;
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
#define MATCH_MASK(match) (EFX_MASK32(match) << EFX_LOW_BIT(match))
EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_HOST ==
@ -149,14 +150,14 @@ hunt_filter_init(
MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO));
#undef MATCH_MASK
EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (hunt_filter_table_t), hftp);
EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (ef10_filter_table_t), eftp);
if (!hftp) {
if (!eftp) {
rc = ENOMEM;
goto fail1;
}
enp->en_filter.ef_hunt_filter_table = hftp;
enp->en_filter.ef_ef10_filter_table = eftp;
return (0);
@ -167,14 +168,15 @@ hunt_filter_init(
}
void
hunt_filter_fini(
ef10_filter_fini(
__in efx_nic_t *enp)
{
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
if (enp->en_filter.ef_hunt_filter_table != NULL) {
EFSYS_KMEM_FREE(enp->en_esip, sizeof (hunt_filter_table_t),
enp->en_filter.ef_hunt_filter_table);
if (enp->en_filter.ef_ef10_filter_table != NULL) {
EFSYS_KMEM_FREE(enp->en_esip, sizeof (ef10_filter_table_t),
enp->en_filter.ef_ef10_filter_table);
}
}
@ -183,7 +185,7 @@ efx_mcdi_filter_op_add(
__in efx_nic_t *enp,
__in efx_filter_spec_t *spec,
__in unsigned int filter_op,
__inout hunt_filter_handle_t *handle)
__inout ef10_filter_handle_t *handle)
{
efx_mcdi_req_t req;
uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN,
@ -201,9 +203,9 @@ efx_mcdi_filter_op_add(
switch (filter_op) {
case MC_CMD_FILTER_OP_IN_OP_REPLACE:
MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO,
handle->hfh_lo);
handle->efh_lo);
MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI,
handle->hfh_hi);
handle->efh_hi);
/* Fall through */
case MC_CMD_FILTER_OP_IN_OP_INSERT:
case MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE:
@ -302,8 +304,8 @@ efx_mcdi_filter_op_add(
goto fail3;
}
handle->hfh_lo = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_LO);
handle->hfh_hi = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_HI);
handle->efh_lo = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_LO);
handle->efh_hi = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_HI);
return (0);
@ -322,7 +324,7 @@ static __checkReturn efx_rc_t
efx_mcdi_filter_op_delete(
__in efx_nic_t *enp,
__in unsigned int filter_op,
__inout hunt_filter_handle_t *handle)
__inout ef10_filter_handle_t *handle)
{
efx_mcdi_req_t req;
uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN,
@ -351,8 +353,8 @@ efx_mcdi_filter_op_delete(
goto fail1;
}
MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, handle->hfh_lo);
MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, handle->hfh_hi);
MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, handle->efh_lo);
MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, handle->efh_hi);
efx_mcdi_execute(enp, &req);
@ -380,7 +382,7 @@ efx_mcdi_filter_op_delete(
}
static __checkReturn boolean_t
hunt_filter_equal(
ef10_filter_equal(
__in const efx_filter_spec_t *left,
__in const efx_filter_spec_t *right)
{
@ -413,7 +415,7 @@ hunt_filter_equal(
}
static __checkReturn boolean_t
hunt_filter_same_dest(
ef10_filter_same_dest(
__in const efx_filter_spec_t *left,
__in const efx_filter_spec_t *right)
{
@ -430,7 +432,7 @@ hunt_filter_same_dest(
}
static __checkReturn uint32_t
hunt_filter_hash(
ef10_filter_hash(
__in efx_filter_spec_t *spec)
{
EFX_STATIC_ASSERT((sizeof (efx_filter_spec_t) % sizeof (uint32_t))
@ -456,7 +458,7 @@ hunt_filter_hash(
* exclusive.
*/
static __checkReturn boolean_t
hunt_filter_is_exclusive(
ef10_filter_is_exclusive(
__in efx_filter_spec_t *spec)
{
if ((spec->efs_match_flags & EFX_FILTER_MATCH_LOC_MAC) &&
@ -478,30 +480,31 @@ hunt_filter_is_exclusive(
}
__checkReturn efx_rc_t
hunt_filter_restore(
ef10_filter_restore(
__in efx_nic_t *enp)
{
int tbl_id;
efx_filter_spec_t *spec;
hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table;
boolean_t restoring;
int state;
efx_rc_t rc;
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
for (tbl_id = 0; tbl_id < EFX_HUNT_FILTER_TBL_ROWS; tbl_id++) {
for (tbl_id = 0; tbl_id < EFX_EF10_FILTER_TBL_ROWS; tbl_id++) {
EFSYS_LOCK(enp->en_eslp, state);
spec = hunt_filter_entry_spec(hftp, tbl_id);
spec = ef10_filter_entry_spec(eftp, tbl_id);
if (spec == NULL) {
restoring = B_FALSE;
} else if (hunt_filter_entry_is_busy(hftp, tbl_id)) {
} else if (ef10_filter_entry_is_busy(eftp, tbl_id)) {
/* Ignore busy entries. */
restoring = B_FALSE;
} else {
hunt_filter_set_entry_busy(hftp, tbl_id);
ef10_filter_set_entry_busy(eftp, tbl_id);
restoring = B_TRUE;
}
@ -510,14 +513,14 @@ hunt_filter_restore(
if (restoring == B_FALSE)
continue;
if (hunt_filter_is_exclusive(spec)) {
if (ef10_filter_is_exclusive(spec)) {
rc = efx_mcdi_filter_op_add(enp, spec,
MC_CMD_FILTER_OP_IN_OP_INSERT,
&hftp->hft_entry[tbl_id].hfe_handle);
&eftp->eft_entry[tbl_id].efe_handle);
} else {
rc = efx_mcdi_filter_op_add(enp, spec,
MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE,
&hftp->hft_entry[tbl_id].hfe_handle);
&eftp->eft_entry[tbl_id].efe_handle);
}
if (rc != 0)
@ -525,7 +528,7 @@ hunt_filter_restore(
EFSYS_LOCK(enp->en_eslp, state);
hunt_filter_set_entry_not_busy(hftp, tbl_id);
ef10_filter_set_entry_not_busy(eftp, tbl_id);
EFSYS_UNLOCK(enp->en_eslp, state);
}
@ -542,17 +545,17 @@ hunt_filter_restore(
* An arbitrary search limit for the software hash table. As per the linux net
* driver.
*/
#define EFX_HUNT_FILTER_SEARCH_LIMIT 200
#define EF10_FILTER_SEARCH_LIMIT 200
static __checkReturn efx_rc_t
hunt_filter_add_internal(
ef10_filter_add_internal(
__in efx_nic_t *enp,
__inout efx_filter_spec_t *spec,
__in boolean_t may_replace,
__out_opt uint32_t *filter_id)
{
efx_rc_t rc;
hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table;
efx_filter_spec_t *saved_spec;
uint32_t hash;
unsigned int depth;
@ -562,13 +565,14 @@ hunt_filter_add_internal(
int state;
boolean_t locked = B_FALSE;
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
#if EFSYS_OPT_RX_SCALE
spec->efs_rss_context = enp->en_rss_context;
#endif
hash = hunt_filter_hash(spec);
hash = ef10_filter_hash(spec);
/*
* FIXME: Add support for inserting filters of different priorities
@ -587,21 +591,21 @@ hunt_filter_add_internal(
locked = B_TRUE;
for (;;) {
i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1);
saved_spec = hunt_filter_entry_spec(hftp, i);
i = (hash + depth) & (EFX_EF10_FILTER_TBL_ROWS - 1);
saved_spec = ef10_filter_entry_spec(eftp, i);
if (!saved_spec) {
if (ins_index < 0) {
ins_index = i;
}
} else if (hunt_filter_equal(spec, saved_spec)) {
if (hunt_filter_entry_is_busy(hftp, i))
} else if (ef10_filter_equal(spec, saved_spec)) {
if (ef10_filter_entry_is_busy(eftp, i))
break;
if (saved_spec->efs_priority
== EFX_FILTER_PRI_AUTO) {
ins_index = i;
goto found;
} else if (hunt_filter_is_exclusive(spec)) {
} else if (ef10_filter_is_exclusive(spec)) {
if (may_replace) {
ins_index = i;
goto found;
@ -619,7 +623,7 @@ hunt_filter_add_internal(
* the first suitable slot or return EBUSY if
* there was none.
*/
if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) {
if (depth == EF10_FILTER_SEARCH_LIMIT) {
if (ins_index < 0) {
rc = EBUSY;
goto fail2;
@ -639,11 +643,11 @@ hunt_filter_add_internal(
* insert a conflicting filter while we're waiting for the
* firmware must find the busy entry.
*/
saved_spec = hunt_filter_entry_spec(hftp, ins_index);
saved_spec = ef10_filter_entry_spec(eftp, ins_index);
if (saved_spec) {
if (saved_spec->efs_priority == EFX_FILTER_PRI_AUTO) {
/* This is a filter we are refreshing */
hunt_filter_set_entry_not_auto_old(hftp, ins_index);
ef10_filter_set_entry_not_auto_old(eftp, ins_index);
goto out_unlock;
}
@ -655,9 +659,9 @@ hunt_filter_add_internal(
goto fail3;
}
*saved_spec = *spec;
hunt_filter_set_entry(hftp, ins_index, saved_spec);
ef10_filter_set_entry(eftp, ins_index, saved_spec);
}
hunt_filter_set_entry_busy(hftp, ins_index);
ef10_filter_set_entry_busy(eftp, ins_index);
EFSYS_UNLOCK(enp->en_eslp, state);
locked = B_FALSE;
@ -669,15 +673,15 @@ hunt_filter_add_internal(
if (replacing) {
rc = efx_mcdi_filter_op_add(enp, spec,
MC_CMD_FILTER_OP_IN_OP_REPLACE,
&hftp->hft_entry[ins_index].hfe_handle);
} else if (hunt_filter_is_exclusive(spec)) {
&eftp->eft_entry[ins_index].efe_handle);
} else if (ef10_filter_is_exclusive(spec)) {
rc = efx_mcdi_filter_op_add(enp, spec,
MC_CMD_FILTER_OP_IN_OP_INSERT,
&hftp->hft_entry[ins_index].hfe_handle);
&eftp->eft_entry[ins_index].efe_handle);
} else {
rc = efx_mcdi_filter_op_add(enp, spec,
MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE,
&hftp->hft_entry[ins_index].hfe_handle);
&eftp->eft_entry[ins_index].efe_handle);
}
if (rc != 0)
@ -694,7 +698,7 @@ hunt_filter_add_internal(
saved_spec->efs_dmaq_id = spec->efs_dmaq_id;
}
hunt_filter_set_entry_not_busy(hftp, ins_index);
ef10_filter_set_entry_not_busy(eftp, ins_index);
out_unlock:
@ -713,8 +717,8 @@ hunt_filter_add_internal(
EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), saved_spec);
saved_spec = NULL;
}
hunt_filter_set_entry_not_busy(hftp, ins_index);
hunt_filter_set_entry(hftp, ins_index, NULL);
ef10_filter_set_entry_not_busy(eftp, ins_index);
ef10_filter_set_entry(eftp, ins_index, NULL);
fail3:
EFSYS_PROBE(fail3);
@ -732,14 +736,14 @@ hunt_filter_add_internal(
}
__checkReturn efx_rc_t
hunt_filter_add(
ef10_filter_add(
__in efx_nic_t *enp,
__inout efx_filter_spec_t *spec,
__in boolean_t may_replace)
{
efx_rc_t rc;
rc = hunt_filter_add_internal(enp, spec, may_replace, NULL);
rc = ef10_filter_add_internal(enp, spec, may_replace, NULL);
if (rc != 0)
goto fail1;
@ -753,15 +757,15 @@ hunt_filter_add(
static __checkReturn efx_rc_t
hunt_filter_delete_internal(
ef10_filter_delete_internal(
__in efx_nic_t *enp,
__in uint32_t filter_id)
{
efx_rc_t rc;
hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table;
efx_filter_spec_t *spec;
int state;
uint32_t filter_idx = filter_id % EFX_HUNT_FILTER_TBL_ROWS;
uint32_t filter_idx = filter_id % EFX_EF10_FILTER_TBL_ROWS;
/*
* Find the software table entry and mark it busy. Don't
@ -771,13 +775,13 @@ hunt_filter_delete_internal(
* FIXME: What if the busy flag is never cleared?
*/
EFSYS_LOCK(enp->en_eslp, state);
while (hunt_filter_entry_is_busy(table, filter_idx)) {
while (ef10_filter_entry_is_busy(table, filter_idx)) {
EFSYS_UNLOCK(enp->en_eslp, state);
EFSYS_SPIN(1);
EFSYS_LOCK(enp->en_eslp, state);
}
if ((spec = hunt_filter_entry_spec(table, filter_idx)) != NULL) {
hunt_filter_set_entry_busy(table, filter_idx);
if ((spec = ef10_filter_entry_spec(table, filter_idx)) != NULL) {
ef10_filter_set_entry_busy(table, filter_idx);
}
EFSYS_UNLOCK(enp->en_eslp, state);
@ -790,20 +794,20 @@ hunt_filter_delete_internal(
* Try to remove the hardware filter. This may fail if the MC has
* rebooted (which frees all hardware filter resources).
*/
if (hunt_filter_is_exclusive(spec)) {
if (ef10_filter_is_exclusive(spec)) {
rc = efx_mcdi_filter_op_delete(enp,
MC_CMD_FILTER_OP_IN_OP_REMOVE,
&table->hft_entry[filter_idx].hfe_handle);
&table->eft_entry[filter_idx].efe_handle);
} else {
rc = efx_mcdi_filter_op_delete(enp,
MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE,
&table->hft_entry[filter_idx].hfe_handle);
&table->eft_entry[filter_idx].efe_handle);
}
/* Free the software table entry */
EFSYS_LOCK(enp->en_eslp, state);
hunt_filter_set_entry_not_busy(table, filter_idx);
hunt_filter_set_entry(table, filter_idx, NULL);
ef10_filter_set_entry_not_busy(table, filter_idx);
ef10_filter_set_entry(table, filter_idx, NULL);
EFSYS_UNLOCK(enp->en_eslp, state);
EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
@ -824,12 +828,12 @@ hunt_filter_delete_internal(
}
__checkReturn efx_rc_t
hunt_filter_delete(
ef10_filter_delete(
__in efx_nic_t *enp,
__inout efx_filter_spec_t *spec)
{
efx_rc_t rc;
hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table;
efx_filter_spec_t *saved_spec;
unsigned int hash;
unsigned int depth;
@ -837,22 +841,23 @@ hunt_filter_delete(
int state;
boolean_t locked = B_FALSE;
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
hash = hunt_filter_hash(spec);
hash = ef10_filter_hash(spec);
EFSYS_LOCK(enp->en_eslp, state);
locked = B_TRUE;
depth = 1;
for (;;) {
i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1);
saved_spec = hunt_filter_entry_spec(table, i);
if (saved_spec && hunt_filter_equal(spec, saved_spec) &&
hunt_filter_same_dest(spec, saved_spec)) {
i = (hash + depth) & (EFX_EF10_FILTER_TBL_ROWS - 1);
saved_spec = ef10_filter_entry_spec(table, i);
if (saved_spec && ef10_filter_equal(spec, saved_spec) &&
ef10_filter_same_dest(spec, saved_spec)) {
break;
}
if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) {
if (depth == EF10_FILTER_SEARCH_LIMIT) {
rc = ENOENT;
goto fail1;
}
@ -862,7 +867,7 @@ hunt_filter_delete(
EFSYS_UNLOCK(enp->en_eslp, state);
locked = B_FALSE;
rc = hunt_filter_delete_internal(enp, i);
rc = ef10_filter_delete_internal(enp, i);
if (rc != 0)
goto fail2;
@ -961,7 +966,7 @@ efx_mcdi_get_parser_disp_info(
}
__checkReturn efx_rc_t
hunt_filter_supported_filters(
ef10_filter_supported_filters(
__in efx_nic_t *enp,
__out uint32_t *list,
__out size_t *length)
@ -980,13 +985,13 @@ hunt_filter_supported_filters(
}
static __checkReturn efx_rc_t
hunt_filter_unicast_refresh(
ef10_filter_unicast_refresh(
__in efx_nic_t *enp,
__in_ecount(6) uint8_t const *addr,
__in boolean_t all_unicst,
__in efx_filter_flag_t filter_flags)
{
hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table;
efx_filter_spec_t spec;
efx_rc_t rc;
@ -996,11 +1001,11 @@ hunt_filter_unicast_refresh(
/* Insert the filter for the local station address */
efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO,
filter_flags,
hftp->hft_default_rxq);
eftp->eft_default_rxq);
efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, addr);
rc = hunt_filter_add_internal(enp, &spec, B_TRUE,
&hftp->hft_unicst_filter_index);
rc = ef10_filter_add_internal(enp, &spec, B_TRUE,
&eftp->eft_unicst_filter_index);
if (rc != 0) {
/*
* Fall back to an unknown filter. We may be able to subscribe
@ -1008,7 +1013,7 @@ hunt_filter_unicast_refresh(
*/
goto use_uc_def;
}
hftp->hft_unicst_filter_set = B_TRUE;
eftp->eft_unicst_filter_set = B_TRUE;
return (0);
@ -1016,32 +1021,32 @@ hunt_filter_unicast_refresh(
/* Insert the unknown unicast filter */
efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO,
filter_flags,
hftp->hft_default_rxq);
eftp->eft_default_rxq);
efx_filter_spec_set_uc_def(&spec);
rc = hunt_filter_add_internal(enp, &spec, B_TRUE,
&hftp->hft_unicst_filter_index);
rc = ef10_filter_add_internal(enp, &spec, B_TRUE,
&eftp->eft_unicst_filter_index);
if (rc != 0)
goto fail1;
hftp->hft_unicst_filter_set = B_TRUE;
eftp->eft_unicst_filter_set = B_TRUE;
return (0);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
if (hftp->hft_unicst_filter_set != B_FALSE) {
(void) hunt_filter_delete_internal(enp,
hftp->hft_unicst_filter_index);
if (eftp->eft_unicst_filter_set != B_FALSE) {
(void) ef10_filter_delete_internal(enp,
eftp->eft_unicst_filter_index);
hftp->hft_unicst_filter_set = B_FALSE;
eftp->eft_unicst_filter_set = B_FALSE;
}
return (rc);
}
static __checkReturn efx_rc_t
hunt_filter_multicast_refresh(
ef10_filter_multicast_refresh(
__in efx_nic_t *enp,
__in boolean_t mulcst,
__in boolean_t all_mulcst,
@ -1050,7 +1055,7 @@ hunt_filter_multicast_refresh(
__in int count,
__in efx_filter_flag_t filter_flags)
{
hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table;
efx_filter_spec_t spec;
uint8_t addr[6];
unsigned i;
@ -1063,25 +1068,25 @@ hunt_filter_multicast_refresh(
count = 0;
if (count + (brdcst ? 1 : 0) >
EFX_ARRAY_SIZE(hftp->hft_mulcst_filter_indexes)) {
EFX_ARRAY_SIZE(eftp->eft_mulcst_filter_indexes)) {
/* Too many MAC addresses; use unknown multicast filter */
goto use_mc_def;
}
/* Insert/renew multicast address list filters */
hftp->hft_mulcst_filter_count = count;
for (i = 0; i < hftp->hft_mulcst_filter_count; i++) {
eftp->eft_mulcst_filter_count = count;
for (i = 0; i < eftp->eft_mulcst_filter_count; i++) {
efx_filter_spec_init_rx(&spec,
EFX_FILTER_PRI_AUTO,
filter_flags,
hftp->hft_default_rxq);
eftp->eft_default_rxq);
efx_filter_spec_set_eth_local(&spec,
EFX_FILTER_SPEC_VID_UNSPEC,
&addrs[i * EFX_MAC_ADDR_LEN]);
rc = hunt_filter_add_internal(enp, &spec, B_TRUE,
&hftp->hft_mulcst_filter_indexes[i]);
rc = ef10_filter_add_internal(enp, &spec, B_TRUE,
&eftp->eft_mulcst_filter_indexes[i]);
if (rc != 0) {
/* Rollback, then use unknown multicast filter */
goto rollback;
@ -1090,18 +1095,18 @@ hunt_filter_multicast_refresh(
if (brdcst == B_TRUE) {
/* Insert/renew broadcast address filter */
hftp->hft_mulcst_filter_count++;
eftp->eft_mulcst_filter_count++;
efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO,
filter_flags,
hftp->hft_default_rxq);
eftp->eft_default_rxq);
EFX_MAC_BROADCAST_ADDR_SET(addr);
efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC,
addr);
rc = hunt_filter_add_internal(enp, &spec, B_TRUE,
&hftp->hft_mulcst_filter_indexes[
hftp->hft_mulcst_filter_count - 1]);
rc = ef10_filter_add_internal(enp, &spec, B_TRUE,
&eftp->eft_mulcst_filter_indexes[
eftp->eft_mulcst_filter_count - 1]);
if (rc != 0) {
/* Rollback, then use unknown multicast filter */
goto rollback;
@ -1116,24 +1121,24 @@ hunt_filter_multicast_refresh(
* before inserting the unknown multicast filter.
*/
while (i--) {
(void) hunt_filter_delete_internal(enp,
hftp->hft_mulcst_filter_indexes[i]);
(void) ef10_filter_delete_internal(enp,
eftp->eft_mulcst_filter_indexes[i]);
}
hftp->hft_mulcst_filter_count = 0;
eftp->eft_mulcst_filter_count = 0;
use_mc_def:
/* Insert the unknown multicast filter */
efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO,
filter_flags,
hftp->hft_default_rxq);
eftp->eft_default_rxq);
efx_filter_spec_set_mc_def(&spec);
rc = hunt_filter_add_internal(enp, &spec, B_TRUE,
&hftp->hft_mulcst_filter_indexes[0]);
rc = ef10_filter_add_internal(enp, &spec, B_TRUE,
&eftp->eft_mulcst_filter_indexes[0]);
if (rc != 0)
goto fail1;
hftp->hft_mulcst_filter_count = 1;
eftp->eft_mulcst_filter_count = 1;
/*
* FIXME: If brdcst == B_FALSE, add a filter to drop broadcast traffic.
@ -1192,7 +1197,7 @@ hunt_filter_get_workarounds(
* still applied in this case).
*/
__checkReturn efx_rc_t
hunt_filter_reconfigure(
ef10_filter_reconfigure(
__in efx_nic_t *enp,
__in_ecount(6) uint8_t const *mac_addr,
__in boolean_t all_unicst,
@ -1202,58 +1207,58 @@ hunt_filter_reconfigure(
__in_ecount(6*count) uint8_t const *addrs,
__in int count)
{
hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table;
efx_filter_flag_t filter_flags;
unsigned i;
int all_unicst_rc;
int all_mulcst_rc;
efx_rc_t rc;
if (table->hft_default_rxq == NULL) {
if (table->eft_default_rxq == NULL) {
/*
* Filters direct traffic to the default RXQ, and so cannot be
* inserted until it is available. Any currently configured
* filters must be removed (ignore errors in case the MC
* has rebooted, which removes hardware filters).
*/
if (table->hft_unicst_filter_set != B_FALSE) {
(void) hunt_filter_delete_internal(enp,
table->hft_unicst_filter_index);
table->hft_unicst_filter_set = B_FALSE;
if (table->eft_unicst_filter_set != B_FALSE) {
(void) ef10_filter_delete_internal(enp,
table->eft_unicst_filter_index);
table->eft_unicst_filter_set = B_FALSE;
}
for (i = 0; i < table->hft_mulcst_filter_count; i++) {
(void) hunt_filter_delete_internal(enp,
table->hft_mulcst_filter_indexes[i]);
for (i = 0; i < table->eft_mulcst_filter_count; i++) {
(void) ef10_filter_delete_internal(enp,
table->eft_mulcst_filter_indexes[i]);
}
table->hft_mulcst_filter_count = 0;
table->eft_mulcst_filter_count = 0;
return (0);
}
if (table->hft_using_rss)
if (table->eft_using_rss)
filter_flags = EFX_FILTER_FLAG_RX_RSS;
else
filter_flags = 0;
/* Mark old filters which may need to be removed */
if (table->hft_unicst_filter_set != B_FALSE) {
hunt_filter_set_entry_auto_old(table,
table->hft_unicst_filter_index);
if (table->eft_unicst_filter_set != B_FALSE) {
ef10_filter_set_entry_auto_old(table,
table->eft_unicst_filter_index);
}
for (i = 0; i < table->hft_mulcst_filter_count; i++) {
hunt_filter_set_entry_auto_old(table,
table->hft_mulcst_filter_indexes[i]);
for (i = 0; i < table->eft_mulcst_filter_count; i++) {
ef10_filter_set_entry_auto_old(table,
table->eft_mulcst_filter_indexes[i]);
}
/* Insert or renew unicast filters */
if ((all_unicst_rc = hunt_filter_unicast_refresh(enp, mac_addr,
if ((all_unicst_rc = ef10_filter_unicast_refresh(enp, mac_addr,
all_unicst, filter_flags)) != 0) {
if (all_unicst == B_FALSE) {
rc = all_unicst_rc;
goto fail1;
}
/* Retry without all_unicast flag */
rc = hunt_filter_unicast_refresh(enp, mac_addr,
rc = ef10_filter_unicast_refresh(enp, mac_addr,
B_FALSE, filter_flags);
if (rc != 0)
goto fail2;
@ -1272,12 +1277,14 @@ hunt_filter_reconfigure(
* filters. This ensures that encp->enc_workaround_bug26807 matches the
* firmware state, and that later changes to enable/disable the
* workaround will result in this function seeing a reset (FLR).
*
* FIXME: On Medford mulicast chaining should always be on.
*/
if ((rc = hunt_filter_get_workarounds(enp)) != 0)
goto fail3;
/* Insert or renew multicast filters */
if ((all_mulcst_rc = hunt_filter_multicast_refresh(enp, mulcst,
if ((all_mulcst_rc = ef10_filter_multicast_refresh(enp, mulcst,
all_mulcst, brdcst,
addrs, count, filter_flags)) != 0) {
if (all_mulcst == B_FALSE) {
@ -1285,7 +1292,7 @@ hunt_filter_reconfigure(
goto fail4;
}
/* Retry without all_mulcast flag */
rc = hunt_filter_multicast_refresh(enp, mulcst,
rc = ef10_filter_multicast_refresh(enp, mulcst,
B_FALSE, brdcst,
addrs, count, filter_flags);
if (rc != 0)
@ -1293,9 +1300,9 @@ hunt_filter_reconfigure(
}
/* Remove old filters which were not renewed */
for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) {
if (hunt_filter_entry_is_auto_old(table, i)) {
(void) hunt_filter_delete_internal(enp, i);
for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) {
if (ef10_filter_entry_is_auto_old(table, i)) {
(void) ef10_filter_delete_internal(enp, i);
}
}
@ -1319,9 +1326,9 @@ hunt_filter_reconfigure(
EFSYS_PROBE1(fail1, efx_rc_t, rc);
/* Clear auto old flags */
for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) {
if (hunt_filter_entry_is_auto_old(table, i)) {
hunt_filter_set_entry_not_auto_old(table, i);
for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) {
if (ef10_filter_entry_is_auto_old(table, i)) {
ef10_filter_set_entry_not_auto_old(table, i);
}
}
@ -1329,45 +1336,45 @@ hunt_filter_reconfigure(
}
void
hunt_filter_get_default_rxq(
ef10_filter_get_default_rxq(
__in efx_nic_t *enp,
__out efx_rxq_t **erpp,
__out boolean_t *using_rss)
{
hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table;
*erpp = table->hft_default_rxq;
*using_rss = table->hft_using_rss;
*erpp = table->eft_default_rxq;
*using_rss = table->eft_using_rss;
}
void
hunt_filter_default_rxq_set(
ef10_filter_default_rxq_set(
__in efx_nic_t *enp,
__in efx_rxq_t *erp,
__in boolean_t using_rss)
{
hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table;
#if EFSYS_OPT_RX_SCALE
EFSYS_ASSERT((using_rss == B_FALSE) ||
(enp->en_rss_context != EF10_RSS_CONTEXT_INVALID));
table->hft_using_rss = using_rss;
table->eft_using_rss = using_rss;
#else
EFSYS_ASSERT(using_rss == B_FALSE);
table->hft_using_rss = B_FALSE;
table->eft_using_rss = B_FALSE;
#endif
table->hft_default_rxq = erp;
table->eft_default_rxq = erp;
}
void
hunt_filter_default_rxq_clear(
ef10_filter_default_rxq_clear(
__in efx_nic_t *enp)
{
hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table;
ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table;
table->hft_default_rxq = NULL;
table->hft_using_rss = B_FALSE;
table->eft_default_rxq = NULL;
table->eft_using_rss = B_FALSE;
}

99
sys/dev/sfxge/common/hunt_impl.h
View File

@ -139,6 +139,21 @@ ef10_intr_trigger(
__in efx_nic_t *enp,
__in unsigned int level);
void
ef10_intr_status_line(
__in efx_nic_t *enp,
__out boolean_t *fatalp,
__out uint32_t *qmaskp);
void
ef10_intr_status_message(
__in efx_nic_t *enp,
__in unsigned int message,
__out boolean_t *fatalp);
void
ef10_intr_fatal(
__in efx_nic_t *enp);
void
ef10_intr_fini(
__in efx_nic_t *enp);
@ -346,18 +361,18 @@ ef10_nvram_partn_write_segment_tlv(
extern __checkReturn efx_rc_t
ef10_nvram_partn_size(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__out size_t *sizep);
extern __checkReturn efx_rc_t
ef10_nvram_partn_lock(
__in efx_nic_t *enp,
__in unsigned int partn);
__in uint32_t partn);
extern __checkReturn efx_rc_t
ef10_nvram_partn_read(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size);
@ -365,14 +380,14 @@ ef10_nvram_partn_read(
extern __checkReturn efx_rc_t
ef10_nvram_partn_erase(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__in size_t size);
extern __checkReturn efx_rc_t
ef10_nvram_partn_write(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size);
@ -380,7 +395,7 @@ ef10_nvram_partn_write(
extern void
ef10_nvram_partn_unlock(
__in efx_nic_t *enp,
__in unsigned int partn);
__in uint32_t partn);
#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
@ -442,7 +457,7 @@ ef10_nvram_rw_finish(
extern __checkReturn efx_rc_t
ef10_nvram_partn_set_version(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in_ecount(4) uint16_t version[4]);
extern __checkReturn efx_rc_t
@ -914,71 +929,75 @@ ef10_rx_fini(
#if EFSYS_OPT_FILTER
typedef struct hunt_filter_handle_s {
uint32_t hfh_lo;
uint32_t hfh_hi;
} hunt_filter_handle_t;
typedef struct ef10_filter_handle_s {
uint32_t efh_lo;
uint32_t efh_hi;
} ef10_filter_handle_t;
typedef struct hunt_filter_entry_s {
uintptr_t hfe_spec; /* pointer to filter spec plus busy bit */
hunt_filter_handle_t hfe_handle;
} hunt_filter_entry_t;
typedef struct ef10_filter_entry_s {
uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
ef10_filter_handle_t efe_handle;
} ef10_filter_entry_t;
/*
* BUSY flag indicates that an update is in progress.
* AUTO_OLD flag is used to mark and sweep MAC packet filters.
*/
#define EFX_HUNT_FILTER_FLAG_BUSY 1U
#define EFX_HUNT_FILTER_FLAG_AUTO_OLD 2U
#define EFX_HUNT_FILTER_FLAGS 3U
#define EFX_EF10_FILTER_FLAG_BUSY 1U
#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
#define EFX_EF10_FILTER_FLAGS 3U
#define EFX_HUNT_FILTER_TBL_ROWS 8192
/*
* Size of the hash table used by the driver. Doesn't need to be the
* same size as the hardware's table.
*/
#define EFX_EF10_FILTER_TBL_ROWS 8192
/* Allow for the broadcast address to be added to the multicast list */
#define EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
typedef struct hunt_filter_table_s {
hunt_filter_entry_t hft_entry[EFX_HUNT_FILTER_TBL_ROWS];
efx_rxq_t * hft_default_rxq;
boolean_t hft_using_rss;
uint32_t hft_unicst_filter_index;
boolean_t hft_unicst_filter_set;
uint32_t hft_mulcst_filter_indexes[
EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX];
uint32_t hft_mulcst_filter_count;
} hunt_filter_table_t;
typedef struct ef10_filter_table_s {
ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
efx_rxq_t * eft_default_rxq;
boolean_t eft_using_rss;
uint32_t eft_unicst_filter_index;
boolean_t eft_unicst_filter_set;
uint32_t eft_mulcst_filter_indexes[
EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
uint32_t eft_mulcst_filter_count;
} ef10_filter_table_t;
__checkReturn efx_rc_t
hunt_filter_init(
ef10_filter_init(
__in efx_nic_t *enp);
void
hunt_filter_fini(
ef10_filter_fini(
__in efx_nic_t *enp);
__checkReturn efx_rc_t
hunt_filter_restore(
ef10_filter_restore(
__in efx_nic_t *enp);
__checkReturn efx_rc_t
hunt_filter_add(
ef10_filter_add(
__in efx_nic_t *enp,
__inout efx_filter_spec_t *spec,
__in boolean_t may_replace);
__checkReturn efx_rc_t
hunt_filter_delete(
ef10_filter_delete(
__in efx_nic_t *enp,
__inout efx_filter_spec_t *spec);
extern __checkReturn efx_rc_t
hunt_filter_supported_filters(
ef10_filter_supported_filters(
__in efx_nic_t *enp,
__out uint32_t *list,
__out size_t *length);
extern __checkReturn efx_rc_t
hunt_filter_reconfigure(
ef10_filter_reconfigure(
__in efx_nic_t *enp,
__in_ecount(6) uint8_t const *mac_addr,
__in boolean_t all_unicst,
@ -989,19 +1008,19 @@ hunt_filter_reconfigure(
__in int count);
extern void
hunt_filter_get_default_rxq(
ef10_filter_get_default_rxq(
__in efx_nic_t *enp,
__out efx_rxq_t **erpp,
__out boolean_t *using_rss);
extern void
hunt_filter_default_rxq_set(
ef10_filter_default_rxq_set(
__in efx_nic_t *enp,
__in efx_rxq_t *erp,
__in boolean_t using_rss);
extern void
hunt_filter_default_rxq_clear(
ef10_filter_default_rxq_clear(
__in efx_nic_t *enp);

42
sys/dev/sfxge/common/hunt_intr.c
View File

@ -148,6 +148,48 @@ ef10_intr_trigger(
return (rc);
}
void
ef10_intr_status_line(
__in efx_nic_t *enp,
__out boolean_t *fatalp,
__out uint32_t *qmaskp)
{
efx_dword_t dword;
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
/* Read the queue mask and implicitly acknowledge the interrupt. */
EFX_BAR_READD(enp, ER_DZ_BIU_INT_ISR_REG, &dword, B_FALSE);
*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
*fatalp = B_FALSE;
}
void
ef10_intr_status_message(
__in efx_nic_t *enp,
__in unsigned int message,
__out boolean_t *fatalp)
{
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
_NOTE(ARGUNUSED(enp, message))
/* EF10 fatal errors are reported via events */
*fatalp = B_FALSE;
}
void
ef10_intr_fatal(
__in efx_nic_t *enp)
{
/* EF10 fatal errors are reported via events */
_NOTE(ARGUNUSED(enp))
}
void
ef10_intr_fini(

8
sys/dev/sfxge/common/hunt_mac.c
View File

@ -281,9 +281,9 @@ hunt_mac_filter_default_rxq_set(
boolean_t old_using_rss;
efx_rc_t rc;
hunt_filter_get_default_rxq(enp, &old_rxq, &old_using_rss);
ef10_filter_get_default_rxq(enp, &old_rxq, &old_using_rss);
hunt_filter_default_rxq_set(enp, erp, using_rss);
ef10_filter_default_rxq_set(enp, erp, using_rss);
rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
epp->ep_all_unicst, epp->ep_mulcst,
@ -299,7 +299,7 @@ hunt_mac_filter_default_rxq_set(
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
hunt_filter_default_rxq_set(enp, old_rxq, old_using_rss);
ef10_filter_default_rxq_set(enp, old_rxq, old_using_rss);
return (rc);
}
@ -310,7 +310,7 @@ hunt_mac_filter_default_rxq_clear(
{
efx_port_t *epp = &(enp->en_port);
hunt_filter_default_rxq_clear(enp);
ef10_filter_default_rxq_clear(enp);
efx_filter_reconfigure(enp, epp->ep_mac_addr,
epp->ep_all_unicst, epp->ep_mulcst,

8
sys/dev/sfxge/common/hunt_mcdi.c
View File

@ -81,6 +81,7 @@ ef10_mcdi_init(
__in efx_nic_t *enp,
__in const efx_mcdi_transport_t *emtp)
{
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efsys_mem_t *esmp = emtp->emt_dma_mem;
efx_dword_t dword;
efx_rc_t rc;
@ -89,6 +90,13 @@ ef10_mcdi_init(
enp->en_family == EFX_FAMILY_MEDFORD);
EFSYS_ASSERT(enp->en_features & EFX_FEATURE_MCDI_DMA);
/*
* All EF10 firmware supports MCDIv2 and MCDIv1.
* Medford BootROM supports MCDIv2 and MCDIv1.
* Huntington BootROM supports MCDIv1 only.
*/
emip->emi_max_version = 2;
/* A host DMA buffer is required for EF10 MCDI */
if (esmp == NULL) {
rc = EINVAL;

111
sys/dev/sfxge/common/hunt_nvram.c
View File

@ -1288,7 +1288,7 @@ ef10_nvram_partn_write_segment_tlv(
__checkReturn efx_rc_t
ef10_nvram_partn_size(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__out size_t *sizep)
{
efx_rc_t rc;
@ -1308,7 +1308,7 @@ ef10_nvram_partn_size(
__checkReturn efx_rc_t
ef10_nvram_partn_lock(
__in efx_nic_t *enp,
__in unsigned int partn)
__in uint32_t partn)
{
efx_rc_t rc;
@ -1326,7 +1326,7 @@ ef10_nvram_partn_lock(
__checkReturn efx_rc_t
ef10_nvram_partn_read(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size)
@ -1358,7 +1358,7 @@ ef10_nvram_partn_read(
__checkReturn efx_rc_t
ef10_nvram_partn_erase(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__in size_t size)
{
@ -1403,7 +1403,7 @@ ef10_nvram_partn_erase(
__checkReturn efx_rc_t
ef10_nvram_partn_write(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size)
@ -1457,7 +1457,7 @@ ef10_nvram_partn_write(
void
ef10_nvram_partn_unlock(
__in efx_nic_t *enp,
__in unsigned int partn)
__in uint32_t partn)
{
boolean_t reboot;
efx_rc_t rc;
@ -1475,7 +1475,7 @@ ef10_nvram_partn_unlock(
__checkReturn efx_rc_t
ef10_nvram_partn_set_version(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in_ecount(4) uint16_t version[4])
{
struct tlv_partition_version partn_version;
@ -1509,8 +1509,6 @@ ef10_nvram_partn_set_version(
#if EFSYS_OPT_NVRAM
/* FIXME: Update partition table for Medford */
typedef struct ef10_parttbl_entry_s {
unsigned int partn;
unsigned int port;
@ -1518,7 +1516,7 @@ typedef struct ef10_parttbl_entry_s {
} ef10_parttbl_entry_t;
/* Translate EFX NVRAM types to firmware partition types */
static ef10_parttbl_entry_t ef10_parttbl[] = {
static ef10_parttbl_entry_t hunt_parttbl[] = {
{NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE},
@ -1549,6 +1547,37 @@ static ef10_parttbl_entry_t ef10_parttbl[] = {
{NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP}
};
static ef10_parttbl_entry_t medford_parttbl[] = {
{NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE, 4, EFX_NVRAM_MC_FIRMWARE},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 1, EFX_NVRAM_MC_GOLDEN},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 2, EFX_NVRAM_MC_GOLDEN},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 3, EFX_NVRAM_MC_GOLDEN},
{NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 4, EFX_NVRAM_MC_GOLDEN},
{NVRAM_PARTITION_TYPE_EXPANSION_ROM, 1, EFX_NVRAM_BOOTROM},
{NVRAM_PARTITION_TYPE_EXPANSION_ROM, 2, EFX_NVRAM_BOOTROM},
{NVRAM_PARTITION_TYPE_EXPANSION_ROM, 3, EFX_NVRAM_BOOTROM},
{NVRAM_PARTITION_TYPE_EXPANSION_ROM, 4, EFX_NVRAM_BOOTROM},
{NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG},
{NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 2, EFX_NVRAM_BOOTROM_CFG},
{NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 3, EFX_NVRAM_BOOTROM_CFG},
{NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 4, EFX_NVRAM_BOOTROM_CFG},
{NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 1, EFX_NVRAM_DYNAMIC_CFG},
{NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 2, EFX_NVRAM_DYNAMIC_CFG},
{NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 3, EFX_NVRAM_DYNAMIC_CFG},
{NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG},
{NVRAM_PARTITION_TYPE_FPGA, 1, EFX_NVRAM_FPGA},
{NVRAM_PARTITION_TYPE_FPGA, 2, EFX_NVRAM_FPGA},
{NVRAM_PARTITION_TYPE_FPGA, 3, EFX_NVRAM_FPGA},
{NVRAM_PARTITION_TYPE_FPGA, 4, EFX_NVRAM_FPGA},
{NVRAM_PARTITION_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP},
{NVRAM_PARTITION_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP},
{NVRAM_PARTITION_TYPE_FPGA_BACKUP, 3, EFX_NVRAM_FPGA_BACKUP},
{NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP}
};
static __checkReturn ef10_parttbl_entry_t *
ef10_parttbl_entry(
__in efx_nic_t *enp,
@ -1556,17 +1585,39 @@ ef10_parttbl_entry(
{
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
ef10_parttbl_entry_t *entry;
int i;
ef10_parttbl_entry_t *parttbl;
size_t parttbl_size = 0;
unsigned int i;
EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES);
for (i = 0; i < EFX_ARRAY_SIZE(ef10_parttbl); i++) {
entry = &ef10_parttbl[i];
switch (enp->en_family) {
case EFX_FAMILY_HUNTINGTON:
parttbl = hunt_parttbl;
parttbl_size = EFX_ARRAY_SIZE(hunt_parttbl);
break;
if (entry->port == emip->emi_port && entry->nvtype == type)
return (entry);
case EFX_FAMILY_MEDFORD:
parttbl = medford_parttbl;
parttbl_size = EFX_ARRAY_SIZE(medford_parttbl);
break;
default:
EFSYS_ASSERT(B_FALSE);
goto not_found;
}
if (parttbl != NULL) {
for (i = 0; i < parttbl_size; i++) {
entry = &parttbl[i];
if (entry->port == emip->emi_port &&
entry->nvtype == type) {
return (entry);
}
}
}
not_found:
return (NULL);
}
@ -1579,10 +1630,12 @@ ef10_nvram_test(
{
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
ef10_parttbl_entry_t *entry;
ef10_parttbl_entry_t *parttbl;
size_t parttbl_size = 0;
unsigned int npartns = 0;
uint32_t *partns = NULL;
size_t size;
int i;
unsigned int i;
unsigned int j;
efx_rc_t rc;
@ -1603,8 +1656,24 @@ ef10_nvram_test(
* Iterate over the list of supported partition types
* applicable to *this* port
*/
for (i = 0; i < EFX_ARRAY_SIZE(ef10_parttbl); i++) {
entry = &ef10_parttbl[i];
switch (enp->en_family) {
case EFX_FAMILY_HUNTINGTON:
parttbl = hunt_parttbl;
parttbl_size = EFX_ARRAY_SIZE(hunt_parttbl);
break;
case EFX_FAMILY_MEDFORD:
parttbl = medford_parttbl;
parttbl_size = EFX_ARRAY_SIZE(medford_parttbl);
break;
default:
EFSYS_ASSERT(B_FALSE);
goto fail3;
}
for (i = 0; i < parttbl_size; i++) {
entry = &parttbl[i];
if (entry->port != emip->emi_port)
continue;
@ -1613,7 +1682,7 @@ ef10_nvram_test(
if (entry->partn == partns[j]) {
rc = efx_mcdi_nvram_test(enp, entry->partn);
if (rc != 0)
goto fail3;
goto fail4;
}
}
}
@ -1621,6 +1690,8 @@ ef10_nvram_test(
EFSYS_KMEM_FREE(enp->en_esip, size, partns);
return (0);
fail4:
EFSYS_PROBE(fail3);
fail3:
EFSYS_PROBE(fail3);
fail2:
@ -1840,7 +1911,7 @@ ef10_nvram_set_version(
__in_ecount(4) uint16_t version[4])
{
ef10_parttbl_entry_t *entry;
unsigned int partn;
uint32_t partn;
efx_rc_t rc;
if ((entry = ef10_parttbl_entry(enp, type)) == NULL) {

43
sys/dev/sfxge/common/hunt_rx.c
View File

@ -147,14 +147,34 @@ efx_mcdi_fini_rxq(
static __checkReturn efx_rc_t
efx_mcdi_rss_context_alloc(
__in efx_nic_t *enp,
__in efx_rx_scale_support_t scale_support,
__in uint32_t num_queues,
__out uint32_t *rss_contextp)
{
efx_mcdi_req_t req;
uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)];
uint32_t rss_context;
uint32_t context_type;
efx_rc_t rc;
if (num_queues > EFX_MAXRSS) {
rc = EINVAL;
goto fail1;
}
switch (scale_support) {
case EFX_RX_SCALE_EXCLUSIVE:
context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
break;
case EFX_RX_SCALE_SHARED:
context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
break;
default:
rc = EINVAL;
goto fail2;
}
(void) memset(payload, 0, sizeof (payload));
req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
req.emr_in_buf = payload;
@ -164,33 +184,36 @@ efx_mcdi_rss_context_alloc(
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
EVB_PORT_ID_ASSIGNED);
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE,
MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
/* NUM_QUEUES is only used to validate indirection table offsets */
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, 64);
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
efx_mcdi_execute(enp, &req);
if (req.emr_rc != 0) {
rc = req.emr_rc;
goto fail1;
goto fail3;
}
if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
rc = EMSGSIZE;
goto fail2;
goto fail4;
}
rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
if (rss_context == EF10_RSS_CONTEXT_INVALID) {
rc = ENOENT;
goto fail3;
goto fail5;
}
*rss_contextp = rss_context;
return (0);
fail5:
EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
fail3:
EFSYS_PROBE(fail3);
fail2:
@ -420,7 +443,8 @@ ef10_rx_init(
{
#if EFSYS_OPT_RX_SCALE
if (efx_mcdi_rss_context_alloc(enp, &enp->en_rss_context) == 0) {
if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
&enp->en_rss_context) == 0) {
/*
* Allocated an exclusive RSS context, which allows both the
* indirection table and key to be modified.
@ -715,11 +739,6 @@ ef10_rx_qcreate(
disable_scatter = B_FALSE;
}
/*
* Note: EFX_RXQ_TYPE_SPLIT_HEADER and EFX_RXQ_TYPE_SPLIT_PAYLOAD are
* not supported here.
*/
if ((rc = efx_mcdi_init_rxq(enp, n, eep->ee_index, label, index,
esmp, disable_scatter)) != 0)
goto fail3;

7
sys/dev/sfxge/common/mcdi_mon.c
View File

@ -149,6 +149,13 @@ static const struct mcdi_sensor_map_s {
STAT(Px, CONTROLLER_SLAVE_VPTAT_EXT_ADC), /* 0x46 SLAVE_VPTAT_EXT_ADC */
STAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC),
/* 0x47 SLAVE_INTERNAL_TEMP_EXT_ADC */
STAT_NO_SENSOR(), /* 0x48 (no sensor) */
STAT(Px, SODIMM_VOUT), /* 0x49 SODIMM_VOUT */
STAT(Px, SODIMM_0_TEMP), /* 0x4a SODIMM_0_TEMP */
STAT(Px, SODIMM_1_TEMP), /* 0x4b SODIMM_1_TEMP */
STAT(Px, PHY0_VCC), /* 0x4c PHY0_VCC */
STAT(Px, PHY1_VCC), /* 0x4d PHY1_VCC */
STAT(Px, CONTROLLER_TDIODE_TEMP), /* 0x4e CONTROLLER_TDIODE_TEMP */
};
#define MCDI_STATIC_SENSOR_ASSERT(_field) \

13
sys/dev/sfxge/common/siena_flash.h
View File

@ -91,6 +91,19 @@ typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */
#define BLOB_CPU_TYPE_RXDI_VTBL1 (14)
#define BLOB_CPU_TYPE_TXDI_VTBL1 (15)
#define BLOB_CPU_TYPE_DUMPSPEC (32)
#define BLOB_CPU_TYPE_MC_XIP (33)
#define BLOB_CPU_TYPE_INVALID (31)
/*
* The upper four bits of the CPU type field specify the compression
* algorithm used for this blob.
*/
#define BLOB_COMPRESSION_MASK (0xf0000000)
#define BLOB_CPU_TYPE_MASK (0x0fffffff)
#define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */
#define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */
typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */
efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */

16
sys/dev/sfxge/common/siena_impl.h
View File

@ -158,18 +158,18 @@ siena_mcdi_feature_supported(
extern __checkReturn efx_rc_t
siena_nvram_partn_size(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__out size_t *sizep);
extern __checkReturn efx_rc_t
siena_nvram_partn_lock(
__in efx_nic_t *enp,
__in unsigned int partn);
__in uint32_t partn);
extern __checkReturn efx_rc_t
siena_nvram_partn_read(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size);
@ -177,14 +177,14 @@ siena_nvram_partn_read(
extern __checkReturn efx_rc_t
siena_nvram_partn_erase(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__in size_t size);
extern __checkReturn efx_rc_t
siena_nvram_partn_write(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size);
@ -192,12 +192,12 @@ siena_nvram_partn_write(
extern void
siena_nvram_partn_unlock(
__in efx_nic_t *enp,
__in unsigned int partn);
__in uint32_t partn);
extern __checkReturn efx_rc_t
siena_nvram_get_dynamic_cfg(
__in efx_nic_t *enp,
__in unsigned int index,
__in uint32_t partn,
__in boolean_t vpd,
__out siena_mc_dynamic_config_hdr_t **dcfgp,
__out size_t *sizep);
@ -223,7 +223,7 @@ siena_nvram_size(
extern __checkReturn efx_rc_t
siena_nvram_get_subtype(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__out uint32_t *subtypep);
extern __checkReturn efx_rc_t

3
sys/dev/sfxge/common/siena_mcdi.c
View File

@ -244,6 +244,9 @@ siena_mcdi_init(
goto fail1;
}
/* Siena BootROM and firmware only support MCDIv1 */
emip->emi_max_version = 1;
/*
* Wipe the atomic reboot status so subsequent MCDI requests succeed.
* BOOT_STATUS is preserved so eno_nic_probe() can boot out of the

20
sys/dev/sfxge/common/siena_nvram.c
View File

@ -44,7 +44,7 @@ __FBSDID("$FreeBSD$");
__checkReturn efx_rc_t
siena_nvram_partn_size(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__out size_t *sizep)
{
efx_rc_t rc;
@ -72,7 +72,7 @@ siena_nvram_partn_size(
__checkReturn efx_rc_t
siena_nvram_partn_lock(
__in efx_nic_t *enp,
__in unsigned int partn)
__in uint32_t partn)
{
efx_rc_t rc;
@ -91,7 +91,7 @@ siena_nvram_partn_lock(
__checkReturn efx_rc_t
siena_nvram_partn_read(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size)
@ -123,7 +123,7 @@ siena_nvram_partn_read(
__checkReturn efx_rc_t
siena_nvram_partn_erase(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__in size_t size)
{
@ -144,7 +144,7 @@ siena_nvram_partn_erase(
__checkReturn efx_rc_t
siena_nvram_partn_write(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in unsigned int offset,
__out_bcount(size) caddr_t data,
__in size_t size)
@ -176,7 +176,7 @@ siena_nvram_partn_write(
void
siena_nvram_partn_unlock(
__in efx_nic_t *enp,
__in unsigned int partn)
__in uint32_t partn)
{
boolean_t reboot;
efx_rc_t rc;
@ -326,7 +326,7 @@ siena_nvram_size(
__checkReturn efx_rc_t
siena_nvram_get_dynamic_cfg(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__in boolean_t vpd,
__out siena_mc_dynamic_config_hdr_t **dcfgp,
__out size_t *sizep)
@ -455,7 +455,7 @@ siena_nvram_get_dynamic_cfg(
__checkReturn efx_rc_t
siena_nvram_get_subtype(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__out uint32_t *subtypep)
{
efx_mcdi_req_t req;
@ -515,8 +515,8 @@ siena_nvram_get_version(
{
siena_mc_dynamic_config_hdr_t *dcfg;
siena_parttbl_entry_t *entry;
unsigned int dcfg_partn;
unsigned int partn;
uint32_t dcfg_partn;
uint32_t partn;
unsigned int i;
efx_rc_t rc;

4
sys/dev/sfxge/common/siena_vpd.c
View File

@ -44,7 +44,7 @@ __FBSDID("$FreeBSD$");
static __checkReturn efx_rc_t
siena_vpd_get_static(
__in efx_nic_t *enp,
__in unsigned int partn,
__in uint32_t partn,
__deref_out_bcount_opt(*sizep) caddr_t *svpdp,
__out size_t *sizep)
{
@ -207,7 +207,7 @@ siena_vpd_size(
__out size_t *sizep)
{
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
unsigned int partn;
uint32_t partn;
efx_rc_t rc;
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);

1
sys/dev/uart/uart_bus.h
View File

@ -113,6 +113,7 @@ struct uart_softc {
/* Pulse capturing support (PPS). */
struct pps_state sc_pps;
int sc_pps_mode;
sbintime_t sc_pps_captime;
/* Upper layer data. */
void *sc_softih;

143
sys/dev/uart/uart_core.c
View File

@ -48,6 +48,7 @@ __FBSDID("$FreeBSD$");
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
#include <dev/uart/uart_ppstypes.h>
#include "uart_if.h"
@ -70,47 +71,47 @@ static int uart_force_poll;
SYSCTL_INT(_debug, OID_AUTO, uart_force_poll, CTLFLAG_RDTUN, &uart_force_poll,
0, "Force UART polling");
#define PPS_MODE_DISABLED 0
#define PPS_MODE_CTS 1
#define PPS_MODE_DCD 2
static inline int
uart_pps_signal(int pps_mode)
{
switch(pps_mode) {
case PPS_MODE_CTS:
return (SER_CTS);
case PPS_MODE_DCD:
return (SER_DCD);
}
return (0);
}
static inline int
uart_pps_mode_valid(int pps_mode)
{
int opt;
switch(pps_mode) {
case PPS_MODE_DISABLED:
case PPS_MODE_CTS:
case PPS_MODE_DCD:
return (true);
switch(pps_mode & UART_PPS_SIGNAL_MASK) {
case UART_PPS_DISABLED:
case UART_PPS_CTS:
case UART_PPS_DCD:
break;
default:
return (false);
}
return (false);
opt = pps_mode & UART_PPS_OPTION_MASK;
if ((opt & ~(UART_PPS_INVERT_PULSE | UART_PPS_NARROW_PULSE)) != 0)
return (false);
return (true);
}
static const char *
uart_pps_mode_name(int pps_mode)
static void
uart_pps_print_mode(struct uart_softc *sc)
{
switch(pps_mode) {
case PPS_MODE_DISABLED:
return ("disabled");
case PPS_MODE_CTS:
return ("CTS");
case PPS_MODE_DCD:
return ("DCD");
device_printf(sc->sc_dev, "PPS capture mode: ");
switch(sc->sc_pps_mode) {
case UART_PPS_DISABLED:
printf("disabled");
case UART_PPS_CTS:
printf("CTS");
case UART_PPS_DCD:
printf("DCD");
default:
printf("invalid");
}
return ("invalid");
if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE)
printf("-Inverted");
if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE)
printf("-NarrowPulse");
printf("\n");
}
static int
@ -130,6 +131,55 @@ uart_pps_mode_sysctl(SYSCTL_HANDLER_ARGS)
return(0);
}
static void
uart_pps_process(struct uart_softc *sc, int ser_sig)
{
sbintime_t now;
int is_assert, pps_sig;
/* Which signal is configured as PPS? Early out if none. */
switch(sc->sc_pps_mode & UART_PPS_SIGNAL_MASK) {
case UART_PPS_CTS:
pps_sig = SER_CTS;
break;
case UART_PPS_DCD:
pps_sig = SER_DCD;
break;
default:
return;
}
/* Early out if there is no change in the signal configured as PPS. */
if ((ser_sig & SER_DELTA(pps_sig)) == 0)
return;
/*
* In narrow-pulse mode we need to synthesize both capture and clear
* events from a single "delta occurred" indication from the uart
* hardware because the pulse width is too narrow to reliably detect
* both edges. However, when the pulse width is close to our interrupt
* processing latency we might intermittantly catch both edges. To
* guard against generating spurious events when that happens, we use a
* separate timer to ensure at least half a second elapses before we
* generate another event.
*/
pps_capture(&sc->sc_pps);
if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
now = getsbinuptime();
if (now > sc->sc_pps_captime + 500 * SBT_1MS) {
sc->sc_pps_captime = now;
pps_event(&sc->sc_pps, PPS_CAPTUREASSERT);
pps_event(&sc->sc_pps, PPS_CAPTURECLEAR);
}
} else {
is_assert = ser_sig & pps_sig;
if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE)
is_assert = !is_assert;
pps_event(&sc->sc_pps, is_assert ? PPS_CAPTUREASSERT :
PPS_CAPTURECLEAR);
}
}
static void
uart_pps_init(struct uart_softc *sc)
{
@ -147,23 +197,23 @@ uart_pps_init(struct uart_softc *sc)
* for one specific device.
*/
#ifdef UART_PPS_ON_CTS
sc->sc_pps_mode = PPS_MODE_CTS;
sc->sc_pps_mode = UART_PPS_CTS;
#else
sc->sc_pps_mode = PPS_MODE_DCD;
sc->sc_pps_mode = UART_PPS_DCD;
#endif
TUNABLE_INT_FETCH("hw.uart.pps_mode", &sc->sc_pps_mode);
SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "pps_mode",
CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0, uart_pps_mode_sysctl, "I",
"pulse capturing mode - 0/1/2 - disabled/CTS/DCD");
"pulse mode: 0/1/2=disabled/CTS/DCD; "
"add 0x10 to invert, 0x20 for narrow pulse");
if (!uart_pps_mode_valid(sc->sc_pps_mode)) {
device_printf(sc->sc_dev,
"Invalid pps_mode %d configured; disabling PPS capture\n",
"Invalid pps_mode 0x%02x configured; disabling PPS capture\n",
sc->sc_pps_mode);
sc->sc_pps_mode = PPS_MODE_DISABLED;
sc->sc_pps_mode = UART_PPS_DISABLED;
} else if (bootverbose) {
device_printf(sc->sc_dev, "PPS capture mode %d (%s)\n",
sc->sc_pps_mode, uart_pps_mode_name(sc->sc_pps_mode));
uart_pps_print_mode(sc);
}
sc->sc_pps.ppscap = PPS_CAPTUREBOTH;
@ -313,23 +363,16 @@ static __inline int
uart_intr_sigchg(void *arg)
{
struct uart_softc *sc = arg;
int new, old, pps_sig, sig;
int new, old, sig;
sig = UART_GETSIG(sc);
/*
* Time pulse counting support. Note that both CTS and DCD are
* active-low signals. The status bit is high to indicate that
* the signal on the line is low, which corresponds to a PPS
* clear event.
* Time pulse counting support, invoked whenever the PPS parameters are
* currently set to capture either edge of the signal.
*/
if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) {
pps_sig = uart_pps_signal(sc->sc_pps_mode);
if (sig & SER_DELTA(pps_sig)) {
pps_capture(&sc->sc_pps);
pps_event(&sc->sc_pps, (sig & pps_sig) ?
PPS_CAPTURECLEAR : PPS_CAPTUREASSERT);
}
uart_pps_process(sc, sig);
}
/*

76
sys/dev/uart/uart_dev_ns8250.c
View File

@ -51,6 +51,7 @@ __FBSDID("$FreeBSD$");
#endif
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_dev_ns8250.h>
#include <dev/uart/uart_ppstypes.h>
#include <dev/ic/ns16550.h>
@ -401,11 +402,40 @@ static struct ofw_compat_data compat_data[] = {
UART_FDT_CLASS_AND_DEVICE(compat_data);
#endif
#define SIGCHG(c, i, s, d) \
if (c) { \
i |= (i & s) ? s : s | d; \
} else { \
i = (i & s) ? (i & ~s) | d : i; \
/* Use token-pasting to form SER_ and MSR_ named constants. */
#define SER(sig) SER_##sig
#define SERD(sig) SER_D##sig
#define MSR(sig) MSR_##sig
#define MSRD(sig) MSR_D##sig
/*
* Detect signal changes using software delta detection. The previous state of
* the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
* short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
* new state of both the signal and the delta bits.
*/
#define SIGCHGSW(var, msr, sig) \
if ((msr) & MSR(sig)) { \
if ((var & SER(sig)) == 0) \
var |= SERD(sig) | SER(sig); \
} else { \
if ((var & SER(sig)) != 0) \
var = SERD(sig) | (var & ~SER(sig)); \
}
/*
* Detect signal changes using the hardware msr delta bits. This is currently
* used only when PPS timing information is being captured using the "narrow
* pulse" option. With a narrow PPS pulse the signal may not still be asserted
* by time the interrupt handler is invoked. The hardware will latch the fact
* that it changed in the delta bits.
*/
#define SIGCHGHW(var, msr, sig) \
if ((msr) & MSRD(sig)) { \
if (((msr) & MSR(sig)) != 0) \
var |= SERD(sig) | SER(sig); \
else \
var = SERD(sig) | (var & ~SER(sig)); \
}
int
@ -532,21 +562,37 @@ ns8250_bus_flush(struct uart_softc *sc, int what)
int
ns8250_bus_getsig(struct uart_softc *sc)
{
uint32_t new, old, sig;
uint32_t old, sig;
uint8_t msr;
/*
* The delta bits are reputed to be broken on some hardware, so use
* software delta detection by default. Use the hardware delta bits
* when capturing PPS pulses which are too narrow for software detection
* to see the edges. Hardware delta for RI doesn't work like the
* others, so always use software for it. Other threads may be changing
* other (non-MSR) bits in sc_hwsig, so loop until it can succesfully
* update without other changes happening. Note that the SIGCHGxx()
* macros carefully preserve the delta bits when we have to loop several
* times and a signal transitions between iterations.
*/
do {
old = sc->sc_hwsig;
sig = old;
uart_lock(sc->sc_hwmtx);
msr = uart_getreg(&sc->sc_bas, REG_MSR);
uart_unlock(sc->sc_hwmtx);
SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
new = sig & ~SER_MASK_DELTA;
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
SIGCHGHW(sig, msr, DSR);
SIGCHGHW(sig, msr, CTS);
SIGCHGHW(sig, msr, DCD);
} else {
SIGCHGSW(sig, msr, DSR);
SIGCHGSW(sig, msr, CTS);
SIGCHGSW(sig, msr, DCD);
}
SIGCHGSW(sig, msr, RI);
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
return (sig);
}
@ -900,12 +946,10 @@ ns8250_bus_setsig(struct uart_softc *sc, int sig)
old = sc->sc_hwsig;
new = old;
if (sig & SER_DDTR) {
SIGCHG(sig & SER_DTR, new, SER_DTR,
SER_DDTR);
new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
}
if (sig & SER_DRTS) {
SIGCHG(sig & SER_RTS, new, SER_RTS,
SER_DRTS);
new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
}
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
uart_lock(sc->sc_hwmtx);

46
sys/dev/uart/uart_ppstypes.h Normal file
View File

@ -0,0 +1,46 @@
/*-
* Copyright (c) 2015 Ian Lepore
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _DEV_UART_PPSTYPES_H_
#define _DEV_UART_PPSTYPES_H_
/*
* These constants are shared by several drivers including uart and usb_serial.
*/
#define UART_PPS_SIGNAL_MASK 0x0f
#define UART_PPS_OPTION_MASK 0xf0
#define UART_PPS_DISABLED 0x00
#define UART_PPS_CTS 0x01
#define UART_PPS_DCD 0x02
#define UART_PPS_INVERT_PULSE 0x10
#define UART_PPS_NARROW_PULSE 0x20
#endif /* _DEV_UART_PPSTYPES_H_ */

4
usr.sbin/ypldap/yp.c
View File

@ -83,10 +83,10 @@ void
yp_enable_events(void)
{
int i;
extern fd_set svc_fdset;
extern fd_set svc_fdset;
struct yp_event *ye;
for (i = 0; i < getdtablesize(); i++) {
for (i = 0; i < FD_SETSIZE; i++) {
if (FD_ISSET(i, &svc_fdset)) {
if ((ye = calloc(1, sizeof(*ye))) == NULL)
fatal(NULL);

5
usr.sbin/ypldap/ypldap.conf.5
View File

@ -15,7 +15,7 @@
.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
.\"
.Dd $Mdocdate: April 30 2012 $
.Dd $Mdocdate: January 13 2016 $
.Dt YPLDAP.CONF 5
.Os
.Sh NAME
@ -155,6 +155,9 @@ Use the supplied LDAP filter to retrieve password entries.
.It Pa /etc/ypldap.conf
.Xr ypldap 8
configuration file.
.It Pa /usr/share/example/ypldap/ypldap.conf
.Xr ypldap 8
configuration file example.
.El
.Sh SEE ALSO
.Xr ypbind 8 ,