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* Fixed problem where some rev 8013EBT boards want the DCR_LS flag

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* set in order to work in 16bit mode.

   Seems also to improve performance by 15%! (?!) I think there might
be more to this flag than the manual says.
This commit is contained in:
David Greenman 1993-08-02 10:36:05 +00:00
parent 9f12b7bf9a
commit 0d1a37c0f1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=226
2 changed files with 14 additions and 6 deletions
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10
sys/dev/ed/if_ed.c
View File

@ -17,6 +17,10 @@
* Modification history
*
* $Log: if_ed.c,v $
* Revision 1.19 93/08/02 02:57:53 davidg
* Fixed problem where some rev 8013EBT boards want the DCR_LS flag
* set in order to work in 16bit mode.
*
* Revision 1.18 93/07/27 03:41:36 davidg
* removed unnecessary variable assignment in ed_reset()
*
@ -881,14 +885,14 @@ ed_init(unit)
if (sc->memwidth == 16) {
/*
* Set FIFO threshold to 8, No auto-init Remote DMA,
* byte order=80x86, word-wide DMA xfers
* byte order=80x86, word-wide DMA xfers,
*/
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS);
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
} else {
/*
* Same as above, but byte-wide DMA xfers
*/
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1);
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
}
/*

10
sys/i386/isa/if_ed.c
View File

@ -17,6 +17,10 @@
* Modification history
*
* $Log: if_ed.c,v $
* Revision 1.19 93/08/02 02:57:53 davidg
* Fixed problem where some rev 8013EBT boards want the DCR_LS flag
* set in order to work in 16bit mode.
*
* Revision 1.18 93/07/27 03:41:36 davidg
* removed unnecessary variable assignment in ed_reset()
*
@ -881,14 +885,14 @@ ed_init(unit)
if (sc->memwidth == 16) {
/*
* Set FIFO threshold to 8, No auto-init Remote DMA,
* byte order=80x86, word-wide DMA xfers
* byte order=80x86, word-wide DMA xfers,
*/
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS);
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
} else {
/*
* Same as above, but byte-wide DMA xfers
*/
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1);
outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
}
/*