[PowerPC64LE] Fix AP spinup on powernv.

OPAL unconditionally enters secondary CPUs with only HV and SF set.

I tried writing a secondary entry point instead, but OPAL rejected it
and I am unsure why, so I resorted to making the system reset interrupt
endian-flexible.

This means we take a slight performance hit on wakeup on LE, but it is
a good stopgap until we can figure out a reliable way to make OPAL enter
where we want it to.

It probably makes sense to have it around anyway, because I can imagine
scenarios where the cpu resets itself to BE and does a software reset.

Sponsored by:	Tag1 Consulting, Inc.

sys/powerpc/aim/trap_subr64.S

@@ -319,6 +319,19 @@ dtrace_invop_calltrap_addr:
 	.globl	CNAME(cpu_wakeup_handler)
 	.p2align 3
 CNAME(rstcode):
+#ifdef __LITTLE_ENDIAN__
+	/*
+	 * XXX This shouldn't be necessary.
+	 *
+	 * According to the ISA documentation, LE should be set from HILE
+	 * or the LPCR ILE bit automatically. However, the entry into this
+	 * vector from OPAL_START_CPU does not honor this correctly.
+	 *
+	 * We should be able to define an alternate entry for opal's
+	 * start_kernel_secondary asm code to branch to.
+	 */
+	RETURN_TO_NATIVE_ENDIAN
+#endif
 	/*
 	 * Check if this is software reset or
 	 * processor is waking up from power saving mode

sys/powerpc/include/asm.h

@@ -213,6 +213,9 @@ name: \
  * wrong endian.
  *
  * This sequence is NMI-reentrant.
+ *
+ * Do not change the length of this sequence without looking at the users,
+ * this is used in size-constrained places like the reset vector!
  */
 #define	RETURN_TO_NATIVE_ENDIAN						  \
 	tdi	0, %r0, 0x48;	/* Endian swapped: b . + 8		*/\