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esp: Remove

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Belatedly remove esp(4). It was tagged as gone in 13, but was overlooked
until now.

Sponsored by:		Netflix
Reviewed by:		scottl
Differential Revision:	https://reviews.freebsd.org/D33115
This commit is contained in:
Warner Losh 2021-11-25 00:21:24 -07:00
parent 60de2867c9
commit 0d5935af8f
15 changed files with 0 additions and 5017 deletions
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1
share/man/man4/Makefile
View File

@ -142,7 +142,6 @@ MAN= aac.4 \
ena.4 \
enc.4 \
epair.4 \
esp.4 \
est.4 \
et.4 \
etherswitch.4 \

111
share/man/man4/esp.4
View File

@ -1,111 +0,0 @@
.\"
.\" Copyright (c) 2011 Marius Strobl <marius@FreeBSD.org>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd December 26, 2020
.Dt ESP 4
.Os
.Sh NAME
.Nm esp
.Nd Emulex ESP, NCR 53C9x and QLogic FAS families based SCSI controllers
.Sh SYNOPSIS
To compile this driver into the kernel, place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device scbus"
.Cd "device esp"
.Ed
.Pp
Alternatively, to load the driver as a module at boot time, place the
following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
if_esp_load="YES"
.Ed
.Sh DEPRECATION NOTICE
The
.Nm
driver is not present in
.Fx 13.0 .
.Sh DESCRIPTION
The
.Nm
driver provides support for the
.Tn AMD
Am53C974, the
.Tn Emulex
ESP100, ESP100A, ESP200 and ESP406, the
.Tn NCR
53C90, 53C94 and 53C96 as well as the
.Tn QLogic
FAS100A, FAS216, FAS366 and FAS408
.Tn SCSI
controller chips found in a wide variety of systems and peripheral boards.
.Sh HARDWARE
Controllers supported by the
.Nm
driver include:
.Pp
.Bl -bullet -compact
.It
Tekram DC390
.It
Tekram DC390T
.El
.Sh SEE ALSO
.Xr cd 4 ,
.Xr ch 4 ,
.Xr da 4 ,
.Xr intro 4 ,
.Xr pci 4 ,
.Xr sa 4 ,
.Xr scsi 4 ,
.Xr camcontrol 8
.Sh HISTORY
The
.Nm
driver first appeared in
.Nx 1.3 .
The first
.Fx
version to include it was
.Fx 5.3 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was ported to
.Fx
by
.An Scott Long Aq Mt scottl@FreeBSD.org
and later on considerably improved by
.An Marius Strobl Aq Mt marius@FreeBSD.org .
.Sh BUGS
The
.Nm
driver should read the EEPROM settings of
.Tn Tekram
controllers.

1
sys/amd64/conf/GENERIC
View File

@ -157,7 +157,6 @@ device siis # SiliconImage SiI3124/SiI3132/SiI3531 SATA
# SCSI Controllers
device ahc # AHA2940 and onboard AIC7xxx devices
device ahd # AHA39320/29320 and onboard AIC79xx devices
device esp # AMD Am53C974 (Tekram DC-390(T))
device hptiop # Highpoint RocketRaid 3xxx series
device isp # Qlogic family
#device ispfw # Firmware for QLogic HBAs- normally a module

4
sys/conf/NOTES
View File

@ -1522,9 +1522,6 @@ options TERMINAL_KERN_ATTR=(FG_LIGHTRED|BG_BLACK)
# ahc: Adaptec 274x/284x/2910/293x/294x/394x/3950x/3960x/398X/4944/
# 19160x/29160x, aic7770/aic78xx
# ahd: Adaptec 29320/39320 Controllers.
# esp: Emulex ESP, NCR 53C9x and QLogic FAS families based controllers
# including the AMD Am53C974 (found on devices such as the Tekram
# DC-390(T)) and the Sun ESP and FAS families of controllers
# isp: Qlogic ISP 1020, 1040 and 1040B PCI SCSI host adapters,
# ISP 1240 Dual Ultra SCSI, ISP 1080 and 1280 (Dual) Ultra2,
# ISP 12160 Ultra3 SCSI,
@ -1544,7 +1541,6 @@ options TERMINAL_KERN_ATTR=(FG_LIGHTRED|BG_BLACK)
device aacraid
device ahc
device ahd
device esp
device isp
envvar hint.isp.0.disable="1"
envvar hint.isp.0.role="3"

2
sys/conf/files
View File

@ -1680,8 +1680,6 @@ dev/ena/ena_sysctl.c optional ena \
compile-with "${NORMAL_C} -I$S/contrib"
contrib/ena-com/ena_com.c optional ena
contrib/ena-com/ena_eth_com.c optional ena
dev/esp/esp_pci.c optional esp pci
dev/esp/ncr53c9x.c optional esp
dev/etherswitch/arswitch/arswitch.c optional arswitch
dev/etherswitch/arswitch/arswitch_reg.c optional arswitch
dev/etherswitch/arswitch/arswitch_phy.c optional arswitch

74
sys/dev/esp/am53c974reg.h
View File

@ -1,74 +0,0 @@
/* $NetBSD: pcscpreg.h,v 1.2 2008/04/28 20:23:55 martin Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Izumi Tsutsui.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _AM53C974_H_
#define _AM53C974_H_
/*
* Am53c974 DMA engine registers
*/
#define DMA_CMD 0x40 /* Command */
#define DMACMD_RSVD 0xFFFFFF28 /* reserved */
#define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */
#define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */
#define DMACMD_MDL 0x00000010 /* Map to Memory Description List */
#define DMACMD_DIAG 0x00000004 /* Diagnostic */
#define DMACMD_CMD 0x00000003 /* Command Code Bit */
#define DMACMD_IDLE 0x00000000 /* Idle */
#define DMACMD_BLAST 0x00000001 /* Blast */
#define DMACMD_ABORT 0x00000002 /* Abort */
#define DMACMD_START 0x00000003 /* Start */
#define DMA_STC 0x44 /* Start Transfer Count */
#define DMA_SPA 0x48 /* Start Physical Address */
#define DMA_WBC 0x4C /* Working Byte Counter */
#define DMA_WAC 0x50 /* Working Address Counter */
#define DMA_STAT 0x54 /* Status Register */
#define DMASTAT_RSVD 0xFFFFFF80 /* reserved */
#define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */
#define DMASTAT_BCMP 0x00000020 /* BLAST Complete */
#define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */
#define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */
#define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */
#define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */
#define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */
#define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */
#define DMA_WMAC 0x5C /* Working MDL Counter */
#define DMA_SBAC 0x70 /* SCSI Bus and Control */
#endif /* _AM53C974_H_ */

656
sys/dev/esp/esp_pci.c
View File

@ -1,656 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-2-Clause-NetBSD
*
* Copyright (c) 2011 Marius Strobl <marius@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $NetBSD: pcscp.c,v 1.45 2010/11/13 13:52:08 uebayasi Exp $ */
/*-
* Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center; Izumi Tsutsui.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* esp_pci.c: device dependent code for AMD Am53c974 (PCscsi-PCI)
* written by Izumi Tsutsui <tsutsui@NetBSD.org>
*
* Technical manual available at
* http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/scsi/scsi_all.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/esp/ncr53c9xreg.h>
#include <dev/esp/ncr53c9xvar.h>
#include <dev/esp/am53c974reg.h>
#define PCI_DEVICE_ID_AMD53C974 0x20201022
struct esp_pci_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
device_t sc_dev;
struct resource *sc_res[2];
#define ESP_PCI_RES_INTR 0
#define ESP_PCI_RES_IO 1
bus_dma_tag_t sc_pdmat;
bus_dma_tag_t sc_xferdmat; /* DMA tag for transfers */
bus_dmamap_t sc_xferdmam; /* DMA map for transfers */
void *sc_ih; /* interrupt handler */
size_t sc_dmasize; /* DMA size */
void **sc_dmaaddr; /* DMA address */
size_t *sc_dmalen; /* DMA length */
int sc_active; /* DMA state */
int sc_datain; /* DMA Data Direction */
};
static struct resource_spec esp_pci_res_spec[] = {
{ SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* ESP_PCI_RES_INTR */
{ SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, /* ESP_PCI_RES_IO */
{ -1, 0 }
};
#define READ_DMAREG(sc, reg) \
bus_read_4((sc)->sc_res[ESP_PCI_RES_IO], (reg))
#define WRITE_DMAREG(sc, reg, var) \
bus_write_4((sc)->sc_res[ESP_PCI_RES_IO], (reg), (var))
#define READ_ESPREG(sc, reg) \
bus_read_1((sc)->sc_res[ESP_PCI_RES_IO], (reg) << 2)
#define WRITE_ESPREG(sc, reg, val) \
bus_write_1((sc)->sc_res[ESP_PCI_RES_IO], (reg) << 2, (val))
static int esp_pci_probe(device_t);
static int esp_pci_attach(device_t);
static int esp_pci_detach(device_t);
static int esp_pci_suspend(device_t);
static int esp_pci_resume(device_t);
static device_method_t esp_pci_methods[] = {
DEVMETHOD(device_probe, esp_pci_probe),
DEVMETHOD(device_attach, esp_pci_attach),
DEVMETHOD(device_detach, esp_pci_detach),
DEVMETHOD(device_suspend, esp_pci_suspend),
DEVMETHOD(device_resume, esp_pci_resume),
DEVMETHOD_END
};
static driver_t esp_pci_driver = {
"esp",
esp_pci_methods,
sizeof(struct esp_pci_softc)
};
DRIVER_MODULE(esp, pci, esp_pci_driver, esp_devclass, 0, 0);
MODULE_DEPEND(esp, pci, 1, 1, 1);
/*
* Functions and the switch for the MI code
*/
static void esp_pci_dma_go(struct ncr53c9x_softc *);
static int esp_pci_dma_intr(struct ncr53c9x_softc *);
static int esp_pci_dma_isactive(struct ncr53c9x_softc *);
static int esp_pci_dma_isintr(struct ncr53c9x_softc *);
static void esp_pci_dma_reset(struct ncr53c9x_softc *);
static int esp_pci_dma_setup(struct ncr53c9x_softc *, void **, size_t *,
int, size_t *);
static void esp_pci_dma_stop(struct ncr53c9x_softc *);
static void esp_pci_write_reg(struct ncr53c9x_softc *, int, uint8_t);
static uint8_t esp_pci_read_reg(struct ncr53c9x_softc *, int);
static void esp_pci_xfermap(void *arg, bus_dma_segment_t *segs, int nseg,
int error);
static struct ncr53c9x_glue esp_pci_glue = {
esp_pci_read_reg,
esp_pci_write_reg,
esp_pci_dma_isintr,
esp_pci_dma_reset,
esp_pci_dma_intr,
esp_pci_dma_setup,
esp_pci_dma_go,
esp_pci_dma_stop,
esp_pci_dma_isactive,
};
static int
esp_pci_probe(device_t dev)
{
if (pci_get_devid(dev) == PCI_DEVICE_ID_AMD53C974) {
device_set_desc(dev, "AMD Am53C974 Fast-SCSI");
return (BUS_PROBE_DEFAULT);
}
return (ENXIO);
}
/*
* Attach this instance, and then all the sub-devices
*/
static int
esp_pci_attach(device_t dev)
{
struct esp_pci_softc *esc;
struct ncr53c9x_softc *sc;
int error;
esc = device_get_softc(dev);
sc = &esc->sc_ncr53c9x;
NCR_LOCK_INIT(sc);
esc->sc_dev = dev;
sc->sc_glue = &esp_pci_glue;
pci_enable_busmaster(dev);
error = bus_alloc_resources(dev, esp_pci_res_spec, esc->sc_res);
if (error != 0) {
device_printf(dev, "failed to allocate resources\n");
bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
return (error);
}
error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXSIZE_32BIT, BUS_SPACE_UNRESTRICTED,
BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &esc->sc_pdmat);
if (error != 0) {
device_printf(dev, "cannot create parent DMA tag\n");
goto fail_res;
}
/*
* XXX More of this should be in ncr53c9x_attach(), but
* XXX should we really poke around the chip that much in
* XXX the MI code? Think about this more...
*/
/*
* Set up static configuration info.
*
* XXX we should read the configuration from the EEPROM.
*/
sc->sc_id = 7;
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK;
sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE;
sc->sc_rev = NCR_VARIANT_AM53C974;
sc->sc_features = NCR_F_FASTSCSI | NCR_F_DMASELECT;
sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI;
sc->sc_freq = 40; /* MHz */
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
sc->sc_maxxfer = DFLTPHYS; /* see below */
sc->sc_maxoffset = 15;
sc->sc_extended_geom = 1;
#define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */
/*
* Create the DMA tag and map for the data transfers.
*
* Note: given that bus_dma(9) only adheres to the requested alignment
* for the first segment (and that also only for bus_dmamem_alloc()ed
* DMA maps) we can't use the Memory Descriptor List. However, also
* when not using the MDL, the maximum transfer size apparently is
* limited to 4k so we have to split transfers up, which plain sucks.
*/
error = bus_dma_tag_create(esc->sc_pdmat, PAGE_SIZE, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
MDL_SEG_SIZE, 1, MDL_SEG_SIZE, BUS_DMA_ALLOCNOW,
busdma_lock_mutex, &sc->sc_lock, &esc->sc_xferdmat);
if (error != 0) {
device_printf(dev, "cannot create transfer DMA tag\n");
goto fail_pdmat;
}
error = bus_dmamap_create(esc->sc_xferdmat, 0, &esc->sc_xferdmam);
if (error != 0) {
device_printf(dev, "cannot create transfer DMA map\n");
goto fail_xferdmat;
}
error = bus_setup_intr(dev, esc->sc_res[ESP_PCI_RES_INTR],
INTR_MPSAFE | INTR_TYPE_CAM, NULL, ncr53c9x_intr, sc,
&esc->sc_ih);
if (error != 0) {
device_printf(dev, "cannot set up interrupt\n");
goto fail_xferdmam;
}
/* Do the common parts of attachment. */
sc->sc_dev = esc->sc_dev;
error = ncr53c9x_attach(sc);
if (error != 0) {
device_printf(esc->sc_dev, "ncr53c9x_attach failed\n");
goto fail_intr;
}
return (0);
fail_intr:
bus_teardown_intr(esc->sc_dev, esc->sc_res[ESP_PCI_RES_INTR],
esc->sc_ih);
fail_xferdmam:
bus_dmamap_destroy(esc->sc_xferdmat, esc->sc_xferdmam);
fail_xferdmat:
bus_dma_tag_destroy(esc->sc_xferdmat);
fail_pdmat:
bus_dma_tag_destroy(esc->sc_pdmat);
fail_res:
bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
NCR_LOCK_DESTROY(sc);
return (error);
}
static int
esp_pci_detach(device_t dev)
{
struct ncr53c9x_softc *sc;
struct esp_pci_softc *esc;
int error;
esc = device_get_softc(dev);
sc = &esc->sc_ncr53c9x;
bus_teardown_intr(esc->sc_dev, esc->sc_res[ESP_PCI_RES_INTR],
esc->sc_ih);
error = ncr53c9x_detach(sc);
if (error != 0)
return (error);
bus_dmamap_destroy(esc->sc_xferdmat, esc->sc_xferdmam);
bus_dma_tag_destroy(esc->sc_xferdmat);
bus_dma_tag_destroy(esc->sc_pdmat);
bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
NCR_LOCK_DESTROY(sc);
return (0);
}
static int
esp_pci_suspend(device_t dev)
{
return (ENXIO);
}
static int
esp_pci_resume(device_t dev)
{
return (ENXIO);
}
static void
esp_pci_xfermap(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)arg;
if (error != 0)
return;
KASSERT(nsegs == 1, ("%s: bad transfer segment count %d", __func__,
nsegs));
KASSERT(segs[0].ds_len <= MDL_SEG_SIZE,
("%s: bad transfer segment length %ld", __func__,
(long)segs[0].ds_len));
/* Program the DMA Starting Physical Address. */
WRITE_DMAREG(esc, DMA_SPA, segs[0].ds_addr);
}
/*
* Glue functions
*/
static uint8_t
esp_pci_read_reg(struct ncr53c9x_softc *sc, int reg)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
return (READ_ESPREG(esc, reg));
}
static void
esp_pci_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
WRITE_ESPREG(esc, reg, v);
}
static int
esp_pci_dma_isintr(struct ncr53c9x_softc *sc)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
return (READ_ESPREG(esc, NCR_STAT) & NCRSTAT_INT) != 0;
}
static void
esp_pci_dma_reset(struct ncr53c9x_softc *sc)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE);
esc->sc_active = 0;
}
static int
esp_pci_dma_intr(struct ncr53c9x_softc *sc)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
bus_dma_tag_t xferdmat;
bus_dmamap_t xferdmam;
size_t dmasize;
int datain, i, resid, trans;
uint32_t dmastat;
char *p = NULL;
xferdmat = esc->sc_xferdmat;
xferdmam = esc->sc_xferdmam;
datain = esc->sc_datain;
dmastat = READ_DMAREG(esc, DMA_STAT);
if ((dmastat & DMASTAT_ERR) != 0) {
/* XXX not tested... */
WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT | (datain != 0 ?
DMACMD_DIR : 0));
device_printf(esc->sc_dev, "DMA error detected; Aborting.\n");
bus_dmamap_sync(xferdmat, xferdmam, datain != 0 ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(xferdmat, xferdmam);
return (-1);
}
if ((dmastat & DMASTAT_ABT) != 0) {
/* XXX what should be done? */
device_printf(esc->sc_dev, "DMA aborted.\n");
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ?
DMACMD_DIR : 0));
esc->sc_active = 0;
return (0);
}
KASSERT(esc->sc_active != 0, ("%s: DMA wasn't active", __func__));
/* DMA has stopped. */
esc->sc_active = 0;
dmasize = esc->sc_dmasize;
if (dmasize == 0) {
/* A "Transfer Pad" operation completed. */
NCR_DMA(("%s: discarded %d bytes (tcl=%d, tcm=%d)\n",
__func__, READ_ESPREG(esc, NCR_TCL) |
(READ_ESPREG(esc, NCR_TCM) << 8),
READ_ESPREG(esc, NCR_TCL), READ_ESPREG(esc, NCR_TCM)));
return (0);
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the ESP counter registers get decremented as
* bytes are clocked into the FIFO.
*/
if (datain == 0 &&
(resid = (READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0)
NCR_DMA(("%s: empty esp FIFO of %d ", __func__, resid));
if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* "Terminal count" is off, so read the residue
* out of the ESP counter registers.
*/
if (datain != 0) {
resid = READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF;
while (resid > 1)
resid =
READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_DIR);
for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */
if ((READ_DMAREG(esc, DMA_STAT) &
DMASTAT_BCMP) != 0)
break;
/* See the below comments... */
if (resid != 0)
p = *esc->sc_dmaaddr;
}
resid += READ_ESPREG(esc, NCR_TCL) |
(READ_ESPREG(esc, NCR_TCM) << 8) |
(READ_ESPREG(esc, NCR_TCH) << 16);
} else
while ((dmastat & DMASTAT_DONE) == 0)
dmastat = READ_DMAREG(esc, DMA_STAT);
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ?
DMACMD_DIR : 0));
/* Sync the transfer buffer. */
bus_dmamap_sync(xferdmat, xferdmam, datain != 0 ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(xferdmat, xferdmam);
trans = dmasize - resid;
/*
* From the technical manual notes:
*
* "In some odd byte conditions, one residual byte will be left
* in the SCSI FIFO, and the FIFO flags will never count to 0.
* When this happens, the residual byte should be retrieved
* via PIO following completion of the BLAST operation."
*/
if (p != NULL) {
p += trans;
*p = READ_ESPREG(esc, NCR_FIFO);
trans++;
}
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
device_printf(dev, "xfer (%d) > req (%d)\n", trans, dmasize);
#endif
trans = dmasize;
}
NCR_DMA(("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", __func__,
READ_ESPREG(esc, NCR_TCL), READ_ESPREG(esc, NCR_TCM),
READ_ESPREG(esc, NCR_TCH), trans, resid));
*esc->sc_dmalen -= trans;
*esc->sc_dmaaddr = (char *)*esc->sc_dmaaddr + trans;
return (0);
}
static int
esp_pci_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len,
int datain, size_t *dmasize)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
int error;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ? DMACMD_DIR :
0));
*dmasize = esc->sc_dmasize = ulmin(*dmasize, MDL_SEG_SIZE);
esc->sc_dmaaddr = addr;
esc->sc_dmalen = len;
esc->sc_datain = datain;
/*
* There's no need to set up DMA for a "Transfer Pad" operation.
*/
if (*dmasize == 0)
return (0);
/* Set the transfer length. */
WRITE_DMAREG(esc, DMA_STC, *dmasize);
/*
* Load the transfer buffer and program the DMA address.
* Note that the NCR53C9x core can't handle EINPROGRESS so we set
* BUS_DMA_NOWAIT.
*/
error = bus_dmamap_load(esc->sc_xferdmat, esc->sc_xferdmam,
*esc->sc_dmaaddr, *dmasize, esp_pci_xfermap, sc, BUS_DMA_NOWAIT);
return (error);
}
static void
esp_pci_dma_go(struct ncr53c9x_softc *sc)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
int datain;
datain = esc->sc_datain;
/* No DMA transfer for a "Transfer Pad" operation */
if (esc->sc_dmasize == 0)
return;
/* Sync the transfer buffer. */
bus_dmamap_sync(esc->sc_xferdmat, esc->sc_xferdmam, datain != 0 ?
BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
/* Set the DMA engine to the IDLE state. */
/* XXX DMA Transfer Interrupt Enable bit is broken? */
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | /* DMACMD_INTE | */
(datain != 0 ? DMACMD_DIR : 0));
/* Issue a DMA start command. */
WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | /* DMACMD_INTE | */
(datain != 0 ? DMACMD_DIR : 0));
esc->sc_active = 1;
}
static void
esp_pci_dma_stop(struct ncr53c9x_softc *sc)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
/* DMA stop */
/* XXX what should we do here ? */
WRITE_DMAREG(esc, DMA_CMD,
DMACMD_ABORT | (esc->sc_datain != 0 ? DMACMD_DIR : 0));
bus_dmamap_unload(esc->sc_xferdmat, esc->sc_xferdmam);
esc->sc_active = 0;
}
static int
esp_pci_dma_isactive(struct ncr53c9x_softc *sc)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
/* XXX should we check esc->sc_active? */
if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE)
return (1);
return (0);
}

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sys/dev/esp/ncr53c9x.c
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296
sys/dev/esp/ncr53c9xreg.h
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/* $NetBSD: ncr53c9xreg.h,v 1.16 2009/09/07 13:31:44 tsutsui Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _NCR53C9XREG_H_
#define _NCR53C9XREG_H_
/*
* Register addresses, relative to some base address
*/
#define NCR_TCL 0x00 /* RW - Transfer Count Low */
#define NCR_TCM 0x01 /* RW - Transfer Count Mid */
#define NCR_TCH 0x0e /* RW - Transfer Count High */
/* NOT on 53C90 */
#define NCR_FIFO 0x02 /* RW - FIFO data */
#define NCR_CMD 0x03 /* RW - Command (2 deep) */
#define NCRCMD_DMA 0x80 /* DMA Bit */
#define NCRCMD_NOP 0x00 /* No Operation */
#define NCRCMD_FLUSH 0x01 /* Flush FIFO */
#define NCRCMD_RSTCHIP 0x02 /* Reset Chip */
#define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
#define NCRCMD_RESEL 0x40 /* Reselect Sequence */
#define NCRCMD_SELNATN 0x41 /* Select without ATN */
#define NCRCMD_SELATN 0x42 /* Select with ATN */
#define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */
#define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */
#define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */
#define NCRCMD_SELATN3 0x46 /* Select with ATN3 */
#define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */
#define NCRCMD_SNDMSG 0x20 /* Send Message */
#define NCRCMD_SNDSTAT 0x21 /* Send Status */
#define NCRCMD_SNDDATA 0x22 /* Send Data */
#define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */
#define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */
#define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */
#define NCRCMD_DISC 0x27 /* Disconnect */
#define NCRCMD_RECMSG 0x28 /* Receive Message */
#define NCRCMD_RECCMD 0x29 /* Receive Command */
#define NCRCMD_RECDATA 0x2a /* Receive Data */
#define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
#define NCRCMD_ABORT 0x04 /* Target Abort DMA */
#define NCRCMD_TRANS 0x10 /* Transfer Information */
#define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
#define NCRCMD_MSGOK 0x12 /* Message Accepted */
#define NCRCMD_TRPAD 0x18 /* Transfer Pad */
#define NCRCMD_SETATN 0x1a /* Set ATN */
#define NCRCMD_RSTATN 0x1b /* Reset ATN */
#define NCR_STAT 0x04 /* RO - Status */
#define NCRSTAT_INT 0x80 /* Interrupt */
#define NCRSTAT_GE 0x40 /* Gross Error */
#define NCRSTAT_PE 0x20 /* Parity Error */
#define NCRSTAT_TC 0x10 /* Terminal Count */
#define NCRSTAT_VGC 0x08 /* Valid Group Code */
#define NCRSTAT_PHASE 0x07 /* Phase bits */
#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
#define NCR_BUSID_HMEXC32 0x40 /* HME xfer counter is 32bit */
#define NCR_BUSID_HMEENCID 0x10 /* HME encode reselection ID */
#define NCR_INTR 0x05 /* RO - Interrupt */
#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
#define NCRINTR_ILL 0x40 /* Illegal Command */
#define NCRINTR_DIS 0x20 /* Disconnect */
#define NCRINTR_BS 0x10 /* Bus Service */
#define NCRINTR_FC 0x08 /* Function Complete */
#define NCRINTR_RESEL 0x04 /* Reselected */
#define NCRINTR_SELATN 0x02 /* Select with ATN */
#define NCRINTR_SEL 0x01 /* Selected */
#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
#define NCR_STEP 0x06 /* RO - Sequence Step */
#define NCRSTEP_MASK 0x07 /* the last 3 bits */
#define NCRSTEP_DONE 0x04 /* command went out */
#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
/* Default 5 (53C9X) */
#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
#define NCRFIFO_FF 0x1f /* Bytes in FIFO */
#define NCR_SYNCOFF 0x07 /* WO - Synch Offset */
/* 0 = ASYNC */
/* 1 - 15 = SYNC bytes */
#define NCR_CFG1 0x08 /* RW - Configuration #1 */
#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
#define NCRCFG1_PARENB 0x10 /* Enable Parity Check */
#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
#define NCRCFG1_BUSID 0x07 /* Bus ID */
#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
/* 0 = 35.01 - 40MHz */
/* NEVER SET TO 1 */
/* 2 = 10MHz */
/* 3 = 10.01 - 15MHz */
/* 4 = 15.01 - 20MHz */
/* 5 = 20.01 - 25MHz */
/* 6 = 25.01 - 30MHz */
/* 7 = 30.01 - 35MHz */
#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
#define NCR_CFG2 0x0b /* RW - Configuration #2 */
#define NCRCFG2_RSVD 0xa0 /* reserved */
#define NCRCFG2_FE 0x40 /* Features Enable */
#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
#define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */
#define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */
#define NCRCFG2_RPE 0x02 /* Register Parity Error */
#define NCRCFG2_DPE 0x01 /* DMA Parity Error */
#define NCRCFG2_HMEFE 0x10 /* HME feature enable */
#define NCRCFG2_HME32 0x80 /* HME 32 extended */
/* Config #3 only on 53C9X */
#define NCR_CFG3 0x0c /* RW - Configuration #3 */
#define NCRCFG3_RSVD 0xe0 /* reserved */
#define NCRCFG3_IDM 0x10 /* ID Message Res Check */
#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
#define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */
#define NCRCFG3_FSCSI 0x02 /* Fast SCSI */
#define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */
/*
* For some unknown reason, the ESP406/FAS408 looks like every
* other ncr53c9x, except for configuration #3 register. At any
* rate, if you're dealing with these chips, you need to use these
* defines instead.
*/
/* Config #3 different on ESP406/FAS408 */
#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
#define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */
#define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */
#define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */
#define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */
#define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */
/* Config #3 also different on NCR53CF9x/FAS100A/FAS216/FAS236 */
#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
#define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */
#define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */
#define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */
#define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */
#define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */
/* Config #3 on FAS366 */
#define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to DMA */
#define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */
#define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */
#define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */
#define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */
#define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */
#define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */
#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
/* Config #4 only on ESP406/FAS408 */
#define NCR_CFG4 0x0d /* RW - Configuration #4 */
#define NCRCFG4_CRS1 0x80 /* Select register set #1 */
#define NCRCFG4_RSVD 0x7b /* reserved */
#define NCRCFG4_ACTNEG 0x04 /* Active negation */
/*
The following registers are only on the ESP406/FAS408. The
documentation refers to them as "Control Register Set #1".
These are the registers that are visible when bit 7 of
register 0x0d is set. This bit is common to both register sets.
*/
#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
#define NCRJMP_RSVD 0xc0 /* reserved */
#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
#define NCRJMP_J4 0x10 /* Jumper #4 */
#define NCRJMP_J3 0x08 /* Jumper #3 */
#define NCRJMP_J2 0x04 /* Jumper #2 */
#define NCRJMP_J1 0x02 /* Jumper #1 */
#define NCRJMP_J0 0x01 /* Jumper #0 */
#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
#define NCRPSTAT_PERR 0x80 /* PIO Error */
#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
#define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */
#define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */
#define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */
#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
#define NCRPIOI_RSVD 0xe0 /* reserved */
#define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */
#define NCRPIOI_13 0x08 /* IRQ When 1/3 */
#define NCRPIOI_23 0x04 /* IRQ When 2/3 */
#define NCRPIOI_FULL 0x02 /* IRQ When Full */
#define NCRPIOI_FINV 0x01 /* Flag Invert */
#define NCR_CFG5 0x0d /* RW - Configuration #5 */
#define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */
#define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */
#define NCRCFG5_AADDR 0x20 /* Auto Address */
#define NCRCFG5_PTRINC 0x10 /* Pointer Increment */
#define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */
#define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */
#define NCRCFG5_INTP 0x02 /* INT Polarity */
#define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */
#define NCR_SIGNTR 0x0e /* RO - Signature */
/* Am53c974 Config #3 */
#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
#define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */
#define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */
#define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */
#define NCRAMDCFG3_FSCSI 0x10 /* Fast SCSI */
#define NCRAMDCFG3_FCLK 0x08 /* Fast Clock (40MHz) */
#define NCRAMDCFG3_RSVD 0x07 /* Reserved */
/* Am53c974 Config #4 */
#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
#define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */
#define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */
#define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */
#define NCRAMDCFG4_GE35NS 0x40 /* Signal window 35ns */
#define NCRAMDCFG4_GE0NS 0xc0 /* Signal window 0ns */
#define NCRAMDCFG4_PWD 0x20 /* Reduced power feature */
#define NCRAMDCFG4_RSVD 0x13 /* Reserved */
#define NCRAMDCFG4_RAE 0x08 /* Active neg. REQ/ACK */
#define NCRAMDCFG4_RADE 0x04 /* Active neg. REQ/ACK/DAT */
/*
* FAS366
*/
#define NCR_RCL NCR_TCH /* Recommand counter low */
#define NCR_RCH 0xf /* Recommand counter high */
#define NCR_UID NCR_RCL /* fas366 part-uniq id */
/* status register #2 definitions (read only) */
#define NCR_STAT2 NCR_CCF
#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */
#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */
#endif /* _NCR53C9XREG_H_ */

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/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-4-Clause
*
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _NCR53C9XVAR_H_
#define _NCR53C9XVAR_H_
#include <sys/lock.h>
/* Set this to 1 for normal debug, or 2 for per-target tracing. */
/* #define NCR53C9X_DEBUG 2 */
/* Wide or differential can have 16 targets */
#define NCR_NLUN 8
#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
#define FREQTOCCF(freq) (((freq + 4) / 5))
/*
* NCR 53c9x variants. Note these values are used as indexes into
* a table; do not modify them unless you know what you are doing.
*/
#define NCR_VARIANT_ESP100 0
#define NCR_VARIANT_ESP100A 1
#define NCR_VARIANT_ESP200 2
#define NCR_VARIANT_NCR53C94 3
#define NCR_VARIANT_NCR53C96 4
#define NCR_VARIANT_ESP406 5
#define NCR_VARIANT_FAS408 6
#define NCR_VARIANT_FAS216 7
#define NCR_VARIANT_AM53C974 8
#define NCR_VARIANT_FAS366 9
#define NCR_VARIANT_NCR53C90_86C01 10
#define NCR_VARIANT_FAS100A 11
#define NCR_VARIANT_FAS236 12
#define NCR_VARIANT_MAX 13
/* XXX Max tag depth. Should this be defined in the register header? */
#define NCR_TAG_DEPTH 256
/*
* ECB. Holds additional information for each SCSI command Comments: We
* need a separate scsi command block because we may need to overwrite it
* with a request sense command. Basically, we refrain from fiddling with
* the ccb union (except do the expected updating of return values).
* We'll generally update: ccb->ccb_h.status and ccb->csio.{resid,
* scsi_status,sense_data}.
*/
struct ncr53c9x_ecb {
/* These fields are preserved between alloc and free. */
struct callout ch;
struct ncr53c9x_softc *sc;
int tag_id;
int flags;
union ccb *ccb; /* SCSI xfer ctrl block from above */
TAILQ_ENTRY(ncr53c9x_ecb) free_links;
TAILQ_ENTRY(ncr53c9x_ecb) chain;
#define ECB_ALLOC 0x01
#define ECB_READY 0x02
#define ECB_SENSE 0x04
#define ECB_ABORT 0x40
#define ECB_RESET 0x80
#define ECB_TENTATIVE_DONE 0x100
int timeout;
struct {
uint8_t msg[3]; /* Selection Id msg and tags */
struct scsi_generic cmd; /* SCSI command block */
} cmd;
uint8_t *daddr; /* Saved data pointer */
int clen; /* Size of command in cmd.cmd */
int dleft; /* Residue */
uint8_t stat; /* SCSI status byte */
uint8_t tag[2]; /* TAG bytes */
uint8_t pad[1];
#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
char trace[1000];
#endif
};
#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
#define ECB_TRACE(ecb, msg, a, b) do { \
const char *f = "[" msg "]"; \
int n = strlen((ecb)->trace); \
if (n < (sizeof((ecb)->trace)-100)) \
sprintf((ecb)->trace + n, f, a, b); \
} while (/* CONSTCOND */0)
#else
#define ECB_TRACE(ecb, msg, a, b)
#endif
/*
* Some info about each (possible) target and LUN on the SCSI bus.
*
* SCSI I and II devices can have up to 8 LUNs, each with up to 256
* outstanding tags. SCSI III devices have 64-bit LUN identifiers
* that can be sparsely allocated.
*
* Since SCSI II devices can have up to 8 LUNs, we use an array
* of 8 pointers to ncr53c9x_linfo structures for fast lookup.
* Longer LUNs need to traverse the linked list.
*/
struct ncr53c9x_linfo {
int64_t lun;
LIST_ENTRY(ncr53c9x_linfo) link;
time_t last_used;
uint8_t used; /* # slots in use */
uint8_t avail; /* where to start scanning */
uint8_t busy;
struct ncr53c9x_ecb *untagged;
struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
};
struct ncr53c9x_xinfo {
uint8_t period;
uint8_t offset;
uint8_t width;
};
struct ncr53c9x_tinfo {
int cmds; /* # of commands processed */
int dconns; /* # of disconnects */
int touts; /* # of timeouts */
int perrs; /* # of parity errors */
int senses; /* # of request sense commands sent */
uint8_t flags;
#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
#define T_TAG 0x04 /* Turn on TAG QUEUEs */
#define T_SDTRSENT 0x08 /* SDTR message has been sent to */
#define T_WDTRSENT 0x10 /* WDTR message has been sent to */
struct ncr53c9x_xinfo curr;
struct ncr53c9x_xinfo goal;
LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
};
/* Look up a lun in a tinfo */
#define TINFO_LUN(t, l) ( \
(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
? ((t)->lun[(l)]) \
: ncr53c9x_lunsearch((t), (int64_t)(l)) \
)
/* Register a linenumber (for debugging). */
#define LOGLINE(p)
#define NCR_SHOWECBS 0x01
#define NCR_SHOWINTS 0x02
#define NCR_SHOWCMDS 0x04
#define NCR_SHOWMISC 0x08
#define NCR_SHOWTRAC 0x10
#define NCR_SHOWSTART 0x20
#define NCR_SHOWPHASE 0x40
#define NCR_SHOWDMA 0x80
#define NCR_SHOWCCMDS 0x100
#define NCR_SHOWMSGS 0x200
#ifdef NCR53C9X_DEBUG
extern int ncr53c9x_debug;
#define NCR_ECBS(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_MISC(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_INTS(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_TRACE(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_CMDS(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_START(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_PHASE(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_DMA(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#define NCR_MSGS(str) \
do { \
if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \
printf str; \
} while (/* CONSTCOND */0)
#else
#define NCR_ECBS(str)
#define NCR_MISC(str)
#define NCR_INTS(str)
#define NCR_TRACE(str)
#define NCR_CMDS(str)
#define NCR_START(str)
#define NCR_PHASE(str)
#define NCR_DMA(str)
#define NCR_MSGS(str)
#endif
#define NCR_MAX_MSG_LEN 8
struct ncr53c9x_softc;
/*
* Function switch used as glue to MD code
*/
struct ncr53c9x_glue {
/* Mandatory entry points. */
uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int);
void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t);
int (*gl_dma_isintr)(struct ncr53c9x_softc *);
void (*gl_dma_reset)(struct ncr53c9x_softc *);
int (*gl_dma_intr)(struct ncr53c9x_softc *);
int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *,
int, size_t *);
void (*gl_dma_go)(struct ncr53c9x_softc *);
void (*gl_dma_stop)(struct ncr53c9x_softc *);
int (*gl_dma_isactive)(struct ncr53c9x_softc *);
};
struct ncr53c9x_softc {
device_t sc_dev; /* us as a device */
struct cam_sim *sc_sim; /* our scsi adapter */
struct cam_path *sc_path; /* our scsi channel */
struct callout sc_watchdog; /* periodic timer */
const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
int sc_cfflags; /* Copy of config flags */
/* register defaults */
uint8_t sc_cfg1; /* Config 1 */
uint8_t sc_cfg2; /* Config 2, not ESP100 */
uint8_t sc_cfg3; /* Config 3, ESP200,FAS */
uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
uint8_t sc_cfg4; /* Config 4, only ESP200 */
uint8_t sc_cfg5; /* Config 5, only ESP200 */
uint8_t sc_ccf; /* Clock Conversion */
uint8_t sc_timeout;
/* register copies, see ncr53c9x_readregs() */
uint8_t sc_espintr;
uint8_t sc_espstat;
uint8_t sc_espstep;
uint8_t sc_espstat2;
uint8_t sc_espfflags;
/* Lists of command blocks */
TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
struct ncr53c9x_ecb *sc_nexus; /* Current command */
int sc_ntarg;
struct ncr53c9x_tinfo *sc_tinfo;
/* Data about the current nexus (updated for every cmd switch) */
void *sc_dp; /* Current data pointer */
ssize_t sc_dleft; /* Data left to transfer */
/* Adapter state */
int sc_phase; /* Copy of what bus phase we are in */
int sc_prevphase; /* Copy of what bus phase we were in */
uint8_t sc_state; /* State applicable to the adapter */
uint8_t sc_flags; /* See below */
uint8_t sc_selid;
uint8_t sc_lastcmd;
/* Message stuff */
uint16_t sc_msgify; /* IDENTIFY message associated with nexus */
uint16_t sc_msgout; /* What message is on its way out? */
uint16_t sc_msgpriq; /* One or more messages to send (encoded) */
uint16_t sc_msgoutq; /* What messages have been sent so far? */
uint8_t *sc_omess; /* MSGOUT buffer */
int sc_omess_self; /* MSGOUT buffer is self-allocated */
void *sc_omp; /* Message pointer (for multibyte messages) */
size_t sc_omlen;
uint8_t *sc_imess; /* MSGIN buffer */
int sc_imess_self; /* MSGIN buffer is self-allocated */
void *sc_imp; /* Message pointer (for multibyte messages) */
size_t sc_imlen;
void *sc_cmdp; /* Command pointer (for DMAed commands) */
size_t sc_cmdlen; /* Size of command in transit */
/* Hardware attributes */
int sc_freq; /* SCSI bus frequency in MHz */
int sc_id; /* Our SCSI id */
int sc_rev; /* Chip revision */
int sc_features; /* Chip features */
int sc_minsync; /* Minimum sync period / 4 */
int sc_maxxfer; /* Maximum transfer size */
int sc_maxoffset; /* Maximum offset */
int sc_maxwidth; /* Maximum width */
int sc_extended_geom; /* Should we return extended geometry */
struct mtx sc_lock; /* driver mutex */
struct ncr53c9x_ecb *ecb_array;
TAILQ_HEAD(,ncr53c9x_ecb) free_list;
};
/* values for sc_state */
#define NCR_IDLE 1 /* Waiting for something to do */
#define NCR_SELECTING 2 /* SCSI command is arbiting */
#define NCR_RESELECTED 3 /* Has been reselected */
#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
#define NCR_CLEANING 8
#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
/* values for sc_flags */
#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
#define NCR_ABORTING 0x02 /* Bailing out */
#define NCR_ICCS 0x04 /* Expect status phase results */
#define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */
#define NCR_ATN 0x10 /* ATN asserted */
#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */
/* values for sc_features */
#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
#define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */
/* values for sc_msgout */
#define SEND_DEV_RESET 0x0001
#define SEND_PARITY_ERROR 0x0002
#define SEND_INIT_DET_ERR 0x0004
#define SEND_REJECT 0x0008
#define SEND_IDENTIFY 0x0010
#define SEND_ABORT 0x0020
#define SEND_TAG 0x0040
#define SEND_WDTR 0x0080
#define SEND_SDTR 0x0100
/* SCSI Status codes */
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
/* phase bits */
#define IOI 0x01
#define CDI 0x02
#define MSGI 0x04
/* Information transfer phases */
#define DATA_OUT_PHASE (0)
#define DATA_IN_PHASE (IOI)
#define COMMAND_PHASE (CDI)
#define STATUS_PHASE (CDI | IOI)
#define MESSAGE_OUT_PHASE (MSGI | CDI)
#define MESSAGE_IN_PHASE (MSGI | CDI | IOI)
#define PHASE_MASK (MSGI | CDI | IOI)
/* Some pseudo phases for getphase()*/
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
/*
* Macros to read and write the chip's registers.
*/
#define NCR_READ_REG(sc, reg) \
(*(sc)->sc_glue->gl_read_reg)((sc), (reg))
#define NCR_WRITE_REG(sc, reg, val) \
(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
#ifdef NCR53C9X_DEBUG
#define NCRCMD(sc, cmd) do { \
if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \
sc->sc_lastcmd = cmd; \
NCR_WRITE_REG(sc, NCR_CMD, cmd); \
} while (/* CONSTCOND */ 0)
#else
#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
#endif
/*
* Macros for locking
*/
#define NCR_LOCK_INIT(_sc) \
mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
#define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock)
#define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
#define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
#define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what))
#define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
/*
* DMA macros for NCR53c9x
*/
#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
(*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc))
#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
/*
* Macro to convert the chip register Clock Per Byte value to
* Synchronous Transfer Period.
*/
#define ncr53c9x_cpb2stp(sc, cpb) \
((250 * (cpb)) / (sc)->sc_freq)
extern devclass_t esp_devclass;
int ncr53c9x_attach(struct ncr53c9x_softc *sc);
int ncr53c9x_detach(struct ncr53c9x_softc *sc);
void ncr53c9x_intr(void *arg);
#endif /* _NCR53C9XVAR_H_ */

79
sys/dev/ic/esp.h
View File

@ -1,79 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1995 Sean Eric Fagan.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _IC_ESP_H_
#define _IC_ESP_H_
/*
* Definitions for Hayes ESP serial cards.
*/
/*
* CMD1 and CMD2 are the command ports, offsets from <esp_iobase>.
*/
#define ESP_CMD1 4
#define ESP_CMD2 5
/*
* STAT1 and STAT2 are to get return values and status bytes;
* they overload CMD1 and CMD2.
*/
#define ESP_STATUS1 ESP_CMD1
#define ESP_STATUS2 ESP_CMD2
/*
* Commands. Commands are given by writing the command value to
* ESP_CMD1 and then writing or reading some number of bytes from
* ESP_CMD2 or ESP_STATUS2.
*/
#define ESP_GETTEST 0x01 /* self-test command (1 byte + extras) */
#define ESP_GETDIPS 0x02 /* get on-board DIP switches (1 byte) */
#define ESP_SETFLOWTYPE 0x08 /* set type of flow-control (2 bytes) */
#define ESP_SETRXFLOW 0x0a /* set Rx FIFO flow control levels (4 bytes) */
#define ESP_SETMODE 0x10 /* set board mode (1 byte) */
#define ESP_SETCLOCK 0x23 /* set UART clock prescaler */
/* Mode bits (ESP_SETMODE). */
#define ESP_MODE_FIFO 0x02 /* act like a 16550 (compatibility mode) */
#define ESP_MODE_RTS 0x04 /* use RTS hardware flow control */
#define ESP_MODE_SCALE 0x80 /* scale FIFO trigger levels */
/* Flow control type bits (ESP_SETFLOWTYPE). */
#define ESP_FLOW_RTS 0x04 /* cmd1: local Rx sends RTS flow control */
#define ESP_FLOW_CTS 0x10 /* cmd2: local transmitter responds to CTS */
/* Used by ESP_SETRXFLOW. */
#define HIBYTE(w) (((w) >> 8) & 0xff)
#define LOBYTE(w) ((w) & 0xff)
#endif /* !_IC_ESP_H_ */

1
sys/i386/conf/GENERIC
View File

@ -132,7 +132,6 @@ device siis # SiliconImage SiI3124/SiI3132/SiI3531 SATA
# SCSI Controllers
device ahc # AHA2940 and onboard AIC7xxx devices
device esp # AMD Am53C974 (Tekram DC-390(T))
device hptiop # Highpoint RocketRaid 3xxx series
device isp # Qlogic family
#device ispfw # Firmware for QLogic HBAs- normally a module

1
sys/modules/Makefile
View File

@ -109,7 +109,6 @@ SUBDIR= \
${_em} \
${_ena} \
${_enetc} \
esp \
${_et} \
evdev \
${_exca} \

9
sys/modules/esp/Makefile
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@ -1,9 +0,0 @@
# $FreeBSD$
.PATH: ${SRCTOP}/sys/dev/esp
KMOD= esp
SRCS= device_if.h esp_pci.c bus_if.h ncr53c9x.c
SRCS+= opt_cam.h pci_if.h
.include <bsd.kmod.mk>

21
tools/kerneldoc/subsys/Doxyfile-dev_esp
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@ -1,21 +0,0 @@
# Doxyfile 1.5.2
# $FreeBSD$
#---------------------------------------------------------------------------
# Project related configuration options
#---------------------------------------------------------------------------
PROJECT_NAME = "FreeBSD kernel ESP device code"
OUTPUT_DIRECTORY = $(DOXYGEN_DEST_PATH)/dev_esp/
EXTRACT_ALL = YES # for undocumented src, no warnings enabled
#---------------------------------------------------------------------------
# configuration options related to the input files
#---------------------------------------------------------------------------
INPUT = $(DOXYGEN_SRC_PATH)/dev/esp/ \
$(NOTREVIEWED)
GENERATE_TAGFILE = dev_esp/dev_esp.tag
@INCLUDE_PATH = $(DOXYGEN_INCLUDE_PATH)
@INCLUDE = common-Doxyfile