Import Linux 5.1 DTS files
This commit is contained in:
Emmanuel Vadot
parent
2131505c51
commit
0db636cb5e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=347363 svn path=/vendor/device-tree/5.1/; revision=347364; tag=vendor/device-tree/5.1
@ -15,7 +15,7 @@ DT_TMP_SCHEMA := processed-schema.yaml
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extra-y += $(DT_TMP_SCHEMA)
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quiet_cmd_mk_schema = SCHEMA $@
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cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(filter-out FORCE, $^)
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cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(real-prereqs)
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DT_DOCS = $(shell \
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cd $(srctree)/$(src) && \
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@ -109,6 +109,7 @@ Board compatible values (alphabetically, grouped by SoC):
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- "amlogic,s400" (Meson axg a113d)
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- "amlogic,u200" (Meson g12a s905d2)
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- "amediatech,x96-max" (Meson g12a s905x2)
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Amlogic Meson Firmware registers Interface
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------------------------------------------
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@ -1,6 +0,0 @@
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Armadeus i.MX Platforms Device Tree Bindings
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-----------------------------------------------
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APF51: i.MX51 based module.
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Required root node properties:
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- compatible = "armadeus,imx51-apf51", "fsl,imx51";
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@ -21,7 +21,8 @@ Its subnodes can be:
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RSTC Reset Controller required properties:
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- compatible: Should be "atmel,<chip>-rstc".
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<chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
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<chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
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it also can be "microchip,sam9x60-rstc"
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- reg: Should contain registers location and length
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- clocks: phandle to input clock.
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@ -147,6 +148,7 @@ required properties:
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- compatible: Should be "atmel,<chip>-sfr", "syscon" or
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"atmel,<chip>-sfrbu", "syscon"
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<chip> can be "sama5d3", "sama5d4" or "sama5d2".
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It also can be "microchip,sam9x60-sfr", "syscon".
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- reg: Should contain registers location and length
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sfr@f0038000 {
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@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
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Required root node properties:
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compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
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Raspberry Pi 3 Model A+
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Required root node properties:
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compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
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Raspberry Pi 3 Model B
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Required root node properties:
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compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
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@ -1,6 +0,0 @@
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Beckhoff Automation Platforms Device Tree Bindings
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--------------------------------------------------
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CX9020 Embedded PC
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Required root node properties:
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- compatible = "bhf,cx9020", "fsl,imx53";
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18
Bindings/arm/bitmain.yaml
Normal file
18
Bindings/arm/bitmain.yaml
Normal file
@ -0,0 +1,18 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/bitmain.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bitmain platform device tree bindings
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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compatible:
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items:
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- enum:
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- bitmain,sophon-edge
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- const: bitmain,bm1880
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...
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@ -1,25 +0,0 @@
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CompuLab SB-SOM is a multi-module baseboard capable of carrying:
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- CM-T43
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- CM-T54
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- CM-QS600
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- CL-SOM-AM57x
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- CL-SOM-iMX7
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modules with minor modifications to the SB-SOM assembly.
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Required root node properties:
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- compatible = should be "compulab,sb-som"
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Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
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Freescale i.MX7 ARM Cortex-A7 System-on-Chip.
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Required root node properties:
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- compatible = "compulab,cl-som-imx7", "fsl,imx7d";
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Compulab SBC-iMX7 is a single board computer based on the
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Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
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the CL-SOM-iMX7 System-on-Module providing most of the functions,
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and SB-SOM-iMX7 carrier board providing additional peripheral
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functions and connectors.
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Required root node properties:
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- compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
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@ -228,6 +228,7 @@ patternProperties:
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- renesas,r9a06g032-smp
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- rockchip,rk3036-smp
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- rockchip,rk3066-smp
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- socionext,milbeaut-m10v-smp
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- ste,dbx500-smp
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cpu-release-addr:
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16
Bindings/arm/freescale/fsl,imx7ulp-sim.txt
Normal file
16
Bindings/arm/freescale/fsl,imx7ulp-sim.txt
Normal file
@ -0,0 +1,16 @@
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Freescale i.MX7ULP System Integration Module
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----------------------------------------------
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The system integration module (SIM) provides system control and chip configuration
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registers. In this module, chip revision information is located in JTAG ID register,
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and a set of registers have been made available in DGO domain for SW use, with the
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objective to maintain its value between system resets.
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Required properties:
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- compatible: Should be "fsl,imx7ulp-sim".
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- reg: Specifies base physical address and size of the register sets.
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Example:
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sim: sim@410a3000 {
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compatible = "fsl,imx7ulp-sim", "syscon";
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reg = <0x410a3000 0x1000>;
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};
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@ -58,7 +58,11 @@ This binding for the SCU power domain providers uses the generic power
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domain binding[2].
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Required properties:
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- compatible: Should be "fsl,imx8qxp-scu-pd".
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- compatible: Should be one of:
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"fsl,imx8qm-scu-pd",
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"fsl,imx8qxp-scu-pd"
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followed by "fsl,scu-pd"
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- #power-domain-cells: Must be 1. Contains the Resource ID used by
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SCU commands.
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See detailed Resource ID list from:
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@ -70,7 +74,10 @@ Clock bindings based on SCU Message Protocol
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This binding uses the common clock binding[1].
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Required properties:
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- compatible: Should be "fsl,imx8qxp-clock".
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- compatible: Should be one of:
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"fsl,imx8qm-clock"
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"fsl,imx8qxp-clock"
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followed by "fsl,scu-clk"
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- #clock-cells: Should be 1. Contains the Clock ID value.
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- clocks: List of clock specifiers, must contain an entry for
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each required entry in clock-names
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@ -137,7 +144,7 @@ firmware {
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&lsio_mu1 1 3>;
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clk: clk {
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compatible = "fsl,imx8qxp-clk";
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compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
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#clock-cells = <1>;
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};
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@ -154,7 +161,7 @@ firmware {
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};
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pd: imx8qx-pd {
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compatible = "fsl,imx8qxp-scu-pd";
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compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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@ -1,237 +0,0 @@
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Freescale i.MX Platforms Device Tree Bindings
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-----------------------------------------------
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i.MX23 Evaluation Kit
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Required root node properties:
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- compatible = "fsl,imx23-evk", "fsl,imx23";
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i.MX25 Product Development Kit
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Required root node properties:
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- compatible = "fsl,imx25-pdk", "fsl,imx25";
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i.MX27 Product Development Kit
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Required root node properties:
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- compatible = "fsl,imx27-pdk", "fsl,imx27";
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i.MX28 Evaluation Kit
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Required root node properties:
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- compatible = "fsl,imx28-evk", "fsl,imx28";
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i.MX51 Babbage Board
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Required root node properties:
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- compatible = "fsl,imx51-babbage", "fsl,imx51";
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i.MX53 Automotive Reference Design Board
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Required root node properties:
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- compatible = "fsl,imx53-ard", "fsl,imx53";
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i.MX53 Evaluation Kit
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Required root node properties:
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- compatible = "fsl,imx53-evk", "fsl,imx53";
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i.MX53 Quick Start Board
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Required root node properties:
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- compatible = "fsl,imx53-qsb", "fsl,imx53";
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i.MX53 Smart Mobile Reference Design Board
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Required root node properties:
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- compatible = "fsl,imx53-smd", "fsl,imx53";
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i.MX6 Quad Armadillo2 Board
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Required root node properties:
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- compatible = "fsl,imx6q-arm2", "fsl,imx6q";
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i.MX6 Quad SABRE Lite Board
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Required root node properties:
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- compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
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i.MX6 Quad SABRE Smart Device Board
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Required root node properties:
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- compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
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i.MX6 Quad SABRE Automotive Board
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Required root node properties:
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- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
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i.MX6SLL EVK board
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Required root node properties:
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- compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
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i.MX6 Quad Plus SABRE Smart Device Board
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Required root node properties:
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- compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
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i.MX6 Quad Plus SABRE Automotive Board
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Required root node properties:
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- compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
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i.MX6 DualLite SABRE Smart Device Board
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Required root node properties:
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- compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
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i.MX6 DualLite/Solo SABRE Automotive Board
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Required root node properties:
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- compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
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i.MX6 SoloLite EVK Board
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Required root node properties:
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- compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
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i.MX6 UltraLite 14x14 EVK Board
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Required root node properties:
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- compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
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i.MX6 UltraLiteLite 14x14 EVK Board
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Required root node properties:
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- compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
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i.MX6 ULZ 14x14 EVK Board
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Required root node properties:
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- compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
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i.MX6 SoloX SDB Board
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Required root node properties:
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- compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
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i.MX6 SoloX Sabre Auto Board
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Required root node properties:
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- compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
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i.MX7 SabreSD Board
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Required root node properties:
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- compatible = "fsl,imx7d-sdb", "fsl,imx7d";
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i.MX7ULP Evaluation Kit
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Required root node properties:
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- compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
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Generic i.MX boards
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-------------------
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No iomux setup is done for these boards, so this must have been configured
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by the bootloader for boards to work with the generic bindings.
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i.MX27 generic board
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Required root node properties:
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- compatible = "fsl,imx27";
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i.MX51 generic board
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Required root node properties:
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- compatible = "fsl,imx51";
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i.MX53 generic board
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Required root node properties:
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- compatible = "fsl,imx53";
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i.MX6q generic board
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Required root node properties:
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- compatible = "fsl,imx6q";
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i.MX7ULP generic board
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Required root node properties:
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- compatible = "fsl,imx7ulp";
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Freescale Vybrid Platform Device Tree Bindings
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----------------------------------------------
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For the Vybrid SoC familiy all variants with DDR controller are supported,
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which is the VF5xx and VF6xx series. Out of historical reasons, in most
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places the kernel uses vf610 to refer to the whole familiy.
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The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
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core support.
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Required root node compatible property (one of them):
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- compatible = "fsl,vf500";
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- compatible = "fsl,vf510";
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- compatible = "fsl,vf600";
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- compatible = "fsl,vf610";
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- compatible = "fsl,vf610m4";
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Freescale LS1021A Platform Device Tree Bindings
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------------------------------------------------
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Required root node compatible properties:
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- compatible = "fsl,ls1021a";
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Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
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----------------------------------------------------------------
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LS1012A SoC
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Required root node properties:
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- compatible = "fsl,ls1012a";
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LS1012A ARMv8 based RDB Board
|
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Required root node properties:
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- compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
|
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LS1012A ARMv8 based FRDM Board
|
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Required root node properties:
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- compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
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LS1012A ARMv8 based QDS Board
|
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Required root node properties:
|
||||
- compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
|
||||
|
||||
LS1043A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a";
|
||||
|
||||
LS1043A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
|
||||
|
||||
LS1043A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
|
||||
|
||||
LS1046A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1046a";
|
||||
|
||||
LS1046A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
|
||||
|
||||
LS1046A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
|
||||
|
||||
LS1088A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1088a";
|
||||
|
||||
LS1088A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
|
||||
|
||||
LS1088A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
|
||||
|
||||
LS2080A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a";
|
||||
|
||||
LS2080A ARMv8 based Simulator model
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
|
||||
|
||||
LS2080A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
|
||||
|
||||
LS2080A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
|
||||
|
||||
LS2088A SoC
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2088a";
|
||||
|
||||
LS2088A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
|
||||
|
||||
LS2088A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
|
||||
232
Bindings/arm/fsl.yaml
Normal file
232
Bindings/arm/fsl.yaml
Normal file
@ -0,0 +1,232 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Li Yang <leoyang.li@nxp.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: i.MX23 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx23-evk
|
||||
- olimex,imx23-olinuxino
|
||||
- const: fsl,imx23
|
||||
|
||||
- description: i.MX25 Product Development Kit
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx25-pdk
|
||||
- const: fsl,imx25
|
||||
|
||||
- description: i.MX27 Product Development Kit
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx27-pdk
|
||||
- const: fsl,imx27
|
||||
|
||||
- description: i.MX28 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx28-evk
|
||||
- i2se,duckbill
|
||||
- i2se,duckbill-2
|
||||
- technologic,imx28-ts4600
|
||||
- const: fsl,imx28
|
||||
- description: i.MX28 Duckbill 2 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- i2se,duckbill-2-485
|
||||
- i2se,duckbill-2-enocean
|
||||
- i2se,duckbill-2-spi
|
||||
- const: i2se,duckbill-2
|
||||
- const: fsl,imx28
|
||||
|
||||
- description: i.MX51 Babbage Board
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx51-apf51
|
||||
- fsl,imx51-babbage
|
||||
- technologic,imx51-ts4800
|
||||
- const: fsl,imx51
|
||||
|
||||
- description: i.MX53 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- bhf,cx9020
|
||||
- fsl,imx53-ard
|
||||
- fsl,imx53-evk
|
||||
- fsl,imx53-qsb
|
||||
- fsl,imx53-smd
|
||||
- const: fsl,imx53
|
||||
|
||||
- description: i.MX6Q based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6q-arm2
|
||||
- fsl,imx6q-sabreauto
|
||||
- fsl,imx6q-sabrelite
|
||||
- fsl,imx6q-sabresd
|
||||
- technologic,imx6q-ts4900
|
||||
- technologic,imx6q-ts7970
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: i.MX6QP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board
|
||||
- fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board
|
||||
- const: fsl,imx6qp
|
||||
|
||||
- description: i.MX6DL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
|
||||
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
|
||||
- technologic,imx6dl-ts4900
|
||||
- technologic,imx6dl-ts7970
|
||||
- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
|
||||
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
|
||||
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6SL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
|
||||
- const: fsl,imx6sl
|
||||
|
||||
- description: i.MX6SLL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6sll-evk
|
||||
- const: fsl,imx6sll
|
||||
|
||||
- description: i.MX6SX based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
|
||||
- fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
|
||||
- const: fsl,imx6sx
|
||||
|
||||
- description: i.MX6UL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: i.MX6ULL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULZ based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board
|
||||
- const: fsl,imx6ull # This seems odd. Should be last?
|
||||
- const: fsl,imx6ulz
|
||||
|
||||
- description: i.MX7D based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx7d-sdb # i.MX7 SabreSD Board
|
||||
- const: fsl,imx7d
|
||||
|
||||
- description:
|
||||
Compulab SBC-iMX7 is a single board computer based on the
|
||||
Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
|
||||
the CL-SOM-iMX7 System-on-Module providing most of the functions,
|
||||
and SB-SOM-iMX7 carrier board providing additional peripheral
|
||||
functions and connectors.
|
||||
items:
|
||||
- const: compulab,sbc-imx7
|
||||
- const: compulab,cl-som-imx7
|
||||
- const: fsl,imx7d
|
||||
|
||||
- description: i.MX8QXP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
|
||||
- const: fsl,imx8qxp
|
||||
|
||||
- description:
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
|
||||
For the Vybrid SoC familiy all variants with DDR controller are supported,
|
||||
which is the VF5xx and VF6xx series. Out of historical reasons, in most
|
||||
places the kernel uses vf610 to refer to the whole familiy.
|
||||
The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
|
||||
core support.
|
||||
items:
|
||||
- enum:
|
||||
- fsl,vf500
|
||||
- fsl,vf510
|
||||
- fsl,vf600
|
||||
- fsl,vf610
|
||||
- fsl,vf610m4
|
||||
|
||||
- description: LS1012A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- ebs-systart,oxalis
|
||||
- fsl,ls1012a-rdb
|
||||
- fsl,ls1012a-frdm
|
||||
- fsl,ls1012a-qds
|
||||
- const: fsl,ls1012a
|
||||
|
||||
- description: LS1021A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1021a-moxa-uc-8410a
|
||||
- fsl,ls1021a-qds
|
||||
- fsl,ls1021a-twr
|
||||
- const: fsl,ls1021a
|
||||
|
||||
- description: LS1043A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1043a-rdb
|
||||
- fsl,ls1043a-qds
|
||||
- const: fsl,ls1043a
|
||||
|
||||
- description: LS1046A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1046a-qds
|
||||
- fsl,ls1046a-rdb
|
||||
- const: fsl,ls1046a
|
||||
|
||||
- description: LS1088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls1088a-qds
|
||||
- fsl,ls1088a-rdb
|
||||
- const: fsl,ls1088a
|
||||
|
||||
- description: LS2080A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls2080a-simu
|
||||
- fsl,ls2080a-qds
|
||||
- fsl,ls2080a-rdb
|
||||
- const: fsl,ls2080a
|
||||
|
||||
- description: LS2088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,ls2088a-qds
|
||||
- fsl,ls2088a-rdb
|
||||
- const: fsl,ls2088a
|
||||
|
||||
...
|
||||
@ -1,22 +0,0 @@
|
||||
I2SE Device Tree Bindings
|
||||
-------------------------
|
||||
|
||||
Duckbill Board
|
||||
Required root node properties:
|
||||
- compatible = "i2se,duckbill", "fsl,imx28";
|
||||
|
||||
Duckbill 2 Board
|
||||
Required root node properties:
|
||||
- compatible = "i2se,duckbill-2", "fsl,imx28";
|
||||
|
||||
Duckbill 2 485 Board
|
||||
Required root node properties:
|
||||
- compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
|
||||
|
||||
Duckbill 2 EnOcean Board
|
||||
Required root node properties:
|
||||
- compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
|
||||
|
||||
Duckbill 2 SPI Board
|
||||
Required root node properties:
|
||||
- compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28";
|
||||
@ -1,114 +0,0 @@
|
||||
* ARM L2 Cache Controller
|
||||
|
||||
ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
|
||||
PL310 and variants) based level 2 cache controller. All these various implementations
|
||||
of the L2 cache controller have compatible programming models (Note 1).
|
||||
Some of the properties that are just prefixed "cache-*" are taken from section
|
||||
3.7.3 of the Devicetree Specification which can be found at:
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
The ARM L2 cache representation in the device tree should be done as follows:
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be one of:
|
||||
"arm,pl310-cache"
|
||||
"arm,l220-cache"
|
||||
"arm,l210-cache"
|
||||
"bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
|
||||
"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
|
||||
offset needs to be added to the address before passing down to the L2
|
||||
cache controller
|
||||
"marvell,aurora-system-cache": Marvell Controller designed to be
|
||||
compatible with the ARM one, with system cache mode (meaning
|
||||
maintenance operations on L1 are broadcasted to the L2 and L2
|
||||
performs the same operation).
|
||||
"marvell,aurora-outer-cache": Marvell Controller designed to be
|
||||
compatible with the ARM one with outer cache mode.
|
||||
"marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
|
||||
with arm,pl310-cache controller.
|
||||
- cache-unified : Specifies the cache is a unified cache.
|
||||
- cache-level : Should be set to 2 for a level 2 cache.
|
||||
- reg : Physical base address and size of cache controller's memory mapped
|
||||
registers.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Minimum valid values are 1. Controllers
|
||||
without setup latency control should use a value of 0.
|
||||
- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Controllers without setup latency control
|
||||
should use 0. Controllers without separate read and write Tag RAM latency
|
||||
values should only use the first cell.
|
||||
- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
|
||||
- arm,filter-ranges : <start length> Starting address and length of window to
|
||||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
|
||||
- arm,io-coherent : indicates that the system is operating in an hardware
|
||||
I/O coherent mode. Valid only when the arm,pl310-cache compatible
|
||||
string is used.
|
||||
- interrupts : 1 combined interrupt.
|
||||
- cache-size : specifies the size in bytes of the cache
|
||||
- cache-sets : specifies the number of associativity sets of the cache
|
||||
- cache-block-size : specifies the size in bytes of a cache block
|
||||
- cache-line-size : specifies the size in bytes of a line in the cache,
|
||||
if this is not specified, the line size is assumed to be equal to the
|
||||
cache block size
|
||||
- cache-id-part: cache id part number to be used if it is not present
|
||||
on hardware
|
||||
- wt-override: If present then L2 is forced to Write through mode
|
||||
- arm,double-linefill : Override double linefill enable setting. Enable if
|
||||
non-zero, disable if zero.
|
||||
- arm,double-linefill-incr : Override double linefill on INCR read. Enable
|
||||
if non-zero, disable if zero.
|
||||
- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
|
||||
if non-zero, disable if zero.
|
||||
- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
|
||||
disable if zero.
|
||||
- arm,prefetch-offset : Override prefetch offset value. Valid values are
|
||||
0-7, 15, 23, and 31.
|
||||
- arm,shared-override : The default behavior of the L220 or PL310 cache
|
||||
controllers with respect to the shareable attribute is to transform "normal
|
||||
memory non-cacheable transactions" into "cacheable no allocate" (for reads)
|
||||
or "write through no write allocate" (for writes).
|
||||
On systems where this may cause DMA buffer corruption, this property must be
|
||||
specified to indicate that such transforms are precluded.
|
||||
- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
|
||||
- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
|
||||
- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
|
||||
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
|
||||
will randomly hang unless outer sync operations are disabled.
|
||||
- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
|
||||
(forcibly enable), property absent (retain settings set by firmware)
|
||||
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)
|
||||
- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero
|
||||
write (PL310)
|
||||
|
||||
Example:
|
||||
|
||||
L2: cache-controller {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfff12000 0x1000>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <2 2 2>;
|
||||
arm,filter-ranges = <0x80000000 0x8000000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
interrupts = <45>;
|
||||
};
|
||||
|
||||
Note 1: The description in this document doesn't apply to integrated L2
|
||||
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
|
||||
integrated L2 controllers are assumed to be all preconfigured by
|
||||
early secure boot code. Thus no need to deal with their configuration
|
||||
in the kernel at all.
|
||||
248
Bindings/arm/l2c2x0.yaml
Normal file
248
Bindings/arm/l2c2x0.yaml
Normal file
@ -0,0 +1,248 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM L2 Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description: |+
|
||||
ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
|
||||
PL220/PL310 and variants) based level 2 cache controller. All these various
|
||||
implementations of the L2 cache controller have compatible programming
|
||||
models (Note 1). Some of the properties that are just prefixed "cache-*" are
|
||||
taken from section 3.7.3 of the Devicetree Specification which can be found
|
||||
at:
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
Note 1: The description in this document doesn't apply to integrated L2
|
||||
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
|
||||
integrated L2 controllers are assumed to be all preconfigured by
|
||||
early secure boot code. Thus no need to deal with their configuration
|
||||
in the kernel at all.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,pl310-cache
|
||||
- arm,l220-cache
|
||||
- arm,l210-cache
|
||||
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
|
||||
- bcm,bcm11351-a2-pl310-cache
|
||||
# For Broadcom bcm11351 chipset where an
|
||||
# offset needs to be added to the address before passing down to the L2
|
||||
# cache controller
|
||||
- brcm,bcm11351-a2-pl310-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one, with system cache mode (meaning
|
||||
# maintenance operations on L1 are broadcasted to the L2 and L2
|
||||
# performs the same operation).
|
||||
- marvell,aurora-system-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one with outer cache mode.
|
||||
- marvell,aurora-outer-cache
|
||||
# Marvell Tauros3 cache controller, compatible
|
||||
# with arm,pl310-cache controller.
|
||||
- marvell,tauros3-cache
|
||||
|
||||
cache-level:
|
||||
const: 2
|
||||
|
||||
cache-unified: true
|
||||
cache-size: true
|
||||
cache-sets: true
|
||||
cache-block-size: true
|
||||
cache-line-size: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
arm,data-latency:
|
||||
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Minimum valid values are 1. Controllers
|
||||
without setup latency control should use a value of 0.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,tag-latency:
|
||||
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Controllers without setup latency control
|
||||
should use 0. Controllers without separate read and write Tag RAM latency
|
||||
values should only use the first cell.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,dirty-latency:
|
||||
description: Cycles of latency for Dirty RAMs. This is a single cell.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 1
|
||||
maximum: 8
|
||||
|
||||
arm,filter-ranges:
|
||||
description: <start length> Starting address and length of window to
|
||||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
arm,io-coherent:
|
||||
description: indicates that the system is operating in an hardware
|
||||
I/O coherent mode. Valid only when the arm,pl310-cache compatible
|
||||
string is used.
|
||||
type: boolean
|
||||
|
||||
interrupts:
|
||||
# Either a single combined interrupt or up to 9 individual interrupts
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
cache-id-part:
|
||||
description: cache id part number to be used if it is not present
|
||||
on hardware
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
wt-override:
|
||||
description: If present then L2 is forced to Write through mode
|
||||
type: boolean
|
||||
|
||||
arm,double-linefill:
|
||||
description: Override double linefill enable setting. Enable if
|
||||
non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,double-linefill-incr:
|
||||
description: Override double linefill on INCR read. Enable
|
||||
if non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,double-linefill-wrap:
|
||||
description: Override double linefill on WRAP read. Enable
|
||||
if non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,prefetch-drop:
|
||||
description: Override prefetch drop enable setting. Enable if non-zero,
|
||||
disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,prefetch-offset:
|
||||
description: Override prefetch offset value.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ]
|
||||
|
||||
arm,shared-override:
|
||||
description: The default behavior of the L220 or PL310 cache
|
||||
controllers with respect to the shareable attribute is to transform "normal
|
||||
memory non-cacheable transactions" into "cacheable no allocate" (for reads)
|
||||
or "write through no write allocate" (for writes).
|
||||
On systems where this may cause DMA buffer corruption, this property must
|
||||
be specified to indicate that such transforms are precluded.
|
||||
type: boolean
|
||||
|
||||
arm,parity-enable:
|
||||
description: enable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
arm,parity-disable:
|
||||
description: disable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
arm,outer-sync-disable:
|
||||
description: disable the outer sync operation on the L2 cache.
|
||||
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
|
||||
will randomly hang unless outer sync operations are disabled.
|
||||
type: boolean
|
||||
|
||||
prefetch-data:
|
||||
description: |
|
||||
Data prefetch. Value: <0> (forcibly disable), <1>
|
||||
(forcibly enable), property absent (retain settings set by firmware)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
prefetch-instr:
|
||||
description: |
|
||||
Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,dynamic-clock-gating:
|
||||
description: |
|
||||
L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,standby-mode:
|
||||
description: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,early-bresp-disable:
|
||||
description: Disable the CA9 optimization Early BRESP (PL310)
|
||||
type: boolean
|
||||
|
||||
arm,full-line-zero-disable:
|
||||
description: Disable the CA9 optimization Full line of zero
|
||||
write (PL310)
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- cache-unified
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cache-controller@fff12000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfff12000 0x1000>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <2 2 2>;
|
||||
arm,filter-ranges = <0x80000000 0x8000000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
interrupts = <45>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -15,11 +15,12 @@ compatible: Must contain one of
|
||||
"mediatek,mt6795"
|
||||
"mediatek,mt6797"
|
||||
"mediatek,mt7622"
|
||||
"mediatek,mt7623" which is referred to MT7623N SoC
|
||||
"mediatek,mt7623a"
|
||||
"mediatek,mt7623"
|
||||
"mediatek,mt7629"
|
||||
"mediatek,mt8127"
|
||||
"mediatek,mt8135"
|
||||
"mediatek,mt8173"
|
||||
"mediatek,mt8183"
|
||||
|
||||
|
||||
Supported boards:
|
||||
@ -57,6 +58,9 @@ Supported boards:
|
||||
- Reference board variant 1 for MT7622:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
|
||||
- Bananapi BPI-R64 for MT7622:
|
||||
Required root node properties:
|
||||
- compatible = "bananapi,bpi-r64", "mediatek,mt7622";
|
||||
- Reference board for MT7623a with eMMC:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
|
||||
@ -68,6 +72,9 @@ Supported boards:
|
||||
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
|
||||
- Bananapi BPI-R2 board:
|
||||
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
|
||||
- Reference board for MT7629:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
|
||||
- MTK mt8127 tablet moose EVB:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
|
||||
@ -77,3 +84,6 @@ Supported boards:
|
||||
- MTK mt8173 tablet EVB:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
|
||||
- Evaluation board for MT8183:
|
||||
Required root node properties:
|
||||
- compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
Olimex Device Tree Bindings
|
||||
---------------------------
|
||||
|
||||
SAM9-L9260 Board
|
||||
Required root node properties:
|
||||
- compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
|
||||
|
||||
i.MX23 Olinuxino Low Cost Board
|
||||
Required root node properties:
|
||||
- compatible = "olimex,imx23-olinuxino", "fsl,imx23";
|
||||
@ -1,70 +0,0 @@
|
||||
* ARM Performance Monitor Units
|
||||
|
||||
ARM cores often have a PMU for counting cpu and cache events like cache misses
|
||||
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
|
||||
representation in the device tree should be done as under:-
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be one of
|
||||
"apm,potenza-pmu"
|
||||
"arm,armv8-pmuv3"
|
||||
"arm,cortex-a73-pmu"
|
||||
"arm,cortex-a72-pmu"
|
||||
"arm,cortex-a57-pmu"
|
||||
"arm,cortex-a53-pmu"
|
||||
"arm,cortex-a35-pmu"
|
||||
"arm,cortex-a17-pmu"
|
||||
"arm,cortex-a15-pmu"
|
||||
"arm,cortex-a12-pmu"
|
||||
"arm,cortex-a9-pmu"
|
||||
"arm,cortex-a8-pmu"
|
||||
"arm,cortex-a7-pmu"
|
||||
"arm,cortex-a5-pmu"
|
||||
"arm,arm11mpcore-pmu"
|
||||
"arm,arm1176-pmu"
|
||||
"arm,arm1136-pmu"
|
||||
"brcm,vulcan-pmu"
|
||||
"cavium,thunder-pmu"
|
||||
"qcom,scorpion-pmu"
|
||||
"qcom,scorpion-mp-pmu"
|
||||
"qcom,krait-pmu"
|
||||
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
|
||||
interrupt (PPI) then 1 interrupt should be specified.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
|
||||
nodes corresponding directly to the affinity of
|
||||
the SPIs listed in the interrupts property.
|
||||
|
||||
When using a PPI, specifies a list of phandles to CPU
|
||||
nodes corresponding to the set of CPUs which have
|
||||
a PMU of this type signalling the PPI listed in the
|
||||
interrupts property, unless this is already specified
|
||||
by the PPI interrupt specifier itself (in which case
|
||||
the interrupt-affinity property shouldn't be present).
|
||||
|
||||
This property should be present when there is more than
|
||||
a single SPI.
|
||||
|
||||
|
||||
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
|
||||
events.
|
||||
|
||||
- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
|
||||
(SDER) is accessible. This will cause the driver to do
|
||||
any setup required that is only possible in ARMv7 secure
|
||||
state. If not present the ARMv7 SDER will not be touched,
|
||||
which means the PMU may fail to operate unless external
|
||||
code (bootloader or security monitor) has performed the
|
||||
appropriate initialisation. Note that this property is
|
||||
not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
|
||||
in Non-secure state.
|
||||
|
||||
Example:
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <100 101>;
|
||||
};
|
||||
87
Bindings/arm/pmu.yaml
Normal file
87
Bindings/arm/pmu.yaml
Normal file
@ -0,0 +1,87 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/pmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Performance Monitor Units
|
||||
|
||||
maintainers:
|
||||
- Mark Rutland <mark.rutland@arm.com>
|
||||
- Will Deacon <will.deacon@arm.com>
|
||||
|
||||
description: |+
|
||||
ARM cores often have a PMU for counting cpu and cache events like cache misses
|
||||
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
|
||||
representation in the device tree should be done as under:-
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apm,potenza-pmu
|
||||
- arm,armv8-pmuv3
|
||||
- arm,cortex-a73-pmu
|
||||
- arm,cortex-a72-pmu
|
||||
- arm,cortex-a57-pmu
|
||||
- arm,cortex-a53-pmu
|
||||
- arm,cortex-a35-pmu
|
||||
- arm,cortex-a17-pmu
|
||||
- arm,cortex-a15-pmu
|
||||
- arm,cortex-a12-pmu
|
||||
- arm,cortex-a9-pmu
|
||||
- arm,cortex-a8-pmu
|
||||
- arm,cortex-a7-pmu
|
||||
- arm,cortex-a5-pmu
|
||||
- arm,arm11mpcore-pmu
|
||||
- arm,arm1176-pmu
|
||||
- arm,arm1136-pmu
|
||||
- brcm,vulcan-pmu
|
||||
- cavium,thunder-pmu
|
||||
- qcom,scorpion-pmu
|
||||
- qcom,scorpion-mp-pmu
|
||||
- qcom,krait-pmu
|
||||
|
||||
interrupts:
|
||||
# Don't know how many CPUs, so no constraints to specify
|
||||
description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
|
||||
|
||||
interrupt-affinity:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
When using SPIs, specifies a list of phandles to CPU
|
||||
nodes corresponding directly to the affinity of
|
||||
the SPIs listed in the interrupts property.
|
||||
|
||||
When using a PPI, specifies a list of phandles to CPU
|
||||
nodes corresponding to the set of CPUs which have
|
||||
a PMU of this type signalling the PPI listed in the
|
||||
interrupts property, unless this is already specified
|
||||
by the PPI interrupt specifier itself (in which case
|
||||
the interrupt-affinity property shouldn't be present).
|
||||
|
||||
This property should be present when there is more than
|
||||
a single SPI.
|
||||
|
||||
qcom,no-pc-write:
|
||||
type: boolean
|
||||
description:
|
||||
Indicates that this PMU doesn't support the 0xc and 0xd events.
|
||||
|
||||
secure-reg-access:
|
||||
type: boolean
|
||||
description:
|
||||
Indicates that the ARMv7 Secure Debug Enable Register
|
||||
(SDER) is accessible. This will cause the driver to do
|
||||
any setup required that is only possible in ARMv7 secure
|
||||
state. If not present the ARMv7 SDER will not be touched,
|
||||
which means the PMU may fail to operate unless external
|
||||
code (bootloader or security monitor) has performed the
|
||||
appropriate initialisation. Note that this property is
|
||||
not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
|
||||
in Non-secure state.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
...
|
||||
238
Bindings/arm/renesas.yaml
Normal file
238
Bindings/arm/renesas.yaml
Normal file
@ -0,0 +1,238 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/shmobile.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Emma Mobile EV2
|
||||
items:
|
||||
- enum:
|
||||
- renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual
|
||||
- const: renesas,emev2
|
||||
|
||||
- description: RZ/A1H (R7S72100)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,genmai # Genmai (RTK772100BC00000BR)
|
||||
- renesas,gr-peach # GR-Peach (X28A-M01-E/F)
|
||||
- renesas,rskrza1 # RSKRZA1 (YR0K77210C000BE)
|
||||
- const: renesas,r7s72100
|
||||
|
||||
- description: RZ/A2 (R7S9210)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,rza2mevb # RZ/A2M Eval Board (RTK7921053S00000BE)
|
||||
- const: renesas,r7s9210
|
||||
|
||||
- description: SH-Mobile AG5 (R8A73A00/SH73A0)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,kzm9g # Kyoto Microcomputer Co. KZM-A9-GT
|
||||
- const: renesas,sh73a0
|
||||
|
||||
- description: R-Mobile APE6 (R8A73A40)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,ape6evm
|
||||
- const: renesas,r8a73a4
|
||||
|
||||
- description: R-Mobile A1 (R8A77400)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,armadillo800eva # Atmark Techno Armadillo-800 EVA
|
||||
- const: renesas,r8a7740
|
||||
|
||||
- description: RZ/G1H (R8A77420)
|
||||
items:
|
||||
- const: renesas,r8a7742
|
||||
|
||||
- description: RZ/G1M (R8A77430)
|
||||
items:
|
||||
- enum:
|
||||
# iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
|
||||
- iwave,g20d
|
||||
- const: iwave,g20m
|
||||
- const: renesas,r8a7743
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
# iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
|
||||
- iwave,g20m
|
||||
- renesas,sk-rzg1m # SK-RZG1M (YR8A77430S000BE)
|
||||
- const: renesas,r8a7743
|
||||
|
||||
- description: RZ/G1N (R8A77440)
|
||||
items:
|
||||
- enum:
|
||||
# iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven)
|
||||
- iwave,g20d
|
||||
- const: iwave,g20m
|
||||
- const: renesas,r8a7744
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
# iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
|
||||
- iwave,g20m
|
||||
- const: renesas,r8a7744
|
||||
|
||||
- description: RZ/G1E (R8A77450)
|
||||
items:
|
||||
- enum:
|
||||
- iwave,g22m # iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
|
||||
- renesas,sk-rzg1e # SK-RZG1E (YR8A77450S000BE)
|
||||
- const: renesas,r8a7745
|
||||
|
||||
- description: iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
|
||||
items:
|
||||
- const: iwave,g22d
|
||||
- const: iwave,g22m
|
||||
- const: renesas,r8a7745
|
||||
|
||||
- description: RZ/G1C (R8A77470)
|
||||
items:
|
||||
- enum:
|
||||
- iwave,g23s #iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
|
||||
- const: renesas,r8a77470
|
||||
|
||||
- description: RZ/G2M (R8A774A1)
|
||||
items:
|
||||
- const: renesas,r8a774a1
|
||||
|
||||
- description: RZ/G2E (R8A774C0)
|
||||
items:
|
||||
- enum:
|
||||
- si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874)
|
||||
- const: renesas,r8a774c0
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875)
|
||||
- const: si-linux,cat874
|
||||
- const: renesas,r8a774c0
|
||||
|
||||
- description: R-Car M1A (R8A77781)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,bockw
|
||||
- const: renesas,r8a7778
|
||||
|
||||
- description: R-Car H1 (R8A77790)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,marzen # Marzen (R0P7779A00010S)
|
||||
- const: renesas,r8a7779
|
||||
|
||||
- description: R-Car H2 (R8A77900)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,lager # Lager (RTP0RC7790SEB00010S)
|
||||
- renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
|
||||
- const: renesas,r8a7790
|
||||
|
||||
- description: R-Car M2-W (R8A77910)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,henninger
|
||||
- renesas,koelsch # Koelsch (RTP0RC7791SEB00010S)
|
||||
- renesas,porter # Porter (M2-LCDP)
|
||||
- const: renesas,r8a7791
|
||||
|
||||
- description: R-Car V2H (R8A77920)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,blanche # Blanche (RTP0RC7792SEB00010S)
|
||||
- renesas,wheat # Wheat (RTP0RC7792ASKB0000JE)
|
||||
- const: renesas,r8a7792
|
||||
|
||||
- description: R-Car M2-N (R8A77930)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,gose # Gose (RTP0RC7793SEB00010S)
|
||||
- const: renesas,r8a7793
|
||||
|
||||
- description: R-Car E2 (R8A77940)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,alt # Alt (RTP0RC7794SEB00010S)
|
||||
- renesas,silk # SILK (RTP0RC7794LCB00011S)
|
||||
- const: renesas,r8a7794
|
||||
|
||||
- description: R-Car H3 (R8A77950)
|
||||
items:
|
||||
- enum:
|
||||
# H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
|
||||
# H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
|
||||
- renesas,h3ulcb
|
||||
- renesas,salvator-x # Salvator-X (RTP0RC7795SIPB0010S)
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
|
||||
- const: renesas,r8a7795
|
||||
|
||||
- description: R-Car M3-W (R8A77960)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
|
||||
- renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S)
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
|
||||
- const: renesas,r8a7796
|
||||
|
||||
- description: Kingfisher (SBEV-RCAR-KF-M03)
|
||||
items:
|
||||
- const: shimafuji,kingfisher
|
||||
- enum:
|
||||
- renesas,h3ulcb
|
||||
- renesas,m3ulcb
|
||||
- enum:
|
||||
- renesas,r8a7795
|
||||
- renesas,r8a7796
|
||||
|
||||
- description: R-Car M3-N (R8A77965)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
|
||||
- renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S (M3-N))
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
|
||||
- const: renesas,r8a77965
|
||||
|
||||
- description: R-Car V3M (R8A77970)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,eagle # Eagle (RTP0RC77970SEB0010S)
|
||||
- renesas,v3msk # V3MSK (Y-ASK-RCAR-V3M-WS10)
|
||||
- const: renesas,r8a77970
|
||||
|
||||
- description: R-Car V3H (R8A77980)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,condor # Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
|
||||
- renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10)
|
||||
- const: renesas,r8a77980
|
||||
|
||||
- description: R-Car E3 (R8A77990)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,ebisu # Ebisu (RTP0RC77990SEB0010S)
|
||||
- const: renesas,r8a77990
|
||||
|
||||
- description: R-Car D3 (R8A77995)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,draak # Draak (RTP0RC77995SEB0010S)
|
||||
- const: renesas,r8a77995
|
||||
|
||||
- description: RZ/N1D (R9A06G032)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
|
||||
- const: renesas,r9a06g032
|
||||
|
||||
...
|
||||
@ -60,6 +60,11 @@ properties:
|
||||
- const: chipspark,rayeager-px2
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: Elgin RV1108 R1
|
||||
items:
|
||||
- const: elgin,rv1108-r1
|
||||
- const: rockchip,rv1108
|
||||
|
||||
- description: Firefly Firefly-RK3288
|
||||
items:
|
||||
- enum:
|
||||
@ -87,6 +92,13 @@ properties:
|
||||
- const: firefly,roc-rk3399-pc
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: FriendlyElec NanoPi4 series boards
|
||||
items:
|
||||
- enum:
|
||||
- friendlyarm,nanopc-t4
|
||||
- friendlyarm,nanopi-m4
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: GeekBuying GeekBox
|
||||
items:
|
||||
- const: geekbuying,geekbox
|
||||
@ -317,6 +329,11 @@ properties:
|
||||
- const: radxa,rock
|
||||
- const: rockchip,rk3188
|
||||
|
||||
- description: Radxa ROCK Pi 4
|
||||
items:
|
||||
- const: radxa,rockpi4
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Radxa Rock2 Square
|
||||
items:
|
||||
- const: radxa,rock2-square
|
||||
|
||||
@ -1,155 +0,0 @@
|
||||
Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
|
||||
--------------------------------------------------------------------
|
||||
|
||||
SoCs:
|
||||
|
||||
- Emma Mobile EV2
|
||||
compatible = "renesas,emev2"
|
||||
- RZ/A1H (R7S72100)
|
||||
compatible = "renesas,r7s72100"
|
||||
- RZ/A2 (R7S9210)
|
||||
compatible = "renesas,r7s9210"
|
||||
- SH-Mobile AG5 (R8A73A00/SH73A0)
|
||||
compatible = "renesas,sh73a0"
|
||||
- R-Mobile APE6 (R8A73A40)
|
||||
compatible = "renesas,r8a73a4"
|
||||
- R-Mobile A1 (R8A77400)
|
||||
compatible = "renesas,r8a7740"
|
||||
- RZ/G1H (R8A77420)
|
||||
compatible = "renesas,r8a7742"
|
||||
- RZ/G1M (R8A77430)
|
||||
compatible = "renesas,r8a7743"
|
||||
- RZ/G1N (R8A77440)
|
||||
compatible = "renesas,r8a7744"
|
||||
- RZ/G1E (R8A77450)
|
||||
compatible = "renesas,r8a7745"
|
||||
- RZ/G1C (R8A77470)
|
||||
compatible = "renesas,r8a77470"
|
||||
- RZ/G2M (R8A774A1)
|
||||
compatible = "renesas,r8a774a1"
|
||||
- RZ/G2E (R8A774C0)
|
||||
compatible = "renesas,r8a774c0"
|
||||
- R-Car M1A (R8A77781)
|
||||
compatible = "renesas,r8a7778"
|
||||
- R-Car H1 (R8A77790)
|
||||
compatible = "renesas,r8a7779"
|
||||
- R-Car H2 (R8A77900)
|
||||
compatible = "renesas,r8a7790"
|
||||
- R-Car M2-W (R8A77910)
|
||||
compatible = "renesas,r8a7791"
|
||||
- R-Car V2H (R8A77920)
|
||||
compatible = "renesas,r8a7792"
|
||||
- R-Car M2-N (R8A77930)
|
||||
compatible = "renesas,r8a7793"
|
||||
- R-Car E2 (R8A77940)
|
||||
compatible = "renesas,r8a7794"
|
||||
- R-Car H3 (R8A77950)
|
||||
compatible = "renesas,r8a7795"
|
||||
- R-Car M3-W (R8A77960)
|
||||
compatible = "renesas,r8a7796"
|
||||
- R-Car M3-N (R8A77965)
|
||||
compatible = "renesas,r8a77965"
|
||||
- R-Car V3M (R8A77970)
|
||||
compatible = "renesas,r8a77970"
|
||||
- R-Car V3H (R8A77980)
|
||||
compatible = "renesas,r8a77980"
|
||||
- R-Car E3 (R8A77990)
|
||||
compatible = "renesas,r8a77990"
|
||||
- R-Car D3 (R8A77995)
|
||||
compatible = "renesas,r8a77995"
|
||||
- RZ/N1D (R9A06G032)
|
||||
compatible = "renesas,r9a06g032"
|
||||
|
||||
Boards:
|
||||
|
||||
- Alt (RTP0RC7794SEB00010S)
|
||||
compatible = "renesas,alt", "renesas,r8a7794"
|
||||
- APE6-EVM
|
||||
compatible = "renesas,ape6evm", "renesas,r8a73a4"
|
||||
- Atmark Techno Armadillo-800 EVA
|
||||
compatible = "renesas,armadillo800eva", "renesas,r8a7740"
|
||||
- Blanche (RTP0RC7792SEB00010S)
|
||||
compatible = "renesas,blanche", "renesas,r8a7792"
|
||||
- BOCK-W
|
||||
compatible = "renesas,bockw", "renesas,r8a7778"
|
||||
- Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
|
||||
compatible = "renesas,condor", "renesas,r8a77980"
|
||||
- Draak (RTP0RC77995SEB0010S)
|
||||
compatible = "renesas,draak", "renesas,r8a77995"
|
||||
- Eagle (RTP0RC77970SEB0010S)
|
||||
compatible = "renesas,eagle", "renesas,r8a77970"
|
||||
- Ebisu (RTP0RC77990SEB0010S)
|
||||
compatible = "renesas,ebisu", "renesas,r8a77990"
|
||||
- Genmai (RTK772100BC00000BR)
|
||||
compatible = "renesas,genmai", "renesas,r7s72100"
|
||||
- GR-Peach (X28A-M01-E/F)
|
||||
compatible = "renesas,gr-peach", "renesas,r7s72100"
|
||||
- Gose (RTP0RC7793SEB00010S)
|
||||
compatible = "renesas,gose", "renesas,r8a7793"
|
||||
- H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
|
||||
H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
|
||||
compatible = "renesas,h3ulcb", "renesas,r8a7795"
|
||||
- Henninger
|
||||
compatible = "renesas,henninger", "renesas,r8a7791"
|
||||
- iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
|
||||
compatible = "iwave,g23s", "renesas,r8a77470"
|
||||
- iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
|
||||
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
|
||||
- iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
|
||||
compatible = "iwave,g22m", "renesas,r8a7745"
|
||||
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
|
||||
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
|
||||
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
|
||||
compatible = "iwave,g20m", "renesas,r8a7743"
|
||||
- iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven)
|
||||
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"
|
||||
- iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
|
||||
compatible = "iwave,g20m", "renesas,r8a7744"
|
||||
- Kingfisher (SBEV-RCAR-KF-M03)
|
||||
compatible = "shimafuji,kingfisher"
|
||||
- Koelsch (RTP0RC7791SEB00010S)
|
||||
compatible = "renesas,koelsch", "renesas,r8a7791"
|
||||
- Kyoto Microcomputer Co. KZM-A9-Dual
|
||||
compatible = "renesas,kzm9d", "renesas,emev2"
|
||||
- Kyoto Microcomputer Co. KZM-A9-GT
|
||||
compatible = "renesas,kzm9g", "renesas,sh73a0"
|
||||
- Lager (RTP0RC7790SEB00010S)
|
||||
compatible = "renesas,lager", "renesas,r8a7790"
|
||||
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
|
||||
compatible = "renesas,m3ulcb", "renesas,r8a7796"
|
||||
- M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
|
||||
compatible = "renesas,m3nulcb", "renesas,r8a77965"
|
||||
- Marzen (R0P7779A00010S)
|
||||
compatible = "renesas,marzen", "renesas,r8a7779"
|
||||
- Porter (M2-LCDP)
|
||||
compatible = "renesas,porter", "renesas,r8a7791"
|
||||
- RSKRZA1 (YR0K77210C000BE)
|
||||
compatible = "renesas,rskrza1", "renesas,r7s72100"
|
||||
- RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
|
||||
compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
|
||||
- Salvator-X (RTP0RC7795SIPB0010S)
|
||||
compatible = "renesas,salvator-x", "renesas,r8a7795"
|
||||
- Salvator-X (RTP0RC7796SIPB0011S)
|
||||
compatible = "renesas,salvator-x", "renesas,r8a7796"
|
||||
- Salvator-X (RTP0RC7796SIPB0011S (M3-N))
|
||||
compatible = "renesas,salvator-x", "renesas,r8a77965"
|
||||
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
|
||||
compatible = "renesas,salvator-xs", "renesas,r8a7795"
|
||||
- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
|
||||
compatible = "renesas,salvator-xs", "renesas,r8a7796"
|
||||
- Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
|
||||
compatible = "renesas,salvator-xs", "renesas,r8a77965"
|
||||
- SILK (RTP0RC7794LCB00011S)
|
||||
compatible = "renesas,silk", "renesas,r8a7794"
|
||||
- SK-RZG1E (YR8A77450S000BE)
|
||||
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
|
||||
- SK-RZG1M (YR8A77430S000BE)
|
||||
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
|
||||
- Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
|
||||
compatible = "renesas,stout", "renesas,r8a7790"
|
||||
- V3HSK (Y-ASK-RCAR-V3H-WS10)
|
||||
compatible = "renesas,v3hsk", "renesas,r8a77980"
|
||||
- V3MSK (Y-ASK-RCAR-V3M-WS10)
|
||||
compatible = "renesas,v3msk", "renesas,r8a77970"
|
||||
- Wheat (RTP0RC7792ASKB0000JE)
|
||||
compatible = "renesas,wheat", "renesas,r8a7792"
|
||||
22
Bindings/arm/socionext/milbeaut.yaml
Normal file
22
Bindings/arm/socionext/milbeaut.yaml
Normal file
@ -0,0 +1,22 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/milbeaut.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Milbeaut platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Taichi Sugaya <sugaya.taichi@socionext.com>
|
||||
- Takao Orito <orito.takao@socionext.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- socionext,milbeaut-m10v-evb
|
||||
- const: socionext,sc2000a
|
||||
...
|
||||
@ -1,23 +0,0 @@
|
||||
Technologic Systems Platforms Device Tree Bindings
|
||||
--------------------------------------------------
|
||||
|
||||
TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip.
|
||||
It can be mounted on a carrier board providing additional peripheral connectors.
|
||||
Required root node properties:
|
||||
- compatible = "technologic,imx28-ts4600", "fsl,imx28"
|
||||
|
||||
TS-4800 board
|
||||
Required root node properties:
|
||||
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
|
||||
|
||||
TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
|
||||
It can be mounted on a carrier board providing additional peripheral connectors.
|
||||
Required root node properties:
|
||||
- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
|
||||
- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
|
||||
|
||||
TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
|
||||
It can be mounted on a carrier board providing additional peripheral connectors.
|
||||
Required root node properties:
|
||||
- compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"
|
||||
- compatible = "technologic,imx6q-ts7970", "fsl,imx6q"
|
||||
@ -87,9 +87,11 @@ properties:
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,darcy
|
||||
- nvidia,p2371-0000
|
||||
- nvidia,p2371-2180
|
||||
- nvidia,p2571
|
||||
- nvidia,p2894-0050-a08
|
||||
- const: nvidia,tegra210
|
||||
- items:
|
||||
- enum:
|
||||
|
||||
@ -47,9 +47,9 @@ Optional properties:
|
||||
Timing property for child nodes. It is mandatory, not optional.
|
||||
|
||||
- fsl,weim-cs-timing: The timing array, contains timing values for the
|
||||
child node. We can get the CS index from the child
|
||||
node's "reg" property. The number of registers depends
|
||||
on the selected chip.
|
||||
child node. We get the CS indexes from the address
|
||||
ranges in the child node's "reg" property.
|
||||
The number of registers depends on the selected chip:
|
||||
For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
|
||||
registers: CSxU, CSxL.
|
||||
For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
|
||||
@ -80,3 +80,29 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
|
||||
0x0000c000 0x1404a38e 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
|
||||
|
||||
In this case, both chip select 0 and 1 will be configured with the same timing
|
||||
array values.
|
||||
|
||||
weim: weim@21b8000 {
|
||||
compatible = "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
clocks = <&clks 196>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x02000000
|
||||
1 0 0x0a000000 0x02000000
|
||||
2 0 0x0c000000 0x02000000
|
||||
3 0 0x0e000000 0x02000000>;
|
||||
fsl,weim-cs-gpr = <&gpr>;
|
||||
|
||||
acme@0 {
|
||||
compatible = "acme,whatever";
|
||||
reg = <0 0 0x100>, <0 0x400000 0x800>,
|
||||
<1 0x400000 0x800>;
|
||||
fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
|
||||
0x00000000 0xa0000240 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -2,13 +2,14 @@
|
||||
|
||||
The Actions Semi Owl Clock Management Unit generates and supplies clock
|
||||
to various controllers within the SoC. The clock binding described here is
|
||||
applicable to S900 and S700 SoC's.
|
||||
applicable to S900, S700 and S500 SoC's.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following,
|
||||
"actions,s900-cmu"
|
||||
"actions,s700-cmu"
|
||||
"actions,s500-cmu"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: Reference to the parent clocks ("hosc", "losc")
|
||||
@ -19,8 +20,8 @@ Each clock is assigned an identifier, and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in corresponding
|
||||
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be
|
||||
used in device tree sources.
|
||||
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
|
||||
actions,s500-cmu.h header and can be used in device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
|
||||
@ -10,6 +10,7 @@ Required Properties:
|
||||
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
|
||||
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
|
||||
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
|
||||
- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
|
||||
followed by the common "amlogic,meson-gx-aoclkc"
|
||||
- clocks: list of clock phandle, one for each entry clock-names.
|
||||
- clock-names: should contain the following:
|
||||
|
||||
@ -9,6 +9,7 @@ Required Properties:
|
||||
"amlogic,gxbb-clkc" for GXBB SoC,
|
||||
"amlogic,gxl-clkc" for GXL and GXM SoC,
|
||||
"amlogic,axg-clkc" for AXG SoC.
|
||||
"amlogic,g12a-clkc" for G12A SoC.
|
||||
- clocks : list of clock phandle, one for each entry clock-names.
|
||||
- clock-names : should contain the following:
|
||||
* "xtal": the platform xtal
|
||||
|
||||
@ -50,6 +50,8 @@ Required Properties:
|
||||
IPs.
|
||||
- "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
|
||||
which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
|
||||
- "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
|
||||
which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
@ -168,6 +170,12 @@ Required Properties:
|
||||
- aclk_cam1_400
|
||||
- aclk_cam1_552
|
||||
|
||||
Input clocks for imem clock controller:
|
||||
- oscclk
|
||||
- aclk_imem_sssx_266
|
||||
- aclk_imem_266
|
||||
- aclk_imem_200
|
||||
|
||||
Optional properties:
|
||||
- power-domains: a phandle to respective power domain node as described by
|
||||
generic PM domain bindings (see power/power_domain.txt for more
|
||||
@ -469,6 +477,21 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
power-domains = <&pd_cam1>;
|
||||
};
|
||||
|
||||
cmu_imem: clock-controller@11060000 {
|
||||
compatible = "samsung,exynos5433-cmu-imem";
|
||||
reg = <0x11060000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"aclk_imem_sssx_266",
|
||||
"aclk_imem_266",
|
||||
"aclk_imem_200";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
|
||||
<&cmu_top CLK_DIV_ACLK_IMEM_266>,
|
||||
<&cmu_top CLK_DIV_ACLK_IMEM_200>;
|
||||
};
|
||||
|
||||
Example 3: UART controller node that consumes the clock generated by the clock
|
||||
controller.
|
||||
|
||||
|
||||
@ -1,23 +0,0 @@
|
||||
Binding for simple fixed-rate clock sources.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "fixed-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clock-frequency : frequency of clock in Hz. Should be a single cell.
|
||||
|
||||
Optional properties:
|
||||
- clock-accuracy : accuracy of clock in ppb (parts per billion).
|
||||
Should be a single cell.
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
clock-accuracy = <100>;
|
||||
};
|
||||
44
Bindings/clock/fixed-clock.yaml
Normal file
44
Bindings/clock/fixed-clock.yaml
Normal file
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for simple fixed-rate clock sources
|
||||
|
||||
maintainers:
|
||||
- Michael Turquette <mturquette@baylibre.com>
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fixed-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clock-frequency: true
|
||||
|
||||
clock-accuracy:
|
||||
description: accuracy of clock in ppb (parts per billion).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clock-frequency
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
clock-accuracy = <100>;
|
||||
};
|
||||
...
|
||||
@ -1,28 +0,0 @@
|
||||
Binding for simple fixed factor rate clock sources.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "fixed-factor-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clock-div: fixed divider.
|
||||
- clock-mult: fixed multiplier.
|
||||
- clocks: parent clock.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Some clocks that require special treatments are also handled by that
|
||||
driver, with the compatibles:
|
||||
- allwinner,sun4i-a10-pll3-2x-clk
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
56
Bindings/clock/fixed-factor-clock.yaml
Normal file
56
Bindings/clock/fixed-factor-clock.yaml
Normal file
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for simple fixed factor rate clock sources
|
||||
|
||||
maintainers:
|
||||
- Michael Turquette <mturquette@baylibre.com>
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-pll3-2x-clk
|
||||
- fixed-factor-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-div:
|
||||
description: Fixed divider
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 1
|
||||
|
||||
clock-mult:
|
||||
description: Fixed multiplier
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
- clock-div
|
||||
- clock-mult
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
...
|
||||
24
Bindings/clock/fixed-mmio-clock.txt
Normal file
24
Bindings/clock/fixed-mmio-clock.txt
Normal file
@ -0,0 +1,24 @@
|
||||
Binding for simple memory mapped io fixed-rate clock sources.
|
||||
The driver reads a clock frequency value from a single 32-bit memory mapped
|
||||
I/O register and registers it as a fixed rate clock.
|
||||
|
||||
It was designed for test systems, like FPGA, not for complete, finished SoCs.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "fixed-mmio-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- reg : Address and length of the clock value register set.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
sysclock: sysclock@fd020004 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-mmio-clock";
|
||||
reg = <0xfd020004 0x4>;
|
||||
};
|
||||
29
Bindings/clock/imx8mm-clock.txt
Normal file
29
Bindings/clock/imx8mm-clock.txt
Normal file
@ -0,0 +1,29 @@
|
||||
* Clock bindings for NXP i.MX8M Mini
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mm-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "osc_32k"
|
||||
- "osc_24m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mm-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
|
||||
for the full list of i.MX8M Mini clock IDs.
|
||||
@ -8,10 +8,11 @@ the fast CPU cluster. It consists of a free-running voltage controlled
|
||||
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
|
||||
control module that will automatically adjust the VDD_CPU voltage by
|
||||
communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
|
||||
Currently only the I2C mode is supported by these bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "nvidia,tegra124-dfll"
|
||||
- compatible : should be one of:
|
||||
- "nvidia,tegra124-dfll": for Tegra124
|
||||
- "nvidia,tegra210-dfll": for Tegra210
|
||||
- reg : Defines the following set of registers, in the order listed:
|
||||
- registers for the DFLL control logic.
|
||||
- registers for the I2C output logic.
|
||||
@ -45,10 +46,31 @@ Required properties for the control loop parameters:
|
||||
Optional properties for the control loop parameters:
|
||||
- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
|
||||
|
||||
Optional properties for mode selection:
|
||||
- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
|
||||
|
||||
Required properties for I2C mode:
|
||||
- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
|
||||
|
||||
Example:
|
||||
Required properties for PWM mode:
|
||||
- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
|
||||
- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
|
||||
control is disabled and the PWM output is tristated. Note that this voltage is
|
||||
configured in hardware, typically via a resistor divider.
|
||||
- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
|
||||
is enabled and PWM output is low. Hence, this is the minimum output voltage
|
||||
that the regulator supports when PWM control is enabled.
|
||||
- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
|
||||
corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
|
||||
duty cycle would be: nvidia,pwm-min-microvolts +
|
||||
nvidia,pwm-voltage-step-microvolts * 2.
|
||||
- pinctrl-0: I/O pad configuration when PWM control is enabled.
|
||||
- pinctrl-1: I/O pad configuration when PWM control is disabled.
|
||||
- pinctrl-names: must include the following entries:
|
||||
- dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
|
||||
- dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
|
||||
|
||||
Example for I2C:
|
||||
|
||||
clock@70110000 {
|
||||
compatible = "nvidia,tegra124-dfll";
|
||||
@ -76,3 +98,58 @@ clock@70110000 {
|
||||
|
||||
nvidia,i2c-fs-rate = <400000>;
|
||||
};
|
||||
|
||||
Example for PWM:
|
||||
|
||||
clock@70110000 {
|
||||
compatible = "nvidia,tegra124-dfll";
|
||||
reg = <0 0x70110000 0 0x100>, /* DFLL control */
|
||||
<0 0x70110000 0 0x100>, /* I2C output control */
|
||||
<0 0x70110100 0 0x100>, /* Integrated I2C controller */
|
||||
<0 0x70110200 0 0x100>; /* Look-up table RAM */
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
|
||||
<&tegra_car TEGRA210_CLK_DFLL_REF>,
|
||||
<&tegra_car TEGRA124_CLK_I2C5>;;
|
||||
clock-names = "soc", "ref", "i2c";
|
||||
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
|
||||
reset-names = "dvco";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "dfllCPU_out";
|
||||
|
||||
nvidia,sample-rate = <25000>;
|
||||
nvidia,droop-ctrl = <0x00000f00>;
|
||||
nvidia,force-mode = <1>;
|
||||
nvidia,cf = <6>;
|
||||
nvidia,ci = <0>;
|
||||
nvidia,cg = <2>;
|
||||
|
||||
nvidia,pwm-min-microvolts = <708000>; /* 708mV */
|
||||
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
|
||||
nvidia,pwm-to-pmic;
|
||||
nvidia,pwm-tristate-microvolts = <1000000>;
|
||||
nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
|
||||
|
||||
pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
|
||||
pinctrl-0 = <&dvfs_pwm_active_state>;
|
||||
pinctrl-1 = <&dvfs_pwm_inactive_state>;
|
||||
};
|
||||
|
||||
/* pinmux nodes added for completeness. Binding doc can be found in:
|
||||
* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
|
||||
*/
|
||||
|
||||
pinmux: pinmux@700008d4 {
|
||||
dvfs_pwm_active_state: dvfs_pwm_active {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -16,6 +16,7 @@ Required properties :
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8998", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
@ -9,11 +9,9 @@ Required properties:
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- cpu_g: Clock mux for the fast CPU cluster.
|
||||
- cpu_lp: Clock mux for the low-power CPU cluster.
|
||||
- pll_x: Fast PLL clocksource.
|
||||
- pll_p: Auxiliary PLL used during fast PLL rate changes.
|
||||
- dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
|
||||
- vdd-cpu-supply: Regulator for CPU voltage
|
||||
|
||||
Optional properties:
|
||||
- clock-latency: Specify the possible maximum transition latency for clock,
|
||||
@ -31,13 +29,11 @@ cpus {
|
||||
reg = <0>;
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
|
||||
<&tegra_car TEGRA124_CLK_CCLK_LP>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_X>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_P>,
|
||||
<&dfll>;
|
||||
clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
|
||||
clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
|
||||
clock-latency = <300000>;
|
||||
vdd-cpu-supply: <&vdd_cpu>;
|
||||
};
|
||||
|
||||
<...>
|
||||
|
||||
19
Bindings/crypto/samsung-slimsss.txt
Normal file
19
Bindings/crypto/samsung-slimsss.txt
Normal file
@ -0,0 +1,19 @@
|
||||
Samsung SoC SlimSSS (Slim Security SubSystem) module
|
||||
|
||||
The SlimSSS module in Exynos5433 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
|
||||
-- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entry for slimSSS version:
|
||||
- "samsung,exynos5433-slim-sss" for Exynos5433 SoC.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SlimSSS module interrupts (one feed
|
||||
control interrupt).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
- clock-names : list of device clock input names; should contain "pclk" and
|
||||
"aclk" for slim-sss in Exynos5433.
|
||||
33
Bindings/display/amlogic,simple-framebuffer.txt
Normal file
33
Bindings/display/amlogic,simple-framebuffer.txt
Normal file
@ -0,0 +1,33 @@
|
||||
Meson specific Simple Framebuffer bindings
|
||||
|
||||
This binding documents meson specific extensions to the simple-framebuffer
|
||||
bindings. The meson simplefb u-boot code relies on the devicetree containing
|
||||
pre-populated simplefb nodes.
|
||||
|
||||
These extensions are intended so that u-boot can select the right node based
|
||||
on which pipeline is being used. As such they are solely intended for
|
||||
firmware / bootloader use, and the OS should ignore them.
|
||||
|
||||
Required properties:
|
||||
- compatible: "amlogic,simple-framebuffer", "simple-framebuffer"
|
||||
- amlogic,pipeline, one of:
|
||||
"vpu-cvbs"
|
||||
"vpu-hdmi"
|
||||
|
||||
Example:
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
simplefb_hdmi: framebuffer-hdmi {
|
||||
compatible = "amlogic,simple-framebuffer",
|
||||
"simple-framebuffer";
|
||||
amlogic,pipeline = "vpu-hdmi";
|
||||
clocks = <&clkc CLKID_HDMI_PCLK>,
|
||||
<&clkc CLKID_CLK81>,
|
||||
<&clkc CLKID_GCLK_VENCI_INT0>;
|
||||
power-domains = <&pwrc_vpu>;
|
||||
};
|
||||
};
|
||||
73
Bindings/display/arm,komeda.txt
Normal file
73
Bindings/display/arm,komeda.txt
Normal file
@ -0,0 +1,73 @@
|
||||
Device Tree bindings for Arm Komeda display driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "arm,mali-d71"
|
||||
- reg: Physical base address and length of the registers in the system
|
||||
- interrupts: the interrupt line number of the device in the system
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each entry
|
||||
in 'clock-names'
|
||||
- clock-names: A list of clock names. It should contain:
|
||||
- "mclk": for the main processor clock
|
||||
- "pclk": for the APB interface clock
|
||||
- #address-cells: Must be 1
|
||||
- #size-cells: Must be 0
|
||||
|
||||
Required properties for sub-node: pipeline@nq
|
||||
Each device contains one or two pipeline sub-nodes (at least one), each
|
||||
pipeline node should provide properties:
|
||||
- reg: Zero-indexed identifier for the pipeline
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each entry
|
||||
in 'clock-names'
|
||||
- clock-names: should contain:
|
||||
- "pxclk": pixel clock
|
||||
- "aclk": AXI interface clock
|
||||
|
||||
- port: each pipeline connect to an encoder input port. The connection is
|
||||
modeled using the OF graph bindings specified in
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
|
||||
Optional properties:
|
||||
- memory-region: phandle to a node describing memory (see
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
|
||||
to be used for the framebuffer; if not present, the framebuffer may
|
||||
be located anywhere in memory.
|
||||
|
||||
Example:
|
||||
/ {
|
||||
...
|
||||
|
||||
dp0: display@c00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "arm,mali-d71";
|
||||
reg = <0xc00000 0x20000>;
|
||||
interrupts = <0 168 4>;
|
||||
clocks = <&dpu_mclk>, <&dpu_aclk>;
|
||||
clock-names = "mclk", "pclk";
|
||||
|
||||
dp0_pipe0: pipeline@0 {
|
||||
clocks = <&fpgaosc2>, <&dpu_aclk>;
|
||||
clock-names = "pxclk", "aclk";
|
||||
reg = <0>;
|
||||
|
||||
port {
|
||||
dp0_pipe0_out: endpoint {
|
||||
remote-endpoint = <&db_dvi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dp0_pipe1: pipeline@1 {
|
||||
clocks = <&fpgaosc2>, <&dpu_aclk>;
|
||||
clock-names = "pxclk", "aclk";
|
||||
reg = <1>;
|
||||
|
||||
port {
|
||||
dp0_pipe1_out: endpoint {
|
||||
remote-endpoint = <&db_dvi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
@ -31,28 +31,7 @@ Required subnodes:
|
||||
- one subnode per DSI device connected on the DSI bus. Each DSI device should
|
||||
contain a reg property encoding its virtual channel.
|
||||
|
||||
Cadence DPHY
|
||||
============
|
||||
|
||||
Cadence DPHY block.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be set to "cdns,dphy".
|
||||
- reg: physical base address and length of the DPHY registers.
|
||||
- clocks: DPHY reference clocks.
|
||||
- clock-names: must contain "psm" and "pll_ref".
|
||||
- #phy-cells: must be set to 0.
|
||||
|
||||
|
||||
Example:
|
||||
dphy0: dphy@fd0e0000{
|
||||
compatible = "cdns,dphy";
|
||||
reg = <0x0 0xfd0e0000 0x0 0x1000>;
|
||||
clocks = <&psm_clk>, <&pll_ref_clk>;
|
||||
clock-names = "psm", "pll_ref";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
dsi0: dsi@fd0c0000 {
|
||||
compatible = "cdns,dsi";
|
||||
reg = <0x0 0xfd0c0000 0x0 0x1000>;
|
||||
|
||||
@ -22,13 +22,11 @@ among others.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be one or more of the following
|
||||
- "ti,ds90c185" for the TI DS90C185 FPD-Link Serializer
|
||||
- "lvds-encoder" for a generic LVDS encoder device
|
||||
- compatible: Must be "lvds-encoder"
|
||||
|
||||
When compatible with the generic version, nodes must list the
|
||||
device-specific version corresponding to the device first
|
||||
followed by the generic version.
|
||||
Any encoder compatible with this generic binding, but with additional
|
||||
properties not listed here, must list a device specific compatible first
|
||||
followed by this generic compatible.
|
||||
|
||||
Required nodes:
|
||||
|
||||
@ -44,8 +42,6 @@ Example
|
||||
|
||||
lvds-encoder {
|
||||
compatible = "lvds-encoder";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -8,6 +8,8 @@ Required properties:
|
||||
|
||||
- compatible : Shall contain one of
|
||||
- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
|
||||
- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
|
||||
- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
|
||||
- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
|
||||
- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
|
||||
- "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
|
||||
@ -25,7 +27,7 @@ Required properties:
|
||||
- clock-names: Name of the clocks. This property is model-dependent.
|
||||
- The functional clock, which mandatory for all models, shall be listed
|
||||
first, and shall be named "fck".
|
||||
- On R8A77990 and R8A77995, the LVDS encoder can use the EXTAL or
|
||||
- On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or
|
||||
DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
|
||||
named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
|
||||
numerical index.
|
||||
|
||||
@ -10,7 +10,7 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
|
||||
- pwdn-gpios: Power down control GPIO
|
||||
- powerdown-gpios: Power down control GPIO (the /PWDN pin, active low).
|
||||
|
||||
Required nodes:
|
||||
|
||||
|
||||
55
Bindings/display/bridge/ti,ds90c185.txt
Normal file
55
Bindings/display/bridge/ti,ds90c185.txt
Normal file
@ -0,0 +1,55 @@
|
||||
Texas Instruments FPD-Link (LVDS) Serializer
|
||||
--------------------------------------------
|
||||
|
||||
The DS90C185 and DS90C187 are low-power serializers for portable
|
||||
battery-powered applications that reduces the size of the RGB
|
||||
interface between the host GPU and the display.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be
|
||||
"ti,ds90c185", "lvds-encoder" for the TI DS90C185 FPD-Link Serializer
|
||||
"ti,ds90c187", "lvds-encoder" for the TI DS90C187 FPD-Link Serializer
|
||||
|
||||
Optional properties:
|
||||
|
||||
- powerdown-gpios: Power down control GPIO (the PDB pin, active-low)
|
||||
|
||||
Required nodes:
|
||||
|
||||
The devices have two video ports. Their connections are modeled using the OF
|
||||
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
- Video port 0 for parallel input
|
||||
- Video port 1 for LVDS output
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
lvds-encoder {
|
||||
compatible = "ti,ds90c185", "lvds-encoder";
|
||||
|
||||
powerdown-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lvds_enc_in: endpoint {
|
||||
remote-endpoint = <&lcdc_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lvds_enc_out: endpoint {
|
||||
remote-endpoint = <&lvds_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
59
Bindings/display/msm/gmu.txt
Normal file
59
Bindings/display/msm/gmu.txt
Normal file
@ -0,0 +1,59 @@
|
||||
Qualcomm adreno/snapdragon GMU (Graphics management unit)
|
||||
|
||||
The GMU is a programmable power controller for the GPU. the CPU controls the
|
||||
GMU which in turn handles power controls for the GPU.
|
||||
|
||||
Required properties:
|
||||
- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
|
||||
for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
|
||||
Note that you need to list the less specific "qcom,adreno-gmu"
|
||||
for generic matches and the more specific identifier to identify
|
||||
the specific device.
|
||||
- reg: Physical base address and length of the GMU registers.
|
||||
- reg-names: Matching names for the register regions
|
||||
* "gmu"
|
||||
* "gmu_pdc"
|
||||
* "gmu_pdc_seg"
|
||||
- interrupts: The interrupt signals from the GMU.
|
||||
- interrupt-names: Matching names for the interrupts
|
||||
* "hfi"
|
||||
* "gmu"
|
||||
- clocks: phandles to the device clocks
|
||||
- clock-names: Matching names for the clocks
|
||||
* "gmu"
|
||||
* "cxo"
|
||||
* "axi"
|
||||
* "mnoc"
|
||||
- power-domains: should be <&clock_gpucc GPU_CX_GDSC>
|
||||
- iommus: phandle to the adreno iommu
|
||||
- operating-points-v2: phandle to the OPP operating points
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
gmu: gmu@506a000 {
|
||||
compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
|
||||
|
||||
reg = <0x506a000 0x30000>,
|
||||
<0xb280000 0x10000>,
|
||||
<0xb480000 0x10000>;
|
||||
reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
|
||||
|
||||
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
|
||||
clock-names = "gmu", "cxo", "axi", "memnoc";
|
||||
|
||||
power-domains = <&gpucc GPU_CX_GDSC>;
|
||||
iommus = <&adreno_smmu 5>;
|
||||
|
||||
operating-points-v2 = <&gmu_opp_table>;
|
||||
};
|
||||
};
|
||||
@ -10,14 +10,23 @@ Required properties:
|
||||
If "amd,imageon" is used, there should be no top level msm device.
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the gpu.
|
||||
- clocks: device clocks
|
||||
- clocks: device clocks (if applicable)
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
- clock-names: the following clocks are required by a3xx, a4xx and a5xx
|
||||
cores:
|
||||
* "core"
|
||||
* "iface"
|
||||
* "mem_iface"
|
||||
For GMU attached devices the GPU clocks are not used and are not required. The
|
||||
following devices should not list clocks:
|
||||
- qcom,adreno-630.2
|
||||
- iommus: optional phandle to an adreno iommu instance
|
||||
- operating-points-v2: optional phandle to the OPP operating points
|
||||
- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
|
||||
control the power for the GPU. Applicable targets:
|
||||
- qcom,adreno-630.2
|
||||
|
||||
Example:
|
||||
Example 3xx/4xx/a5xx:
|
||||
|
||||
/ {
|
||||
...
|
||||
@ -37,3 +46,30 @@ Example:
|
||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||
};
|
||||
};
|
||||
|
||||
Example a6xx (with GMU):
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
gpu@5000000 {
|
||||
compatible = "qcom,adreno-630.2", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
reg = <0x5000000 0x40000>, <0x509e000 0x10>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_mem";
|
||||
|
||||
/*
|
||||
* Look ma, no clocks! The GPU clocks and power are
|
||||
* controlled entirely by the GMU
|
||||
*/
|
||||
|
||||
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
iommus = <&adreno_smmu 0>;
|
||||
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
|
||||
qcom,gmu = <&gmu>;
|
||||
};
|
||||
};
|
||||
|
||||
7
Bindings/display/panel/innolux,ee101ia-01d.txt
Normal file
7
Bindings/display/panel/innolux,ee101ia-01d.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "innolux,ee101ia-01d"
|
||||
|
||||
This binding is compatible with the lvds-panel binding, which is specified
|
||||
in panel-lvds.txt in this directory.
|
||||
12
Bindings/display/panel/lemaker,bl035-rgb-002.txt
Normal file
12
Bindings/display/panel/lemaker,bl035-rgb-002.txt
Normal file
@ -0,0 +1,12 @@
|
||||
LeMaker BL035-RGB-002 3.5" QVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lemaker,bl035-rgb-002"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
Optional properties:
|
||||
- backlight: as specified in the base binding
|
||||
- enable-gpios: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
14
Bindings/display/panel/pda,91-00156-a0.txt
Normal file
14
Bindings/display/panel/pda,91-00156-a0.txt
Normal file
@ -0,0 +1,14 @@
|
||||
PDA 91-00156-A0 5.0" WVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "pda,91-00156-a0"
|
||||
- power-supply: this panel requires a single power supply. A phandle to a
|
||||
regulator needs to be specified here. Compatible with panel-common binding which
|
||||
is specified in the panel-common.txt in this directory.
|
||||
- backlight: this panel's backlight is controlled by an external backlight
|
||||
controller. A phandle to this controller needs to be specified here.
|
||||
Compatible with panel-common binding which is specified in the panel-common.txt
|
||||
in this directory.
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
30
Bindings/display/panel/sitronix,st7701.txt
Normal file
30
Bindings/display/panel/sitronix,st7701.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Sitronix ST7701 based LCD panels
|
||||
|
||||
ST7701 designed for small and medium sizes of TFT LCD display, is
|
||||
capable of supporting up to 480RGBX864 in resolution. It provides
|
||||
several system interfaces like MIPI/RGB/SPI.
|
||||
|
||||
Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has
|
||||
inbuilt ST7701 chip.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "sitronix,st7701" and one of
|
||||
* "techstar,ts8550b"
|
||||
- reset-gpios: a GPIO phandle for the reset pin
|
||||
|
||||
Required properties for techstar,ts8550b:
|
||||
- reg: DSI virtual channel used by that screen
|
||||
- VCC-supply: analog regulator for MIPI circuit
|
||||
- IOVCC-supply: I/O system regulator
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle for the backlight control.
|
||||
|
||||
panel@0 {
|
||||
compatible = "techstar,ts8550b", "sitronix,st7701";
|
||||
reg = <0>;
|
||||
VCC-supply = <®_dldo2>;
|
||||
IOVCC-supply = <®_dldo2>;
|
||||
reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
@ -7,6 +7,7 @@ Required Properties:
|
||||
- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
|
||||
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
|
||||
- "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
|
||||
- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
|
||||
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
|
||||
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
|
||||
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
|
||||
@ -57,6 +58,7 @@ corresponding to each DU output.
|
||||
R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
|
||||
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
|
||||
R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
|
||||
R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
|
||||
|
||||
@ -10,6 +10,7 @@ Required properties:
|
||||
"rockchip,rk3126-vop";
|
||||
"rockchip,px30-vop-lit";
|
||||
"rockchip,px30-vop-big";
|
||||
"rockchip,rk3066-vop";
|
||||
"rockchip,rk3188-vop";
|
||||
"rockchip,rk3288-vop";
|
||||
"rockchip,rk3368-vop";
|
||||
|
||||
@ -20,7 +20,7 @@ Example:
|
||||
backlight: backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
}
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
|
||||
@ -36,7 +36,6 @@ ssd1307: oled@3c {
|
||||
reg = <0x3c>;
|
||||
pwms = <&pwm 4 3000>;
|
||||
reset-gpios = <&gpio2 7>;
|
||||
reset-active-low;
|
||||
};
|
||||
|
||||
ssd1306: oled@3c {
|
||||
@ -44,7 +43,6 @@ ssd1306: oled@3c {
|
||||
reg = <0x3c>;
|
||||
pwms = <&pwm 4 3000>;
|
||||
reset-gpios = <&gpio2 7>;
|
||||
reset-active-low;
|
||||
solomon,com-lrremap;
|
||||
solomon,com-invdir;
|
||||
solomon,com-offset = <32>;
|
||||
|
||||
@ -156,6 +156,7 @@ Required properties:
|
||||
* allwinner,sun6i-a31-tcon
|
||||
* allwinner,sun6i-a31s-tcon
|
||||
* allwinner,sun7i-a20-tcon
|
||||
* allwinner,sun8i-a23-tcon
|
||||
* allwinner,sun8i-a33-tcon
|
||||
* allwinner,sun8i-a83t-tcon-lcd
|
||||
* allwinner,sun8i-a83t-tcon-tv
|
||||
@ -276,6 +277,7 @@ Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun6i-a31-drc
|
||||
* allwinner,sun6i-a31s-drc
|
||||
* allwinner,sun8i-a23-drc
|
||||
* allwinner,sun8i-a33-drc
|
||||
* allwinner,sun9i-a80-drc
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
@ -303,6 +305,7 @@ Required properties:
|
||||
* allwinner,sun5i-a13-display-backend
|
||||
* allwinner,sun6i-a31-display-backend
|
||||
* allwinner,sun7i-a20-display-backend
|
||||
* allwinner,sun8i-a23-display-backend
|
||||
* allwinner,sun8i-a33-display-backend
|
||||
* allwinner,sun9i-a80-display-backend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
@ -360,6 +363,7 @@ Required properties:
|
||||
* allwinner,sun5i-a13-display-frontend
|
||||
* allwinner,sun6i-a31-display-frontend
|
||||
* allwinner,sun7i-a20-display-frontend
|
||||
* allwinner,sun8i-a23-display-frontend
|
||||
* allwinner,sun8i-a33-display-frontend
|
||||
* allwinner,sun9i-a80-display-frontend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
@ -419,6 +423,7 @@ Required properties:
|
||||
* allwinner,sun6i-a31-display-engine
|
||||
* allwinner,sun6i-a31s-display-engine
|
||||
* allwinner,sun7i-a20-display-engine
|
||||
* allwinner,sun8i-a23-display-engine
|
||||
* allwinner,sun8i-a33-display-engine
|
||||
* allwinner,sun8i-a83t-display-engine
|
||||
* allwinner,sun8i-h3-display-engine
|
||||
|
||||
@ -238,6 +238,9 @@ of the following host1x client modules:
|
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
|
||||
- nvidia,edid: supplies a binary EDID blob
|
||||
- nvidia,panel: phandle of a display panel
|
||||
- nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
|
||||
of the SOR, identified by the cell's index, is mapped via the crossbar to
|
||||
the pad specified by the cell's value.
|
||||
|
||||
Optional properties when driving an eDP output:
|
||||
- nvidia,dpaux: phandle to a DispayPort AUX interface
|
||||
|
||||
@ -16,6 +16,9 @@ Optional properties:
|
||||
- dma-channels: Number of DMA channels supported by the controller.
|
||||
- dma-requests: Number of DMA request signals supported by the
|
||||
controller.
|
||||
- dma-channel-mask: Bitmask of available DMA channels in ascending order
|
||||
that are not reserved by firmware and are available to
|
||||
the kernel. i.e. first channel corresponds to LSB.
|
||||
|
||||
Example:
|
||||
|
||||
@ -29,6 +32,7 @@ Example:
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <32>;
|
||||
dma-requests = <127>;
|
||||
dma-channel-mask = <0xfffe>
|
||||
};
|
||||
|
||||
* DMA router
|
||||
|
||||
57
Bindings/dma/fsl-qdma.txt
Normal file
57
Bindings/dma/fsl-qdma.txt
Normal file
@ -0,0 +1,57 @@
|
||||
NXP Layerscape SoC qDMA Controller
|
||||
==================================
|
||||
|
||||
This device follows the generic DMA bindings defined in dma/dma.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be one of
|
||||
"fsl,ls1021a-qdma": for LS1021A Board
|
||||
"fsl,ls1043a-qdma": for ls1043A Board
|
||||
"fsl,ls1046a-qdma": for ls1046A Board
|
||||
- reg: Should contain the register's base address and length.
|
||||
- interrupts: Should contain a reference to the interrupt used by this
|
||||
device.
|
||||
- interrupt-names: Should contain interrupt names:
|
||||
"qdma-queue0": the block0 interrupt
|
||||
"qdma-queue1": the block1 interrupt
|
||||
"qdma-queue2": the block2 interrupt
|
||||
"qdma-queue3": the block3 interrupt
|
||||
"qdma-error": the error interrupt
|
||||
- fsl,dma-queues: Should contain number of queues supported.
|
||||
- dma-channels: Number of DMA channels supported
|
||||
- block-number: the virtual block number
|
||||
- block-offset: the offset of different virtual block
|
||||
- status-sizes: status queue size of per virtual block
|
||||
- queue-sizes: command queue size of per virtual block, the size number
|
||||
based on queues
|
||||
|
||||
Optional properties:
|
||||
|
||||
- dma-channels: Number of DMA channels supported by the controller.
|
||||
- big-endian: If present registers and hardware scatter/gather descriptors
|
||||
of the qDMA are implemented in big endian mode, otherwise in little
|
||||
mode.
|
||||
|
||||
Examples:
|
||||
|
||||
qdma: dma-controller@8390000 {
|
||||
compatible = "fsl,ls1021a-qdma";
|
||||
reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8389000 0x0 0x1000>, /* Status regs */
|
||||
<0x0 0x838a000 0x0 0x2000>; /* Block regs */
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qdma-error",
|
||||
"qdma-queue0", "qdma-queue1";
|
||||
dma-channels = <8>;
|
||||
block-number = <2>;
|
||||
block-offset = <0x1000>;
|
||||
fsl,dma-queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
DMA clients must use the format described in dma/dma.txt file.
|
||||
@ -3,7 +3,9 @@
|
||||
See dma.txt first
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "hisilicon,k3-dma-1.0"
|
||||
- compatible: Must be one of
|
||||
- "hisilicon,k3-dma-1.0"
|
||||
- "hisilicon,hisi-pcm-asp-dma-1.0"
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- interrupts: Should contain one interrupt shared by all channel
|
||||
- #dma-cells: see dma.txt, should be 1, para number
|
||||
|
||||
@ -23,8 +23,6 @@ Deprecated properties:
|
||||
|
||||
|
||||
Optional properties:
|
||||
- is_private: The device channels should be marked as private and not for by the
|
||||
general purpose DMA channel allocator. False if not passed.
|
||||
- multi-block: Multi block transfers supported by hardware. Array property with
|
||||
one cell per channel. 0: not supported, 1 (default): supported.
|
||||
- snps,dma-protection-control: AHB HPROT[3:1] protection setting.
|
||||
|
||||
@ -31,7 +31,7 @@ DMA clients connected to the Spreadtrum DMA controller must use the format
|
||||
described in the dma.txt file, using a two-cell specifier for each channel.
|
||||
The two cells in order are:
|
||||
1. A phandle pointing to the DMA controller.
|
||||
2. The channel id.
|
||||
2. The slave id.
|
||||
|
||||
spi0: spi@70a00000{
|
||||
...
|
||||
|
||||
@ -37,10 +37,11 @@ Required properties:
|
||||
Required properties for VDMA:
|
||||
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
|
||||
|
||||
Optional properties:
|
||||
- xlnx,include-sg: Tells configured for Scatter-mode in
|
||||
the hardware.
|
||||
Optional properties for AXI DMA:
|
||||
- xlnx,sg-length-width: Should be set to the width in bits of the length
|
||||
register as configured in h/w. Takes values {8...26}. If the property
|
||||
is missing or invalid then the default value 23 is used. This is the
|
||||
maximum value that is supported by all IP versions.
|
||||
- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
|
||||
Optional properties for VDMA:
|
||||
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
|
||||
|
||||
25
Bindings/edac/aspeed-sdram-edac.txt
Normal file
25
Bindings/edac/aspeed-sdram-edac.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Aspeed AST2500 SoC EDAC node
|
||||
|
||||
The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
|
||||
correction check).
|
||||
|
||||
The memory controller supports SECDED (single bit error correction, double bit
|
||||
error detection) and single bit error auto scrubbing by reserving 8 bits for
|
||||
every 64 bit word (effectively reducing available memory to 8/9).
|
||||
|
||||
Note, the bootloader must configure ECC mode in the memory controller.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "aspeed,ast2500-sdram-edac"
|
||||
- reg: sdram controller register set should be <0x1e6e0000 0x174>
|
||||
- interrupts: should be AVIC interrupt #0
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
edac: sdram@1e6e0000 {
|
||||
compatible = "aspeed,ast2500-sdram-edac";
|
||||
reg = <0x1e6e0000 0x174>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
@ -75,6 +75,8 @@ Optional properties:
|
||||
|
||||
- address-width: number of address bits (one of 8, 16).
|
||||
|
||||
- num-addresses: total number of i2c slave addresses this device takes
|
||||
|
||||
Example:
|
||||
|
||||
eeprom@52 {
|
||||
@ -82,4 +84,5 @@ eeprom@52 {
|
||||
reg = <0x52>;
|
||||
pagesize = <32>;
|
||||
wp-gpios = <&gpio1 3 0>;
|
||||
num-addresses = <8>;
|
||||
};
|
||||
|
||||
27
Bindings/extcon/extcon-ptn5150.txt
Normal file
27
Bindings/extcon/extcon-ptn5150.txt
Normal file
@ -0,0 +1,27 @@
|
||||
* PTN5150 CC (Configuration Channel) Logic device
|
||||
|
||||
PTN5150 is a small thin low power CC logic chip supporting the USB Type-C
|
||||
connector application with CC control logic detection and indication functions.
|
||||
It is interfaced to the host controller using an I2C interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,ptn5150"
|
||||
- reg: specifies the I2C slave address of the device
|
||||
- int-gpio: should contain a phandle and GPIO specifier for the GPIO pin
|
||||
connected to the PTN5150's INTB pin.
|
||||
- vbus-gpio: should contain a phandle and GPIO specifier for the GPIO pin which
|
||||
is used to control VBUS.
|
||||
- pinctrl-names : a pinctrl state named "default" must be defined.
|
||||
- pinctrl-0 : phandle referencing pin configuration of interrupt and vbus
|
||||
control.
|
||||
|
||||
Example:
|
||||
ptn5150@1d {
|
||||
compatible = "nxp,ptn5150";
|
||||
reg = <0x1d>;
|
||||
int-gpio = <&msmgpio 78 GPIO_ACTIVE_HIGH>;
|
||||
vbus-gpio = <&msmgpio 148 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ptn5150_default>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -8,7 +8,6 @@ which can create the interprocessor communication (IPC) between the CPU
|
||||
and BPMP.
|
||||
|
||||
Required properties:
|
||||
- name : Should be bpmp
|
||||
- compatible
|
||||
Array of strings
|
||||
One of:
|
||||
|
||||
35
Bindings/firmware/nvidia,tegra210-bpmp.txt
Normal file
35
Bindings/firmware/nvidia,tegra210-bpmp.txt
Normal file
@ -0,0 +1,35 @@
|
||||
NVIDIA Tegra210 Boot and Power Management Processor (BPMP)
|
||||
|
||||
The Boot and Power Management Processor (BPMP) is a co-processor found
|
||||
in Tegra210 SoC. It is designed to handle the early stages of the boot
|
||||
process as well as to assisting in entering deep low power state
|
||||
(suspend to ram), and also offloading DRAM memory clock scaling on
|
||||
some platforms. The binding document defines the resources that would
|
||||
be used by the BPMP T210 firmware driver, which can create the
|
||||
interprocessor communication (IPC) between the CPU and BPMP.
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
Array of strings
|
||||
One of:
|
||||
- "nvidia,tegra210-bpmp"
|
||||
- reg: physical base address and length for HW synchornization primitives
|
||||
1) base address and length to Tegra 'atomics' hardware
|
||||
2) base address and length to Tegra 'semaphore' hardware
|
||||
- interrupts: specifies the interrupt number for receiving messages ("rx")
|
||||
and for triggering messages ("tx")
|
||||
|
||||
Optional properties:
|
||||
- #clock-cells : Should be 1 for platforms where DRAM clock control is
|
||||
offloaded to bpmp.
|
||||
|
||||
Example:
|
||||
|
||||
bpmp@70016000 {
|
||||
compatible = "nvidia,tegra210-bpmp";
|
||||
reg = <0x0 0x70016000 0x0 0x2000
|
||||
0x0 0x60001000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "tx", "rx";
|
||||
};
|
||||
@ -17,6 +17,7 @@ Required properties:
|
||||
represents
|
||||
|
||||
Optional properties:
|
||||
- lna-supply : Separate supply for an LNA
|
||||
- enable-gpios : GPIO used to enable the device
|
||||
- timepulse-gpios : Time pulse GPIO
|
||||
|
||||
|
||||
35
Bindings/gnss/mediatek.txt
Normal file
35
Bindings/gnss/mediatek.txt
Normal file
@ -0,0 +1,35 @@
|
||||
Mediatek-based GNSS Receiver DT binding
|
||||
|
||||
Mediatek chipsets are used in GNSS-receiver modules produced by several
|
||||
vendors and can use a UART interface.
|
||||
|
||||
Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
|
||||
properties.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Must be
|
||||
|
||||
"globaltop,pa6h"
|
||||
|
||||
- vcc-supply : Main voltage regulator (pin name: VCC)
|
||||
|
||||
Optional properties:
|
||||
|
||||
- current-speed : Default UART baud rate
|
||||
- gnss-fix-gpios : GPIO used to determine device position fix state
|
||||
(pin name: FIX, 3D_FIX)
|
||||
- reset-gpios : GPIO used to reset the device (pin name: RESET, NRESET)
|
||||
- timepulse-gpios : Time pulse GPIO (pin name: PPS1, 1PPS)
|
||||
- vbackup-supply : Backup voltage regulator (pin name: VBAT, VBACKUP)
|
||||
|
||||
Example:
|
||||
|
||||
serial@1234 {
|
||||
compatible = "ns16550a";
|
||||
|
||||
gnss {
|
||||
compatible = "globaltop,pa6h";
|
||||
vcc-supply = <&vcc_3v3>;
|
||||
};
|
||||
};
|
||||
@ -12,6 +12,7 @@ Required properties:
|
||||
|
||||
"fastrax,uc430"
|
||||
"linx,r4"
|
||||
"wi2wi,w2sg0004"
|
||||
"wi2wi,w2sg0008i"
|
||||
"wi2wi,w2sg0084i"
|
||||
|
||||
|
||||
20
Bindings/gpio/gateworks,pld-gpio.txt
Normal file
20
Bindings/gpio/gateworks,pld-gpio.txt
Normal file
@ -0,0 +1,20 @@
|
||||
Gateworks PLD GPIO controller bindings
|
||||
|
||||
The GPIO controller should be a child node on an I2C bus,
|
||||
see: i2c/i2c.txt for details.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "gateworks,pld-gpio"
|
||||
- reg: I2C slave address
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells: Should be <2>. The first cell is the gpio number and
|
||||
the second cell is used to specify optional parameters.
|
||||
|
||||
Example:
|
||||
|
||||
pld@56 {
|
||||
compatible = "gateworks,pld-gpio";
|
||||
reg = <0x56>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
@ -33,7 +33,7 @@ Required properties:
|
||||
"sprd,sc9860-eic-latch",
|
||||
"sprd,sc9860-eic-async",
|
||||
"sprd,sc9860-eic-sync",
|
||||
"sprd,sc27xx-eic".
|
||||
"sprd,sc2731-eic".
|
||||
- reg: Define the base and range of the I/O address space containing
|
||||
the GPIO controller registers.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
@ -86,7 +86,7 @@ Example:
|
||||
};
|
||||
|
||||
pmic_eic: gpio@300 {
|
||||
compatible = "sprd,sc27xx-eic";
|
||||
compatible = "sprd,sc2731-eic";
|
||||
reg = <0x300>;
|
||||
interrupt-parent = <&sc2731_pmic>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -16,6 +16,7 @@ Required properties:
|
||||
nxp,pca9574
|
||||
nxp,pca9575
|
||||
nxp,pca9698
|
||||
nxp,pcal6416
|
||||
nxp,pcal6524
|
||||
nxp,pcal9555a
|
||||
maxim,max7310
|
||||
|
||||
@ -67,6 +67,18 @@ Optional standard bitfield specifiers for the last cell:
|
||||
https://en.wikipedia.org/wiki/Open_collector
|
||||
- Bit 3: 0 means the output should be maintained during sleep/low-power mode
|
||||
1 means the output state can be lost during sleep/low-power mode
|
||||
- Bit 4: 0 means no pull-up resistor should be enabled
|
||||
1 means a pull-up resistor should be enabled
|
||||
This setting only applies to hardware with a simple on/off
|
||||
control for pull-up configuration. If the hardware has more
|
||||
elaborate pull-up configuration, it should be represented
|
||||
using a pin control binding.
|
||||
- Bit 5: 0 means no pull-down resistor should be enabled
|
||||
1 means a pull-down resistor should be enabled
|
||||
This setting only applies to hardware with a simple on/off
|
||||
control for pull-down configuration. If the hardware has more
|
||||
elaborate pull-down configuration, it should be represented
|
||||
using a pin control binding.
|
||||
|
||||
1.1) GPIO specifier best practices
|
||||
----------------------------------
|
||||
|
||||
38
Bindings/gpio/intel,ixp4xx-gpio.txt
Normal file
38
Bindings/gpio/intel,ixp4xx-gpio.txt
Normal file
@ -0,0 +1,38 @@
|
||||
Intel IXP4xx XScale Networking Processors GPIO
|
||||
|
||||
This GPIO controller is found in the Intel IXP4xx processors.
|
||||
It supports 16 GPIO lines.
|
||||
|
||||
The interrupt portions of the GPIO controller is hierarchical:
|
||||
the synchronous edge detector is part of the GPIO block, but the
|
||||
actual enabling/disabling of the interrupt line is done in the
|
||||
main IXP4xx interrupt controller which has a 1:1 mapping for
|
||||
the first 12 GPIO lines to 12 system interrupts.
|
||||
|
||||
The remaining 4 GPIO lines can not be used for receiving
|
||||
interrupts.
|
||||
|
||||
The interrupt parent of this GPIO controller must be the
|
||||
IXP4xx interrupt controller.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be
|
||||
"intel,ixp4xx-gpio"
|
||||
- reg : Should contain registers location and length
|
||||
- gpio-controller : marks this as a GPIO controller
|
||||
- #gpio-cells : Should be 2, see gpio/gpio.txt
|
||||
- interrupt-controller : marks this as an interrupt controller
|
||||
- #interrupt-cells : a standard two-cell interrupt, see
|
||||
interrupt-controller/interrupts.txt
|
||||
|
||||
Example:
|
||||
|
||||
gpio0: gpio@c8004000 {
|
||||
compatible = "intel,ixp4xx-gpio";
|
||||
reg = <0xc8004000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
@ -13,6 +13,8 @@ Required properties:
|
||||
+ allwinner,sun8i-h3-mali
|
||||
+ allwinner,sun50i-a64-mali
|
||||
+ allwinner,sun50i-h5-mali
|
||||
+ amlogic,meson8-mali
|
||||
+ amlogic,meson8b-mali
|
||||
+ amlogic,meson-gxbb-mali
|
||||
+ amlogic,meson-gxl-mali
|
||||
+ rockchip,rk3036-mali
|
||||
@ -82,6 +84,10 @@ to specify one more vendor-specific compatible, among:
|
||||
Required properties:
|
||||
* resets: phandle to the reset line for the GPU
|
||||
|
||||
- amlogic,meson8-mali and amlogic,meson8b-mali
|
||||
Required properties:
|
||||
* resets: phandle to the reset line for the GPU
|
||||
|
||||
- Rockchip variants:
|
||||
Required properties:
|
||||
* resets: phandle to the reset line for the GPU
|
||||
|
||||
@ -2,9 +2,10 @@
|
||||
|
||||
Required properties:
|
||||
- compatible : value should be one of the following:
|
||||
(a) "samsung,exynos4210-rotator" for Rotator IP in Exynos4210
|
||||
(b) "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412
|
||||
(c) "samsung,exynos5250-rotator" for Rotator IP in Exynos5250
|
||||
* "samsung,s5pv210-rotator" for Rotator IP in S5PV210
|
||||
* "samsung,exynos4210-rotator" for Rotator IP in Exynos4210
|
||||
* "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412
|
||||
* "samsung,exynos5250-rotator" for Rotator IP in Exynos5250
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
15
Bindings/hwmon/ad741x.txt
Normal file
15
Bindings/hwmon/ad741x.txt
Normal file
@ -0,0 +1,15 @@
|
||||
* AD7416/AD7417/AD7418 Temperature Sensor Device Tree Bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: one of
|
||||
"adi,ad7416"
|
||||
"adi,ad7417"
|
||||
"adi,ad7418"
|
||||
- reg: I2C address
|
||||
|
||||
Example:
|
||||
|
||||
hwmon@28 {
|
||||
compatible = "adi,ad7418";
|
||||
reg = <0x28>;
|
||||
};
|
||||
@ -26,7 +26,7 @@ Required node properties:
|
||||
|
||||
Optional node properties:
|
||||
|
||||
- ti,mode: Operation mode (see above).
|
||||
- ti,mode: Operation mode (u8) (see above).
|
||||
|
||||
|
||||
Example (operation mode 2):
|
||||
@ -34,5 +34,5 @@ Example (operation mode 2):
|
||||
adc128d818@1d {
|
||||
compatible = "ti,adc128d818";
|
||||
reg = <0x1d>;
|
||||
ti,mode = <2>;
|
||||
ti,mode = /bits/ 8 <2>;
|
||||
};
|
||||
|
||||
11
Bindings/hwmon/dps650ab.txt
Normal file
11
Bindings/hwmon/dps650ab.txt
Normal file
@ -0,0 +1,11 @@
|
||||
Bindings for Delta Electronics DPS-650-AB power supply
|
||||
|
||||
Required properties:
|
||||
- compatible : "delta,dps650ab"
|
||||
- reg : I2C address, one of 0x58, 0x59.
|
||||
|
||||
Example:
|
||||
dps650ab@58 {
|
||||
compatible = "delta,dps650ab";
|
||||
reg = <0x58>;
|
||||
};
|
||||
12
Bindings/hwmon/hih6130.txt
Normal file
12
Bindings/hwmon/hih6130.txt
Normal file
@ -0,0 +1,12 @@
|
||||
Honeywell Humidicon HIH-6130 humidity/temperature sensor
|
||||
--------------------------------------------------------
|
||||
|
||||
Requires node properties:
|
||||
- compatible : "honeywell,hi6130"
|
||||
- reg : the I2C address of the device. This is 0x27.
|
||||
|
||||
Example:
|
||||
hih6130@27 {
|
||||
compatible = "honeywell,hih6130";
|
||||
reg = <0x27>;
|
||||
};
|
||||
@ -6,6 +6,16 @@ Texas Instruments INA3221 Device Tree Bindings
|
||||
- reg: I2C address
|
||||
|
||||
Optional properties:
|
||||
- ti,single-shot: This chip has two power modes: single-shot (chip takes one
|
||||
measurement and then shuts itself down) and continuous (
|
||||
chip takes continuous measurements). The continuous mode is
|
||||
more reliable and suitable for hardware monitor type device,
|
||||
but the single-shot mode is more power-friendly and useful
|
||||
for battery-powered device which cares power consumptions
|
||||
while still needs some measurements occasionally.
|
||||
If this property is present, the single-shot mode will be
|
||||
used, instead of the default continuous one for monitoring.
|
||||
|
||||
= The node contains optional child nodes for three channels =
|
||||
= Each child node describes the information of input source =
|
||||
|
||||
|
||||
37
Bindings/hwmon/lm75.txt
Normal file
37
Bindings/hwmon/lm75.txt
Normal file
@ -0,0 +1,37 @@
|
||||
*LM75 hwmon sensor.
|
||||
|
||||
Required properties:
|
||||
- compatible: manufacturer and chip name, one of
|
||||
"adi,adt75",
|
||||
"dallas,ds1775",
|
||||
"dallas,ds75",
|
||||
"dallas,ds7505",
|
||||
"gmt,g751",
|
||||
"national,lm75",
|
||||
"national,lm75a",
|
||||
"national,lm75b",
|
||||
"maxim,max6625",
|
||||
"maxim,max6626",
|
||||
"maxim,max31725",
|
||||
"maxim,max31726",
|
||||
"maxim,mcp980x",
|
||||
"st,stds75",
|
||||
"st,stlm75",
|
||||
"microchip,tcn75",
|
||||
"ti,tmp100",
|
||||
"ti,tmp101",
|
||||
"ti,tmp105",
|
||||
"ti,tmp112",
|
||||
"ti,tmp175",
|
||||
"ti,tmp275",
|
||||
"ti,tmp75",
|
||||
"ti,tmp75c",
|
||||
|
||||
- reg: I2C bus address of the device
|
||||
|
||||
Example:
|
||||
|
||||
sensor@48 {
|
||||
compatible = "st,stlm75";
|
||||
reg = <0x48>;
|
||||
};
|
||||
@ -6,6 +6,9 @@ Required properties:
|
||||
- cooling-levels : PWM duty cycle values in a range from 0 to 255
|
||||
which correspond to thermal cooling states
|
||||
|
||||
Optional properties:
|
||||
- fan-supply : phandle to the regulator that provides power to the fan
|
||||
|
||||
Example:
|
||||
fan0: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
|
||||
20
Bindings/i2c/i2c-iop3xx.txt
Normal file
20
Bindings/i2c/i2c-iop3xx.txt
Normal file
@ -0,0 +1,20 @@
|
||||
i2c Controller on XScale platforms such as IOP3xx and IXP4xx
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be one of
|
||||
"intel,iop3xx-i2c"
|
||||
"intel,ixp4xx-i2c";
|
||||
- reg
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
|
||||
Optional properties:
|
||||
- Child nodes conforming to i2c bus binding
|
||||
|
||||
Example:
|
||||
|
||||
i2c@c8011000 {
|
||||
compatible = "intel,ixp4xx-i2c";
|
||||
reg = <0xc8011000 0x18>;
|
||||
interrupts = <33 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
@ -10,6 +10,7 @@ Required properties:
|
||||
"mediatek,mt6589-i2c": for MediaTek MT6589
|
||||
"mediatek,mt7622-i2c": for MediaTek MT7622
|
||||
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
|
||||
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
|
||||
"mediatek,mt8173-i2c": for MediaTek MT8173
|
||||
- reg: physical base address of the controller and dma base, length of memory
|
||||
mapped region.
|
||||
@ -20,6 +20,10 @@ Optional properties:
|
||||
- interrupt-names: should contain "INT1" and/or "INT2", the accelerometer's
|
||||
interrupt line in use.
|
||||
|
||||
- vdd-supply: phandle to the regulator that provides vdd power to the accelerometer.
|
||||
|
||||
- vddio-supply: phandle to the regulator that provides vddio power to the accelerometer.
|
||||
|
||||
Example:
|
||||
|
||||
mma8453fc@1d {
|
||||
|
||||
65
Bindings/iio/adc/adi,ad7606.txt
Normal file
65
Bindings/iio/adc/adi,ad7606.txt
Normal file
@ -0,0 +1,65 @@
|
||||
Analog Devices AD7606 Simultaneous Sampling ADC
|
||||
|
||||
Required properties for the AD7606:
|
||||
|
||||
- compatible: Must be one of
|
||||
* "adi,ad7605-4"
|
||||
* "adi,ad7606-8"
|
||||
* "adi,ad7606-6"
|
||||
* "adi,ad7606-4"
|
||||
- reg: SPI chip select number for the device
|
||||
- spi-max-frequency: Max SPI frequency to use
|
||||
see: Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
- spi-cpha: See Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
- avcc-supply: phandle to the Avcc power supply
|
||||
- interrupts: IRQ line for the ADC
|
||||
see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
- adi,conversion-start-gpios: must be the device tree identifier of the CONVST pin.
|
||||
This logic input is used to initiate conversions on the analog
|
||||
input channels. As the line is active high, it should be marked
|
||||
GPIO_ACTIVE_HIGH.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reset-gpios: must be the device tree identifier of the RESET pin. If specified,
|
||||
it will be asserted during driver probe. As the line is active high,
|
||||
it should be marked GPIO_ACTIVE_HIGH.
|
||||
- standby-gpios: must be the device tree identifier of the STBY pin. This pin is used
|
||||
to place the AD7606 into one of two power-down modes, Standby mode or
|
||||
Shutdown mode. As the line is active low, it should be marked
|
||||
GPIO_ACTIVE_LOW.
|
||||
- adi,first-data-gpios: must be the device tree identifier of the FRSTDATA pin.
|
||||
The FRSTDATA output indicates when the first channel, V1, is
|
||||
being read back on either the parallel, byte or serial interface.
|
||||
As the line is active high, it should be marked GPIO_ACTIVE_HIGH.
|
||||
- adi,range-gpios: must be the device tree identifier of the RANGE pin. The polarity on
|
||||
this pin determines the input range of the analog input channels. If
|
||||
this pin is tied to a logic high, the analog input range is ±10V for
|
||||
all channels. If this pin is tied to a logic low, the analog input range
|
||||
is ±5V for all channels. As the line is active high, it should be marked
|
||||
GPIO_ACTIVE_HIGH.
|
||||
- adi,oversampling-ratio-gpios: must be the device tree identifier of the over-sampling
|
||||
mode pins. As the line is active high, it should be marked
|
||||
GPIO_ACTIVE_HIGH.
|
||||
|
||||
Example:
|
||||
|
||||
adc@0 {
|
||||
compatible = "adi,ad7606-8";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cpol;
|
||||
|
||||
avcc-supply = <&adc_vref>;
|
||||
|
||||
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpio>;
|
||||
|
||||
adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
|
||||
adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH
|
||||
&gpio 23 GPIO_ACTIVE_HIGH
|
||||
&gpio 26 GPIO_ACTIVE_HIGH>;
|
||||
standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
41
Bindings/iio/adc/adi,ad7768-1.txt
Normal file
41
Bindings/iio/adc/adi,ad7768-1.txt
Normal file
@ -0,0 +1,41 @@
|
||||
Analog Devices AD7768-1 ADC device driver
|
||||
|
||||
Required properties for the AD7768-1:
|
||||
|
||||
- compatible: Must be "adi,ad7768-1"
|
||||
- reg: SPI chip select number for the device
|
||||
- spi-max-frequency: Max SPI frequency to use
|
||||
see: Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
- clocks: phandle to the master clock (mclk)
|
||||
see: Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
- clock-names: Must be "mclk".
|
||||
- interrupts: IRQ line for the ADC
|
||||
see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
- vref-supply: vref supply can be used as reference for conversion
|
||||
- adi,sync-in-gpios: must be the device tree identifier of the SYNC-IN pin. Enables
|
||||
synchronization of multiple devices that require simultaneous sampling.
|
||||
A pulse is always required if the configuration is changed in any way, for example
|
||||
if the filter decimation rate changes. As the line is active low, it should
|
||||
be marked GPIO_ACTIVE_LOW.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reset-gpios : GPIO spec for the RESET pin. If specified, it will be asserted during
|
||||
driver probe. As the line is active low, it should be marked GPIO_ACTIVE_LOW.
|
||||
|
||||
Example:
|
||||
|
||||
adc@0 {
|
||||
compatible = "adi,ad7768-1";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <2000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
vref-supply = <&adc_vref>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&gpio>;
|
||||
adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&ad7768_mclk>;
|
||||
clock-names = "mclk";
|
||||
};
|
||||
@ -23,6 +23,10 @@ Required properties:
|
||||
- #io-channel-cells: must be 1, see ../iio-bindings.txt
|
||||
|
||||
Optional properties:
|
||||
- amlogic,hhi-sysctrl: phandle to the syscon which contains the 5th bit
|
||||
of the TSC (temperature sensor coefficient) on
|
||||
Meson8b and Meson8m2 (which used to calibrate the
|
||||
temperature sensor)
|
||||
- nvmem-cells: phandle to the temperature_calib eFuse cells
|
||||
- nvmem-cell-names: if present (to enable the temperature sensor
|
||||
calibration) this must contain "temperature_calib"
|
||||
|
||||
48
Bindings/iio/adc/ingenic,adc.txt
Normal file
48
Bindings/iio/adc/ingenic,adc.txt
Normal file
@ -0,0 +1,48 @@
|
||||
* Ingenic JZ47xx ADC controller IIO bindings
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
* ingenic,jz4725b-adc
|
||||
* ingenic,jz4740-adc
|
||||
- reg: ADC controller registers location and length.
|
||||
- clocks: phandle to the SoC's ADC clock.
|
||||
- clock-names: Must be set to "adc".
|
||||
- #io-channel-cells: Must be set to <1> to indicate channels are selected
|
||||
by index.
|
||||
|
||||
ADC clients must use the format described in iio-bindings.txt, giving
|
||||
a phandle and IIO specifier pair ("io-channels") to the ADC controller.
|
||||
|
||||
Example:
|
||||
|
||||
#include <dt-bindings/iio/adc/ingenic,adc.h>
|
||||
|
||||
adc: adc@10070000 {
|
||||
compatible = "ingenic,jz4740-adc";
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
reg = <0x10070000 0x30>;
|
||||
|
||||
clocks = <&cgu JZ4740_CLK_ADC>;
|
||||
clock-names = "adc";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
...
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&adc INGENIC_ADC_AUX>;
|
||||
io-channel-names = "buttons";
|
||||
...
|
||||
};
|
||||
|
||||
battery {
|
||||
...
|
||||
compatible = "ingenic,jz4740-battery";
|
||||
io-channels = <&adc INGENIC_ADC_BATTERY>;
|
||||
io-channel-names = "battery";
|
||||
...
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user