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Increase the maximum to wait for a transition from 1 to 10 ms. In some

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modes, systems may take longer.  If the status values don't match, try
matching just the lowest 8 bits if no bits above 8 are set in the desired
value.  The IBM R32 has other bits set in the status register that are
irrelevant to the expected value.
This commit is contained in:
Nate Lawson 2005-02-22 06:34:53 +00:00
parent 0dc1b976eb
commit 0db8fa8984
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=142204
1 changed files with 16 additions and 4 deletions
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20
sys/dev/acpica/acpi_perf.c
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@ -448,15 +448,27 @@ acpi_px_set(device_t dev, const struct cf_setting *set)
/* Write the appropriate value to the register. */
PX_SET_REG(sc->perf_ctrl, sc->px_states[i].ctrl_val);
/* Try for up to 1 ms to verify the desired state was selected. */
/*
* Try for up to 10 ms to verify the desired state was selected.
* This is longer than the standard says (1 ms) but in some modes,
* systems may take longer to respond.
*/
sts_val = sc->px_states[i].sts_val;
for (tries = 0; tries < 100; tries++) {
for (tries = 0; tries < 1000; tries++) {
status = PX_GET_REG(sc->perf_status);
if (status == sts_val)
/*
* If we match the status or the desired status is 8 bits
* and matches the relevant bits, assume we succeeded. It
* appears some systems (IBM R32) expect byte-wide access
* even though the standard says the register is 32-bit.
*/
if (status == sts_val ||
((sts_val & ~0xff) == 0 && (status & 0xff) == sts_val))
break;
DELAY(10);
}
if (tries == 100) {
if (tries == 1000) {
device_printf(dev, "Px transition to %d failed\n",
sc->px_states[i].core_freq);
return (ENXIO);