From 0ef0edf2bb8eaa2b27020b38b5e6eb2339717d2f Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Thu, 10 Nov 2016 19:40:14 +0000 Subject: [PATCH] Pull in r263301 from upstream llvm trunk (by Ahmed Bougacha): [AArch64] Don't blindly lower f16/f128 FCCMPs. Instead, extend f16 (like we do when lowering a standalone SETCC), and let f128 be legalized to the RT calls. Fixes PR26803. This fixes a fatal "Cannot select" backend error when building the net/freerdp port for AArch64. PR: 214380 MFC after: 3 days --- .../Target/AArch64/AArch64ISelLowering.cpp | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 9cbf48820e99..29fbed1b5880 100644 --- a/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1177,8 +1177,14 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) { EVT VT = LHS.getValueType(); - if (VT.isFloatingPoint()) + if (VT.isFloatingPoint()) { + assert(VT != MVT::f128); + if (VT == MVT::f16) { + LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); + RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); + } return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); + } // The CMP instruction is just an alias for SUBS, and representing it as // SUBS means that it's possible to get CSE with subtract operations. @@ -1261,9 +1267,14 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS, SDValue Condition, unsigned NZCV, SDLoc DL, SelectionDAG &DAG) { unsigned Opcode = 0; - if (LHS.getValueType().isFloatingPoint()) + if (LHS.getValueType().isFloatingPoint()) { + assert(LHS.getValueType() != MVT::f128); + if (LHS.getValueType() == MVT::f16) { + LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); + RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); + } Opcode = AArch64ISD::FCCMP; - else if (RHS.getOpcode() == ISD::SUB) { + } else if (RHS.getOpcode() == ISD::SUB) { SDValue SubOp0 = RHS.getOperand(0); if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { // See emitComparison() on why we can only do this for SETEQ and SETNE. @@ -1290,6 +1301,8 @@ static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate, return false; unsigned Opcode = Val->getOpcode(); if (Opcode == ISD::SETCC) { + if (Val->getOperand(0).getValueType() == MVT::f128) + return false; CanPushNegate = true; return true; }