Pull in r227752 from upstream llvm trunk (by Michael Kuperstein):
[X86] Convert esp-relative movs of function arguments to pushes, step 2 This moves the transformation introduced in r223757 into a separate MI pass. This allows it to cover many more cases (not only cases where there must be a reserved call frame), and perform rudimentary call folding. It still doesn't have a heuristic, so it is enabled only for optsize/minsize, with stack alignment <= 8, where it ought to be a fairly clear win. (Re-commit of r227728) Differential Revision: http://reviews.llvm.org/D6789 This helps to get sys/boot/i386/boot2 below the required size again, when optimizing with -Oz.
This commit is contained in:
Dimitry Andric
parent
73ee00cef5
commit
0f0f2bfa77
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang360-import/; revision=278112
@ -193,6 +193,11 @@ class TargetFrameLowering {
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return hasReservedCallFrame(MF) || hasFP(MF);
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}
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// needsFrameIndexResolution - Do we need to perform FI resolution for
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// this function. Normally, this is required only when the function
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// has any stack objects. However, targets may want to override this.
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virtual bool needsFrameIndexResolution(const MachineFunction &MF) const;
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/// getFrameIndexOffset - Returns the displacement from the frame register to
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/// the stack frame of the specified index.
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virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
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@ -703,7 +703,8 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
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/// register references and actual offsets.
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///
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void PEI::replaceFrameIndices(MachineFunction &Fn) {
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if (!Fn.getFrameInfo()->hasStackObjects()) return; // Nothing to do?
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const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
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if (!TFI.needsFrameIndexResolution(Fn)) return;
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// Store SPAdj at exit of a basic block.
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SmallVector<int, 8> SPState;
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@ -769,13 +770,6 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
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continue;
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}
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// If we are looking at a call sequence, we need to keep track of
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// the SP adjustment made by each instruction in the sequence.
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// This includes both the frame setup/destroy pseudos (handled above),
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// as well as other instructions that have side effects w.r.t the SP.
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if (InsideCallSequence)
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SPAdj += TII.getSPAdjust(I);
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MachineInstr *MI = I;
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bool DoIncr = true;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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@ -854,6 +848,16 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
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break;
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}
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// If we are looking at a call sequence, we need to keep track of
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// the SP adjustment made by each instruction in the sequence.
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// This includes both the frame setup/destroy pseudos (handled above),
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// as well as other instructions that have side effects w.r.t the SP.
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// Note that this must come after eliminateFrameIndex, because
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// if I itself referred to a frame index, we shouldn't count its own
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// adjustment.
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if (MI && InsideCallSequence)
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SPAdj += TII.getSPAdjust(MI);
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if (DoIncr && I != BB->end()) ++I;
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// Update register states.
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@ -42,3 +42,8 @@ int TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF,
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FrameReg = RI->getFrameRegister(MF);
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return getFrameIndexOffset(MF, FI);
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}
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bool TargetFrameLowering::needsFrameIndexResolution(
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const MachineFunction &MF) const {
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return MF.getFrameInfo()->hasStackObjects();
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}
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@ -67,6 +67,11 @@ FunctionPass *createX86PadShortFunctions();
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/// to eliminate execution delays in some Atom processors.
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FunctionPass *createX86FixupLEAs();
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/// createX86CallFrameOptimization - Return a pass that optimizes
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/// the code-size of x86 call sequences. This is done by replacing
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/// esp-relative movs with pushes.
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FunctionPass *createX86CallFrameOptimization();
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} // End llvm namespace
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#endif
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400
contrib/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
Normal file
400
contrib/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
Normal file
@ -0,0 +1,400 @@
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//===----- X86CallFrameOptimization.cpp - Optimize x86 call sequences -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pass that optimizes call sequences on x86.
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// Currently, it converts movs of function parameters onto the stack into
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// pushes. This is beneficial for two main reasons:
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// 1) The push instruction encoding is much smaller than an esp-relative mov
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// 2) It is possible to push memory arguments directly. So, if the
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// the transformation is preformed pre-reg-alloc, it can help relieve
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// register pressure.
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//
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//===----------------------------------------------------------------------===//
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#include <algorithm>
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "X86MachineFunctionInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-cf-opt"
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cl::opt<bool> NoX86CFOpt("no-x86-call-frame-opt",
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cl::desc("Avoid optimizing x86 call frames for size"),
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cl::init(false), cl::Hidden);
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namespace {
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class X86CallFrameOptimization : public MachineFunctionPass {
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public:
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X86CallFrameOptimization() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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bool shouldPerformTransformation(MachineFunction &MF);
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bool adjustCallSequence(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I);
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MachineInstr *canFoldIntoRegPush(MachineBasicBlock::iterator FrameSetup,
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unsigned Reg);
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const char *getPassName() const override {
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return "X86 Optimize Call Frame";
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}
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const TargetInstrInfo *TII;
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const TargetFrameLowering *TFL;
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const MachineRegisterInfo *MRI;
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static char ID;
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};
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char X86CallFrameOptimization::ID = 0;
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}
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FunctionPass *llvm::createX86CallFrameOptimization() {
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return new X86CallFrameOptimization();
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}
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// This checks whether the transformation is legal and profitable
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bool X86CallFrameOptimization::shouldPerformTransformation(MachineFunction &MF) {
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if (NoX86CFOpt.getValue())
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return false;
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// We currently only support call sequences where *all* parameters.
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// are passed on the stack.
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// No point in running this in 64-bit mode, since some arguments are
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// passed in-register in all common calling conventions, so the pattern
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// we're looking for will never match.
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const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
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if (STI.is64Bit())
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return false;
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// You would expect straight-line code between call-frame setup and
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// call-frame destroy. You would be wrong. There are circumstances (e.g.
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// CMOV_GR8 expansion of a select that feeds a function call!) where we can
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// end up with the setup and the destroy in different basic blocks.
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// This is bad, and breaks SP adjustment.
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// So, check that all of the frames in the function are closed inside
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// the same block, and, for good measure, that there are no nested frames.
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int FrameSetupOpcode = TII->getCallFrameSetupOpcode();
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int FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
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for (MachineBasicBlock &BB : MF) {
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bool InsideFrameSequence = false;
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for (MachineInstr &MI : BB) {
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if (MI.getOpcode() == FrameSetupOpcode) {
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if (InsideFrameSequence)
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return false;
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InsideFrameSequence = true;
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}
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else if (MI.getOpcode() == FrameDestroyOpcode) {
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if (!InsideFrameSequence)
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return false;
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InsideFrameSequence = false;
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}
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}
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if (InsideFrameSequence)
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return false;
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}
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// Now that we know the transformation is legal, check if it is
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// profitable.
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// TODO: Add a heuristic that actually looks at the function,
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// and enable this for more cases.
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// This transformation is always a win when we expected to have
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// a reserved call frame. Under other circumstances, it may be either
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// a win or a loss, and requires a heuristic.
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// For now, enable it only for the relatively clear win cases.
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bool CannotReserveFrame = MF.getFrameInfo()->hasVarSizedObjects();
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if (CannotReserveFrame)
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return true;
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// For now, don't even try to evaluate the profitability when
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// not optimizing for size.
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AttributeSet FnAttrs = MF.getFunction()->getAttributes();
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bool OptForSize =
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FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
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Attribute::OptimizeForSize) ||
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FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
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if (!OptForSize)
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return false;
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// Stack re-alignment can make this unprofitable even in terms of size.
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// As mentioned above, a better heuristic is needed. For now, don't do this
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// when the required alignment is above 8. (4 would be the safe choice, but
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// some experimentation showed 8 is generally good).
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if (TFL->getStackAlignment() > 8)
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return false;
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return true;
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}
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bool X86CallFrameOptimization::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getSubtarget().getInstrInfo();
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TFL = MF.getSubtarget().getFrameLowering();
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MRI = &MF.getRegInfo();
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if (!shouldPerformTransformation(MF))
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return false;
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int FrameSetupOpcode = TII->getCallFrameSetupOpcode();
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bool Changed = false;
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
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if (I->getOpcode() == FrameSetupOpcode)
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Changed |= adjustCallSequence(MF, *BB, I);
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return Changed;
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}
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bool X86CallFrameOptimization::adjustCallSequence(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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// Check that this particular call sequence is amenable to the
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// transformation.
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const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
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MF.getSubtarget().getRegisterInfo());
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unsigned StackPtr = RegInfo.getStackRegister();
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int FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
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// We expect to enter this at the beginning of a call sequence
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assert(I->getOpcode() == TII->getCallFrameSetupOpcode());
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MachineBasicBlock::iterator FrameSetup = I++;
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// For globals in PIC mode, we can have some LEAs here.
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// Ignore them, they don't bother us.
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// TODO: Extend this to something that covers more cases.
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while (I->getOpcode() == X86::LEA32r)
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++I;
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// We expect a copy instruction here.
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// TODO: The copy instruction is a lowering artifact.
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// We should also support a copy-less version, where the stack
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// pointer is used directly.
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if (!I->isCopy() || !I->getOperand(0).isReg())
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return false;
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MachineBasicBlock::iterator SPCopy = I++;
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StackPtr = SPCopy->getOperand(0).getReg();
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// Scan the call setup sequence for the pattern we're looking for.
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// We only handle a simple case - a sequence of MOV32mi or MOV32mr
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// instructions, that push a sequence of 32-bit values onto the stack, with
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// no gaps between them.
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SmallVector<MachineInstr*, 4> MovVector(4, nullptr);
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unsigned int MaxAdjust = FrameSetup->getOperand(0).getImm() / 4;
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if (MaxAdjust > 4)
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MovVector.resize(MaxAdjust, nullptr);
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do {
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int Opcode = I->getOpcode();
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if (Opcode != X86::MOV32mi && Opcode != X86::MOV32mr)
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break;
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// We only want movs of the form:
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// movl imm/r32, k(%esp)
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// If we run into something else, bail.
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// Note that AddrBaseReg may, counter to its name, not be a register,
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// but rather a frame index.
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// TODO: Support the fi case. This should probably work now that we
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// have the infrastructure to track the stack pointer within a call
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// sequence.
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if (!I->getOperand(X86::AddrBaseReg).isReg() ||
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(I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
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!I->getOperand(X86::AddrScaleAmt).isImm() ||
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(I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
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(I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
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(I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
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!I->getOperand(X86::AddrDisp).isImm())
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return false;
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int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm();
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assert(StackDisp >= 0 && "Negative stack displacement when passing parameters");
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// We really don't want to consider the unaligned case.
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if (StackDisp % 4)
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return false;
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StackDisp /= 4;
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assert((size_t)StackDisp < MovVector.size() &&
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"Function call has more parameters than the stack is adjusted for.");
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// If the same stack slot is being filled twice, something's fishy.
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if (MovVector[StackDisp] != nullptr)
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return false;
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MovVector[StackDisp] = I;
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++I;
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} while (I != MBB.end());
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// We now expect the end of the sequence - a call and a stack adjust.
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if (I == MBB.end())
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return false;
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// For PCrel calls, we expect an additional COPY of the basereg.
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// If we find one, skip it.
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if (I->isCopy()) {
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if (I->getOperand(1).getReg() ==
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MF.getInfo<X86MachineFunctionInfo>()->getGlobalBaseReg())
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++I;
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else
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return false;
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}
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if (!I->isCall())
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return false;
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MachineBasicBlock::iterator Call = I;
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if ((++I)->getOpcode() != FrameDestroyOpcode)
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return false;
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// Now, go through the vector, and see that we don't have any gaps,
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// but only a series of 32-bit MOVs.
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int64_t ExpectedDist = 0;
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auto MMI = MovVector.begin(), MME = MovVector.end();
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for (; MMI != MME; ++MMI, ExpectedDist += 4)
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if (*MMI == nullptr)
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break;
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// If the call had no parameters, do nothing
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if (!ExpectedDist)
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return false;
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// We are either at the last parameter, or a gap.
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// Make sure it's not a gap
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for (; MMI != MME; ++MMI)
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if (*MMI != nullptr)
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return false;
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// Ok, we can in fact do the transformation for this call.
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// Do not remove the FrameSetup instruction, but adjust the parameters.
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// PEI will end up finalizing the handling of this.
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FrameSetup->getOperand(1).setImm(ExpectedDist);
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DebugLoc DL = I->getDebugLoc();
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// Now, iterate through the vector in reverse order, and replace the movs
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// with pushes. MOVmi/MOVmr doesn't have any defs, so no need to
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// replace uses.
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for (int Idx = (ExpectedDist / 4) - 1; Idx >= 0; --Idx) {
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MachineBasicBlock::iterator MOV = *MovVector[Idx];
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MachineOperand PushOp = MOV->getOperand(X86::AddrNumOperands);
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if (MOV->getOpcode() == X86::MOV32mi) {
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unsigned PushOpcode = X86::PUSHi32;
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// If the operand is a small (8-bit) immediate, we can use a
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// PUSH instruction with a shorter encoding.
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// Note that isImm() may fail even though this is a MOVmi, because
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// the operand can also be a symbol.
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if (PushOp.isImm()) {
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int64_t Val = PushOp.getImm();
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if (isInt<8>(Val))
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PushOpcode = X86::PUSH32i8;
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}
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BuildMI(MBB, Call, DL, TII->get(PushOpcode)).addOperand(PushOp);
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} else {
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unsigned int Reg = PushOp.getReg();
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// If PUSHrmm is not slow on this target, try to fold the source of the
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// push into the instruction.
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const X86Subtarget &ST = MF.getTarget().getSubtarget<X86Subtarget>();
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bool SlowPUSHrmm = ST.isAtom() || ST.isSLM();
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// Check that this is legal to fold. Right now, we're extremely
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// conservative about that.
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MachineInstr *DefMov = nullptr;
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if (!SlowPUSHrmm && (DefMov = canFoldIntoRegPush(FrameSetup, Reg))) {
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MachineInstr *Push = BuildMI(MBB, Call, DL, TII->get(X86::PUSH32rmm));
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unsigned NumOps = DefMov->getDesc().getNumOperands();
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for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
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Push->addOperand(DefMov->getOperand(i));
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DefMov->eraseFromParent();
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} else {
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BuildMI(MBB, Call, DL, TII->get(X86::PUSH32r)).addReg(Reg).getInstr();
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}
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}
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MBB.erase(MOV);
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}
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// The stack-pointer copy is no longer used in the call sequences.
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// There should not be any other users, but we can't commit to that, so:
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if (MRI->use_empty(SPCopy->getOperand(0).getReg()))
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SPCopy->eraseFromParent();
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// Once we've done this, we need to make sure PEI doesn't assume a reserved
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// frame.
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X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
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FuncInfo->setHasPushSequences(true);
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return true;
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}
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MachineInstr *X86CallFrameOptimization::canFoldIntoRegPush(
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MachineBasicBlock::iterator FrameSetup, unsigned Reg) {
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// Do an extremely restricted form of load folding.
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// ISel will often create patterns like:
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// movl 4(%edi), %eax
|
||||
// movl 8(%edi), %ecx
|
||||
// movl 12(%edi), %edx
|
||||
// movl %edx, 8(%esp)
|
||||
// movl %ecx, 4(%esp)
|
||||
// movl %eax, (%esp)
|
||||
// call
|
||||
// Get rid of those with prejudice.
|
||||
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
||||
return nullptr;
|
||||
|
||||
// Make sure this is the only use of Reg.
|
||||
if (!MRI->hasOneNonDBGUse(Reg))
|
||||
return nullptr;
|
||||
|
||||
MachineBasicBlock::iterator DefMI = MRI->getVRegDef(Reg);
|
||||
|
||||
// Make sure the def is a MOV from memory.
|
||||
// If the def is an another block, give up.
|
||||
if (DefMI->getOpcode() != X86::MOV32rm ||
|
||||
DefMI->getParent() != FrameSetup->getParent())
|
||||
return nullptr;
|
||||
|
||||
// Be careful with movs that load from a stack slot, since it may get
|
||||
// resolved incorrectly.
|
||||
// TODO: Again, we already have the infrastructure, so this should work.
|
||||
if (!DefMI->getOperand(1).isReg())
|
||||
return nullptr;
|
||||
|
||||
// Now, make sure everything else up until the ADJCALLSTACK is a sequence
|
||||
// of MOVs. To be less conservative would require duplicating a lot of the
|
||||
// logic from PeepholeOptimizer.
|
||||
// FIXME: A possibly better approach would be to teach the PeepholeOptimizer
|
||||
// to be smarter about folding into pushes.
|
||||
for (auto I = DefMI; I != FrameSetup; ++I)
|
||||
if (I->getOpcode() != X86::MOV32rm)
|
||||
return nullptr;
|
||||
|
||||
return DefMI;
|
||||
}
|
||||
@ -2735,7 +2735,7 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
|
||||
// Issue CALLSEQ_START
|
||||
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
|
||||
.addImm(NumBytes);
|
||||
.addImm(NumBytes).addImm(0);
|
||||
|
||||
// Walk the register/memloc assignments, inserting copies/loads.
|
||||
const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
|
||||
|
||||
@ -38,7 +38,34 @@ using namespace llvm;
|
||||
extern cl::opt<bool> ForceStackAlign;
|
||||
|
||||
bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
|
||||
return !MF.getFrameInfo()->hasVarSizedObjects();
|
||||
return !MF.getFrameInfo()->hasVarSizedObjects() &&
|
||||
!MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
|
||||
}
|
||||
|
||||
/// canSimplifyCallFramePseudos - If there is a reserved call frame, the
|
||||
/// call frame pseudos can be simplified. Having a FP, as in the default
|
||||
/// implementation, is not sufficient here since we can't always use it.
|
||||
/// Use a more nuanced condition.
|
||||
bool
|
||||
X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
|
||||
const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>
|
||||
(MF.getSubtarget().getRegisterInfo());
|
||||
return hasReservedCallFrame(MF) ||
|
||||
(hasFP(MF) && !TRI->needsStackRealignment(MF))
|
||||
|| TRI->hasBasePointer(MF);
|
||||
}
|
||||
|
||||
// needsFrameIndexResolution - Do we need to perform FI resolution for
|
||||
// this function. Normally, this is required only when the function
|
||||
// has any stack objects. However, FI resolution actually has another job,
|
||||
// not apparent from the title - it resolves callframesetup/destroy
|
||||
// that were not simplified earlier.
|
||||
// So, this is required for x86 functions that have push sequences even
|
||||
// when there are no stack objects.
|
||||
bool
|
||||
X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
|
||||
return MF.getFrameInfo()->hasStackObjects() ||
|
||||
MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
|
||||
}
|
||||
|
||||
/// hasFP - Return true if the specified function should have a dedicated frame
|
||||
@ -93,16 +120,6 @@ static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
|
||||
return X86::AND32ri;
|
||||
}
|
||||
|
||||
static unsigned getPUSHiOpcode(bool IsLP64, MachineOperand MO) {
|
||||
// We don't support LP64 for now.
|
||||
assert(!IsLP64);
|
||||
|
||||
if (MO.isImm() && isInt<8>(MO.getImm()))
|
||||
return X86::PUSH32i8;
|
||||
|
||||
return X86::PUSHi32;;
|
||||
}
|
||||
|
||||
static unsigned getLEArOpcode(unsigned IsLP64) {
|
||||
return IsLP64 ? X86::LEA64r : X86::LEA32r;
|
||||
}
|
||||
@ -1848,100 +1865,6 @@ void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
|
||||
#endif
|
||||
}
|
||||
|
||||
bool X86FrameLowering::
|
||||
convertArgMovsToPushes(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I, uint64_t Amount) const {
|
||||
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
||||
const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
|
||||
MF.getSubtarget().getRegisterInfo());
|
||||
unsigned StackPtr = RegInfo.getStackRegister();
|
||||
|
||||
// Scan the call setup sequence for the pattern we're looking for.
|
||||
// We only handle a simple case now - a sequence of MOV32mi or MOV32mr
|
||||
// instructions, that push a sequence of 32-bit values onto the stack, with
|
||||
// no gaps.
|
||||
std::map<int64_t, MachineBasicBlock::iterator> MovMap;
|
||||
do {
|
||||
int Opcode = I->getOpcode();
|
||||
if (Opcode != X86::MOV32mi && Opcode != X86::MOV32mr)
|
||||
break;
|
||||
|
||||
// We only want movs of the form:
|
||||
// movl imm/r32, k(%ecx)
|
||||
// If we run into something else, bail
|
||||
// Note that AddrBaseReg may, counterintuitively, not be a register...
|
||||
if (!I->getOperand(X86::AddrBaseReg).isReg() ||
|
||||
(I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
|
||||
!I->getOperand(X86::AddrScaleAmt).isImm() ||
|
||||
(I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
|
||||
(I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
|
||||
(I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
|
||||
!I->getOperand(X86::AddrDisp).isImm())
|
||||
return false;
|
||||
|
||||
int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm();
|
||||
|
||||
// We don't want to consider the unaligned case.
|
||||
if (StackDisp % 4)
|
||||
return false;
|
||||
|
||||
// If the same stack slot is being filled twice, something's fishy.
|
||||
if (!MovMap.insert(std::pair<int64_t, MachineInstr*>(StackDisp, I)).second)
|
||||
return false;
|
||||
|
||||
++I;
|
||||
} while (I != MBB.end());
|
||||
|
||||
// We now expect the end of the sequence - a call and a stack adjust.
|
||||
if (I == MBB.end())
|
||||
return false;
|
||||
if (!I->isCall())
|
||||
return false;
|
||||
MachineBasicBlock::iterator Call = I;
|
||||
if ((++I)->getOpcode() != TII.getCallFrameDestroyOpcode())
|
||||
return false;
|
||||
|
||||
// Now, go through the map, and see that we don't have any gaps,
|
||||
// but only a series of 32-bit MOVs.
|
||||
// Since std::map provides ordered iteration, the original order
|
||||
// of the MOVs doesn't matter.
|
||||
int64_t ExpectedDist = 0;
|
||||
for (auto MMI = MovMap.begin(), MME = MovMap.end(); MMI != MME;
|
||||
++MMI, ExpectedDist += 4)
|
||||
if (MMI->first != ExpectedDist)
|
||||
return false;
|
||||
|
||||
// Ok, everything looks fine. Do the transformation.
|
||||
DebugLoc DL = I->getDebugLoc();
|
||||
|
||||
// It's possible the original stack adjustment amount was larger than
|
||||
// that done by the pushes. If so, we still need a SUB.
|
||||
Amount -= ExpectedDist;
|
||||
if (Amount) {
|
||||
MachineInstr* Sub = BuildMI(MBB, Call, DL,
|
||||
TII.get(getSUBriOpcode(false, Amount)), StackPtr)
|
||||
.addReg(StackPtr).addImm(Amount);
|
||||
Sub->getOperand(3).setIsDead();
|
||||
}
|
||||
|
||||
// Now, iterate through the map in reverse order, and replace the movs
|
||||
// with pushes. MOVmi/MOVmr doesn't have any defs, so need to replace uses.
|
||||
for (auto MMI = MovMap.rbegin(), MME = MovMap.rend(); MMI != MME; ++MMI) {
|
||||
MachineBasicBlock::iterator MOV = MMI->second;
|
||||
MachineOperand PushOp = MOV->getOperand(X86::AddrNumOperands);
|
||||
|
||||
// Replace MOVmr with PUSH32r, and MOVmi with PUSHi of appropriate size
|
||||
int PushOpcode = X86::PUSH32r;
|
||||
if (MOV->getOpcode() == X86::MOV32mi)
|
||||
PushOpcode = getPUSHiOpcode(false, PushOp);
|
||||
|
||||
BuildMI(MBB, Call, DL, TII.get(PushOpcode)).addOperand(PushOp);
|
||||
MBB.erase(MOV);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void X86FrameLowering::
|
||||
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I) const {
|
||||
@ -1956,7 +1879,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
bool IsLP64 = STI.isTarget64BitLP64();
|
||||
DebugLoc DL = I->getDebugLoc();
|
||||
uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
|
||||
uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
|
||||
uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
|
||||
I = MBB.erase(I);
|
||||
|
||||
if (!reserveCallFrame) {
|
||||
@ -1976,24 +1899,18 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
|
||||
|
||||
MachineInstr *New = nullptr;
|
||||
if (Opcode == TII.getCallFrameSetupOpcode()) {
|
||||
// Try to convert movs to the stack into pushes.
|
||||
// We currently only look for a pattern that appears in 32-bit
|
||||
// calling conventions.
|
||||
if (!IsLP64 && convertArgMovsToPushes(MF, MBB, I, Amount))
|
||||
return;
|
||||
|
||||
New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
|
||||
StackPtr)
|
||||
.addReg(StackPtr)
|
||||
.addImm(Amount);
|
||||
} else {
|
||||
assert(Opcode == TII.getCallFrameDestroyOpcode());
|
||||
// Factor out the amount that gets handled inside the sequence
|
||||
// (Pushes of argument for frame setup, callee pops for frame destroy)
|
||||
Amount -= InternalAmt;
|
||||
|
||||
// Factor out the amount the callee already popped.
|
||||
Amount -= CalleeAmt;
|
||||
if (Amount) {
|
||||
if (Opcode == TII.getCallFrameSetupOpcode()) {
|
||||
New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)), StackPtr)
|
||||
.addReg(StackPtr).addImm(Amount);
|
||||
} else {
|
||||
assert(Opcode == TII.getCallFrameDestroyOpcode());
|
||||
|
||||
if (Amount) {
|
||||
unsigned Opc = getADDriOpcode(IsLP64, Amount);
|
||||
New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
|
||||
.addReg(StackPtr).addImm(Amount);
|
||||
@ -2011,13 +1928,13 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
return;
|
||||
}
|
||||
|
||||
if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
|
||||
if (Opcode == TII.getCallFrameDestroyOpcode() && InternalAmt) {
|
||||
// If we are performing frame pointer elimination and if the callee pops
|
||||
// something off the stack pointer, add it back. We do this until we have
|
||||
// more advanced stack pointer tracking ability.
|
||||
unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
|
||||
unsigned Opc = getSUBriOpcode(IsLP64, InternalAmt);
|
||||
MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
|
||||
.addReg(StackPtr).addImm(CalleeAmt);
|
||||
.addReg(StackPtr).addImm(InternalAmt);
|
||||
|
||||
// The EFLAGS implicit def is dead.
|
||||
New->getOperand(3).setIsDead();
|
||||
|
||||
@ -64,6 +64,8 @@ class X86FrameLowering : public TargetFrameLowering {
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const override;
|
||||
bool hasReservedCallFrame(const MachineFunction &MF) const override;
|
||||
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
|
||||
bool needsFrameIndexResolution(const MachineFunction &MF) const override;
|
||||
|
||||
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
|
||||
int getFrameIndexReference(const MachineFunction &MF, int FI,
|
||||
|
||||
@ -43,15 +43,18 @@ let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
|
||||
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
||||
// sub / add which can clobber EFLAGS.
|
||||
let Defs = [ESP, EFLAGS], Uses = [ESP] in {
|
||||
def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
|
||||
def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKDOWN",
|
||||
[(X86callseq_start timm:$amt)]>,
|
||||
[]>,
|
||||
Requires<[NotLP64]>;
|
||||
def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKUP",
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)]>,
|
||||
Requires<[NotLP64]>;
|
||||
}
|
||||
def : Pat<(X86callseq_start timm:$amt1),
|
||||
(ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
|
||||
|
||||
|
||||
// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
|
||||
// a stack adjustment and the codegen must know that they may modify the stack
|
||||
@ -59,16 +62,17 @@ def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
||||
// sub / add which can clobber EFLAGS.
|
||||
let Defs = [RSP, EFLAGS], Uses = [RSP] in {
|
||||
def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
|
||||
def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKDOWN",
|
||||
[(X86callseq_start timm:$amt)]>,
|
||||
[]>,
|
||||
Requires<[IsLP64]>;
|
||||
def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKUP",
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)]>,
|
||||
Requires<[IsLP64]>;
|
||||
}
|
||||
|
||||
def : Pat<(X86callseq_start timm:$amt1),
|
||||
(ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
|
||||
|
||||
|
||||
// x86-64 va_start lowering magic.
|
||||
|
||||
@ -1692,6 +1692,58 @@ X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
|
||||
return false;
|
||||
}
|
||||
|
||||
int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
|
||||
const MachineFunction *MF = MI->getParent()->getParent();
|
||||
const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
|
||||
|
||||
if (MI->getOpcode() == getCallFrameSetupOpcode() ||
|
||||
MI->getOpcode() == getCallFrameDestroyOpcode()) {
|
||||
unsigned StackAlign = TFI->getStackAlignment();
|
||||
int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
|
||||
StackAlign;
|
||||
|
||||
SPAdj -= MI->getOperand(1).getImm();
|
||||
|
||||
if (MI->getOpcode() == getCallFrameSetupOpcode())
|
||||
return SPAdj;
|
||||
else
|
||||
return -SPAdj;
|
||||
}
|
||||
|
||||
// To know whether a call adjusts the stack, we need information
|
||||
// that is bound to the following ADJCALLSTACKUP pseudo.
|
||||
// Look for the next ADJCALLSTACKUP that follows the call.
|
||||
if (MI->isCall()) {
|
||||
const MachineBasicBlock* MBB = MI->getParent();
|
||||
auto I = ++MachineBasicBlock::const_iterator(MI);
|
||||
for (auto E = MBB->end(); I != E; ++I) {
|
||||
if (I->getOpcode() == getCallFrameDestroyOpcode() ||
|
||||
I->isCall())
|
||||
break;
|
||||
}
|
||||
|
||||
// If we could not find a frame destroy opcode, then it has already
|
||||
// been simplified, so we don't care.
|
||||
if (I->getOpcode() != getCallFrameDestroyOpcode())
|
||||
return 0;
|
||||
|
||||
return -(I->getOperand(1).getImm());
|
||||
}
|
||||
|
||||
// Currently handle only PUSHes we can reasonably expect to see
|
||||
// in call sequences
|
||||
switch (MI->getOpcode()) {
|
||||
default:
|
||||
return 0;
|
||||
case X86::PUSH32i8:
|
||||
case X86::PUSH32r:
|
||||
case X86::PUSH32rmm:
|
||||
case X86::PUSH32rmr:
|
||||
case X86::PUSHi32:
|
||||
return 4;
|
||||
}
|
||||
}
|
||||
|
||||
/// isFrameOperand - Return true and the FrameIndex if the specified
|
||||
/// operand and follow operands form a reference to the stack frame.
|
||||
bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
|
||||
|
||||
@ -175,6 +175,11 @@ class X86InstrInfo final : public X86GenInstrInfo {
|
||||
///
|
||||
const X86RegisterInfo &getRegisterInfo() const { return RI; }
|
||||
|
||||
/// getSPAdjust - This returns the stack pointer adjustment made by
|
||||
/// this instruction. For x86, we need to handle more complex call
|
||||
/// sequences involving PUSHes.
|
||||
int getSPAdjust(const MachineInstr *MI) const override;
|
||||
|
||||
/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
|
||||
/// extension instruction. That is, it's like a copy where it's legal for the
|
||||
/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
|
||||
|
||||
@ -77,6 +77,9 @@ class X86MachineFunctionInfo : public MachineFunctionInfo {
|
||||
unsigned ArgumentStackSize;
|
||||
/// NumLocalDynamics - Number of local-dynamic TLS accesses.
|
||||
unsigned NumLocalDynamics;
|
||||
/// HasPushSequences - Keeps track of whether this function uses sequences
|
||||
/// of pushes to pass function parameters.
|
||||
bool HasPushSequences;
|
||||
|
||||
private:
|
||||
/// ForwardedMustTailRegParms - A list of virtual and physical registers
|
||||
@ -97,7 +100,8 @@ class X86MachineFunctionInfo : public MachineFunctionInfo {
|
||||
VarArgsGPOffset(0),
|
||||
VarArgsFPOffset(0),
|
||||
ArgumentStackSize(0),
|
||||
NumLocalDynamics(0) {}
|
||||
NumLocalDynamics(0),
|
||||
HasPushSequences(false) {}
|
||||
|
||||
explicit X86MachineFunctionInfo(MachineFunction &MF)
|
||||
: ForceFramePointer(false),
|
||||
@ -113,11 +117,15 @@ class X86MachineFunctionInfo : public MachineFunctionInfo {
|
||||
VarArgsGPOffset(0),
|
||||
VarArgsFPOffset(0),
|
||||
ArgumentStackSize(0),
|
||||
NumLocalDynamics(0) {}
|
||||
NumLocalDynamics(0),
|
||||
HasPushSequences(false) {}
|
||||
|
||||
bool getForceFramePointer() const { return ForceFramePointer;}
|
||||
void setForceFramePointer(bool forceFP) { ForceFramePointer = forceFP; }
|
||||
|
||||
bool getHasPushSequences() const { return HasPushSequences; }
|
||||
void setHasPushSequences(bool HasPush) { HasPushSequences = HasPush; }
|
||||
|
||||
bool getRestoreBasePointer() const { return RestoreBasePointerOffset!=0; }
|
||||
void setRestoreBasePointer(const MachineFunction *MF);
|
||||
int getRestoreBasePointerOffset() const {return RestoreBasePointerOffset; }
|
||||
|
||||
@ -468,8 +468,6 @@ void
|
||||
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected");
|
||||
|
||||
MachineInstr &MI = *II;
|
||||
MachineFunction &MF = *MI.getParent()->getParent();
|
||||
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
||||
@ -506,6 +504,9 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
} else
|
||||
FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
|
||||
|
||||
if (BasePtr == StackPtr)
|
||||
FIOffset += SPAdj;
|
||||
|
||||
// The frame index format for stackmaps and patchpoints is different from the
|
||||
// X86 format. It only has a FI and an offset.
|
||||
if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
|
||||
|
||||
@ -154,6 +154,7 @@ class X86PassConfig : public TargetPassConfig {
|
||||
void addIRPasses() override;
|
||||
bool addInstSelector() override;
|
||||
bool addILPOpts() override;
|
||||
void addPreRegAlloc() override;
|
||||
void addPostRegAlloc() override;
|
||||
void addPreEmitPass() override;
|
||||
};
|
||||
@ -187,6 +188,10 @@ bool X86PassConfig::addILPOpts() {
|
||||
return true;
|
||||
}
|
||||
|
||||
void X86PassConfig::addPreRegAlloc() {
|
||||
addPass(createX86CallFrameOptimization());
|
||||
}
|
||||
|
||||
void X86PassConfig::addPostRegAlloc() {
|
||||
addPass(createX86FloatingPointStackifierPass());
|
||||
}
|
||||
|
||||
@ -6,6 +6,7 @@ LIB= llvmx86codegen
|
||||
|
||||
SRCDIR= lib/Target/X86
|
||||
SRCS= X86AsmPrinter.cpp \
|
||||
X86CallFrameOptimization.cpp \
|
||||
X86FastISel.cpp \
|
||||
X86FixupLEAs.cpp \
|
||||
X86FloatingPoint.cpp \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user