Add/polish some defines.
MFC after: 13 days
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ae3adc0645
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=323058
@ -106,31 +106,36 @@ struct ntb_plx_softc {
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#define PLX_NTX_LINK_OFFSET 0x01000
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/* Bases of NTx our/peer interface registers */
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#define PLX_NTX_OUR(sc) \
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#define PLX_NTX_OUR_BASE(sc) \
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(PLX_NTX_BASE(sc) + ((sc)->link ? PLX_NTX_LINK_OFFSET : 0))
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#define PLX_NTX_PEER(sc) \
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#define PLX_NTX_PEER_BASE(sc) \
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(PLX_NTX_BASE(sc) + ((sc)->link ? 0 : PLX_NTX_LINK_OFFSET))
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/* Read/write NTx our interface registers */
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#define NTX_READ(sc, reg) \
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bus_read_4((sc)->conf_res, PLX_NTX_OUR(sc) + (reg))
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#define NTX_WRITE(sc, reg, val) \
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bus_write_4((sc)->conf_res, PLX_NTX_OUR(sc) + (reg), (val))
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#define NTX_READ(sc, reg) \
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bus_read_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg))
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#define NTX_WRITE(sc, reg, val) \
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bus_write_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg), (val))
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/* Read/write NTx peer interface registers */
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#define PNTX_READ(sc, reg) \
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bus_read_4((sc)->conf_res, PLX_NTX_PEER(sc) + (reg))
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#define PNTX_WRITE(sc, reg, val) \
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bus_write_4((sc)->conf_res, PLX_NTX_PEER(sc) + (reg), (val))
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#define PNTX_READ(sc, reg) \
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bus_read_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg))
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#define PNTX_WRITE(sc, reg, val) \
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bus_write_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg), (val))
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/* Read/write B2B NTx registers */
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#define BNTX_READ(sc, reg) \
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#define BNTX_READ(sc, reg) \
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bus_read_4((sc)->mw_info[(sc)->b2b_mw].mw_res, \
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PLX_NTX_BASE(sc) + (reg))
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#define BNTX_WRITE(sc, reg, val) \
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#define BNTX_WRITE(sc, reg, val) \
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bus_write_4((sc)->mw_info[(sc)->b2b_mw].mw_res, \
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PLX_NTX_BASE(sc) + (reg), (val))
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#define PLX_PORT_BASE(p) ((p) << 12)
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#define PLX_STATION_PORT_BASE(sc) PLX_PORT_BASE((sc)->port & ~7)
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#define PLX_PORT_CONTROL(sc) (PLX_STATION_PORT_BASE(sc) + 0x208)
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static int ntb_plx_init(device_t dev);
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static int ntb_plx_detach(device_t dev);
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static int ntb_plx_mw_set_trans_internal(device_t dev, unsigned mw_idx);
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@ -379,21 +384,16 @@ ntb_plx_attach(device_t dev)
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* Make sure they are present and enabled by writing to them.
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* XXX: Its a hack, but standard 8 registers are not enough.
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*/
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sc->spad_offp1 = sc->spad_off1 = PLX_NTX_OUR_BASE(sc) + 0xc6c;
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sc->spad_offp2 = sc->spad_off2 = PLX_PORT_BASE(sc->ntx * 8) + 0x20c;
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if (sc->b2b_mw >= 0) {
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/* In NTB-to-NTB mode each side has own scratchpads. */
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sc->spad_count1 = PLX_NUM_SPAD;
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sc->spad_off1 = PLX_NTX_OUR(sc) + 0xc6c;
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sc->spad_off2 = (sc->ntx == 0) ? 0x0020c : 0x0820c;
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sc->spad_offp1 = sc->spad_off1;
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sc->spad_offp2 = sc->spad_off2;
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bus_write_4(sc->conf_res, sc->spad_off2, 0x12345678);
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if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678)
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sc->spad_count2 = PLX_NUM_SPAD_PATT;
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} else {
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sc->spad_count1 = PLX_NUM_SPAD / 2;
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sc->spad_off1 = PLX_NTX_OUR(sc) + 0xc6c;
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sc->spad_off2 = (sc->ntx == 0) ? 0x0020c : 0x0820c;
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sc->spad_offp1 = sc->spad_off1;
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sc->spad_offp2 = sc->spad_off2;
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/* Otherwise we have share scratchpads with the peer. */
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if (sc->link) {
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sc->spad_off1 += PLX_NUM_SPAD / 2 * 4;
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sc->spad_off2 += PLX_NUM_SPAD_PATT / 2 * 4;
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@ -401,6 +401,7 @@ ntb_plx_attach(device_t dev)
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sc->spad_offp1 += PLX_NUM_SPAD / 2 * 4;
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sc->spad_offp2 += PLX_NUM_SPAD_PATT / 2 * 4;
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}
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sc->spad_count1 = PLX_NUM_SPAD / 2;
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bus_write_4(sc->conf_res, sc->spad_off2, 0x12345678);
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if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678)
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sc->spad_count2 = PLX_NUM_SPAD_PATT / 2;
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@ -473,7 +474,7 @@ ntb_plx_link_enable(device_t dev, enum ntb_speed speed __unused,
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return (0);
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}
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reg = ((sc->port & ~7) << 12) | 0x208;
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reg = PLX_PORT_CONTROL(sc);
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val = bus_read_4(sc->conf_res, reg);
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if ((val & (1 << (sc->port & 7))) == 0) {
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/* If already enabled, generate fake link event and exit. */
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@ -495,7 +496,7 @@ ntb_plx_link_disable(device_t dev)
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if (sc->link)
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return (0);
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reg = ((sc->port & ~7) << 12) | 0x208;
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reg = PLX_PORT_CONTROL(sc);
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val = bus_read_4(sc->conf_res, reg);
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val |= (1 << (sc->port & 7));
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bus_write_4(sc->conf_res, reg, val);
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@ -512,7 +513,7 @@ ntb_plx_link_enabled(device_t dev)
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if (sc->link)
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return (TRUE);
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reg = ((sc->port & ~7) << 12) | 0x208;
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reg = PLX_PORT_CONTROL(sc);
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val = bus_read_4(sc->conf_res, reg);
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return ((val & (1 << (sc->port & 7))) == 0);
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}
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