Add support for the 'invept' and 'invvpid' instructions. Beyond simply
adding appropriate table entries, the assembler had to be adjusted as these are the first non-SSE instructions to use a 3-byte opcode (and a mandatory prefix to boot). MFC after: 1 month
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6632f45773
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11a08d62da
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=238167
@ -3990,6 +3990,16 @@ output_insn (void)
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goto check_prefix;
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}
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}
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else if (i.tm.base_opcode == 0x660f3880 || i.tm.base_opcode == 0x660f3881)
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{
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/* invept and invvpid are 3 byte instructions with a
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mandatory prefix. */
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if (i.tm.base_opcode & 0xff000000)
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{
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prefix = (i.tm.base_opcode >> 24) & 0xff;
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add_prefix (prefix);
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}
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}
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else if ((i.tm.base_opcode & 0xff0000) != 0)
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{
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prefix = (i.tm.base_opcode >> 16) & 0xff;
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@ -4029,6 +4039,12 @@ output_insn (void)
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p = frag_more (3);
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*p++ = (i.tm.base_opcode >> 16) & 0xff;
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}
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else if (i.tm.base_opcode == 0x660f3880 ||
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i.tm.base_opcode == 0x660f3881)
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{
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p = frag_more (3);
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*p++ = (i.tm.base_opcode >> 16) & 0xff;
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}
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else
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p = frag_more (2);
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@ -213,6 +213,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Ew { OP_E, w_mode }
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#define M { OP_M, 0 } /* lea, lgdt, etc. */
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#define Ma { OP_M, v_mode }
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#define Mo { OP_M, o_mode }
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#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
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#define Mq { OP_M, q_mode }
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#define Gb { OP_G, b_mode }
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@ -540,6 +541,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define PREGRP95 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 95 } }
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#define PREGRP96 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 96 } }
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#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } }
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#define PREGRP98 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 98 } }
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#define PREGRP99 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 99 } }
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#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
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@ -2586,6 +2589,22 @@ static const struct dis386 prefix_user_table[][4] = {
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{ "punpckldq",{ MX, EMq } },
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{ "(bad)", { XX } },
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},
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/* PREGRP98 */
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "invept", { Gm, Mo } },
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{ "(bad)", { XX } },
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},
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/* PREGRP99 */
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{
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "invvpid",{ Gm, Mo } },
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{ "(bad)", { XX } },
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},
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};
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static const struct dis386 x86_64_table[][2] = {
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@ -2755,8 +2774,8 @@ static const struct dis386 three_byte_table[][256] = {
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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/* 80 */
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ PREGRP98 },
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{ PREGRP99 },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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@ -5884,7 +5903,7 @@ static void
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OP_M (int bytemode, int sizeflag)
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{
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if (modrm.mod == 3)
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/* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
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/* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst,invept,invvpid modrm */
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BadOp ();
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else
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OP_E (bytemode, sizeflag);
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@ -1289,6 +1289,10 @@ mwait, 2, 0xf01, 0xc9, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
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mwait, 2, 0xf01, 0xc9, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64, Reg64 }
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// VMX instructions.
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invept, 2, 0x660f3880, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
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invept, 2, 0x660f3880, None, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
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invvpid, 2, 0x660f3881, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
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invvpid, 2, 0x660f3881, None, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
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vmcall, 0, 0xf01, 0xc1, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
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vmclear, 1, 0x660fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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vmlaunch, 0, 0xf01, 0xc2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
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@ -3625,6 +3625,22 @@ const template i386_optab[] =
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No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
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{ Reg64,
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Reg64 } },
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{ "invept", 2, 0x660f3880, None, CpuVMX|CpuNo64,
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Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32 } },
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{ "invept", 2, 0x660f3880, None, CpuVMX|Cpu64,
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Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "invvpid", 2, 0x660f3881, None, CpuVMX|CpuNo64,
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Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg32 } },
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{ "invvpid", 2, 0x660f3881, None, CpuVMX|Cpu64,
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Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
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Reg64 } },
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{ "vmcall", 0, 0xf01, 0xc1, CpuVMX,
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No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
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{ 0 } },
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