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Add support for the 'invept' and 'invvpid' instructions. Beyond simply

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adding appropriate table entries, the assembler had to be adjusted as
these are the first non-SSE instructions to use a 3-byte opcode (and a
mandatory prefix to boot).

MFC after:	1 month
This commit is contained in:
John Baldwin 2012-07-06 14:28:18 +00:00
parent 6632f45773
commit 11a08d62da
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=238167
4 changed files with 58 additions and 3 deletions
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16
contrib/binutils/gas/config/tc-i386.c
View File

@ -3990,6 +3990,16 @@ output_insn (void)
goto check_prefix;
}
}
else if (i.tm.base_opcode == 0x660f3880 || i.tm.base_opcode == 0x660f3881)
{
/* invept and invvpid are 3 byte instructions with a
mandatory prefix. */
if (i.tm.base_opcode & 0xff000000)
{
prefix = (i.tm.base_opcode >> 24) & 0xff;
add_prefix (prefix);
}
}
else if ((i.tm.base_opcode & 0xff0000) != 0)
{
prefix = (i.tm.base_opcode >> 16) & 0xff;
@ -4029,6 +4039,12 @@ output_insn (void)
p = frag_more (3);
*p++ = (i.tm.base_opcode >> 16) & 0xff;
}
else if (i.tm.base_opcode == 0x660f3880 ||
i.tm.base_opcode == 0x660f3881)
{
p = frag_more (3);
*p++ = (i.tm.base_opcode >> 16) & 0xff;
}
else
p = frag_more (2);

25
contrib/binutils/opcodes/i386-dis.c
View File

@ -213,6 +213,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Ew { OP_E, w_mode }
#define M { OP_M, 0 } /* lea, lgdt, etc. */
#define Ma { OP_M, v_mode }
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
#define Gb { OP_G, b_mode }
@ -540,6 +541,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define PREGRP95 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 95 } }
#define PREGRP96 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 96 } }
#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } }
#define PREGRP98 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 98 } }
#define PREGRP99 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 99 } }
#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
@ -2586,6 +2589,22 @@ static const struct dis386 prefix_user_table[][4] = {
{ "punpckldq",{ MX, EMq } },
{ "(bad)", { XX } },
},
/* PREGRP98 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "invept", { Gm, Mo } },
{ "(bad)", { XX } },
},
/* PREGRP99 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "invvpid",{ Gm, Mo } },
{ "(bad)", { XX } },
},
};
static const struct dis386 x86_64_table[][2] = {
@ -2755,8 +2774,8 @@ static const struct dis386 three_byte_table[][256] = {
{ "(bad)", { XX } },
{ "(bad)", { XX } },
/* 80 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ PREGRP98 },
{ PREGRP99 },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
@ -5884,7 +5903,7 @@ static void
OP_M (int bytemode, int sizeflag)
{
if (modrm.mod == 3)
/* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
/* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst,invept,invvpid modrm */
BadOp ();
else
OP_E (bytemode, sizeflag);

4
contrib/binutils/opcodes/i386-opc.tbl
View File

@ -1289,6 +1289,10 @@ mwait, 2, 0xf01, 0xc9, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
mwait, 2, 0xf01, 0xc9, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64, Reg64 }
// VMX instructions.
invept, 2, 0x660f3880, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
invept, 2, 0x660f3880, None, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
invvpid, 2, 0x660f3881, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
invvpid, 2, 0x660f3881, None, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
vmcall, 0, 0xf01, 0xc1, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
vmclear, 1, 0x660fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
vmlaunch, 0, 0xf01, 0xc2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }

16
contrib/binutils/opcodes/i386-tbl.h
View File

@ -3625,6 +3625,22 @@ const template i386_optab[] =
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
{ Reg64,
Reg64 } },
{ "invept", 2, 0x660f3880, None, CpuVMX|CpuNo64,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
Reg32 } },
{ "invept", 2, 0x660f3880, None, CpuVMX|Cpu64,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
Reg64 } },
{ "invvpid", 2, 0x660f3881, None, CpuVMX|CpuNo64,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
Reg32 } },
{ "invvpid", 2, 0x660f3881, None, CpuVMX|Cpu64,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
Reg64 } },
{ "vmcall", 0, 0xf01, 0xc1, CpuVMX,
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
{ 0 } },