Enhance Armada 38x SoC identification string

Add hw_clockrate and CPU frequency, basing on sample-at-reset
configuration.

Submitted by:	Arnaud Ysmal <arnaud.ysmal@stormshield.eu>
		Marcin Wojtas <mw@semihalf.com>
Obtained from: Stormshield, Semihalf
Sponsored by: Stormshield
Reviewed by: andrew
Differential revision: https://reviews.freebsd.org/D10899

sys/arm/mv/armada38x/armada38x.c

@@ -29,6 +29,7 @@
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
+#include <sys/sysctl.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
 
@@ -43,6 +44,10 @@ int armada38x_scu_enable(void);
 int armada38x_win_set_iosync_barrier(void);
 int armada38x_mbus_optimization(void);
 
+static int hw_clockrate;
+SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
+    &hw_clockrate, 0, "CPU instruction clock rate");
+
 uint32_t
 get_tclk(void)
 {
@@ -60,6 +65,29 @@ get_tclk(void)
 		return (TCLK_200MHZ);
 }
 
+uint32_t
+get_cpu_freq(void)
+{
+	uint32_t sar;
+
+	static const uint32_t cpu_frequencies[] = {
+		0, 0, 0, 0,
+		1066, 0, 0, 0,
+		1332, 0, 0, 0,
+		1600, 0, 0, 0,
+		1866, 0, 0, 2000
+	};
+
+	sar = (uint32_t)get_sar_value();
+	sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
+	if (sar >= nitems(cpu_frequencies))
+		return (0);
+
+	hw_clockrate = cpu_frequencies[sar];
+
+	return (hw_clockrate * 1000 * 1000);
+}
+
 int
 armada38x_win_set_iosync_barrier(void)
 {

sys/arm/mv/armadaxp/armadaxp.c

@@ -136,6 +136,13 @@ get_tclk(void)
 		return (TCLK_200MHZ);
 }
 
+uint32_t
+get_cpu_freq(void)
+{
+
+	return (0);
+}
+
 static uint32_t
 count_l2clk(void)
 {

sys/arm/mv/discovery/discovery.c

@@ -109,3 +109,10 @@ get_tclk(void)
 		panic("Unknown TCLK settings!");
 	}
 }
+
+uint32_t
+get_cpu_freq(void)
+{
+
+	return (0);
+}

sys/arm/mv/kirkwood/kirkwood.c

@@ -79,3 +79,10 @@ get_tclk(void)
 
 	return (TCLK_166MHZ);
 }
+
+uint32_t
+get_cpu_freq(void)
+{
+
+	return (0);
+}

sys/arm/mv/mv_common.c

@@ -419,7 +419,7 @@ soc_id(uint32_t *dev, uint32_t *rev)
 static void
 soc_identify(void)
 {
-	uint32_t d, r, size, mode;
+	uint32_t d, r, size, mode, freq;
 	const char *dev;
 	const char *rev;
 
@@ -512,7 +512,11 @@ soc_identify(void)
 	printf("%s", dev);
 	if (*rev != '\0')
 		printf(" rev %s", rev);
-	printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
+	printf(", TClock %dMHz", get_tclk() / 1000 / 1000);
+	freq = get_cpu_freq();
+	if (freq != 0)
+		printf(", Frequency %dMHz", freq / 1000 / 1000);
+	printf("\n");
 
 	mode = read_cpu_ctrl(CPU_CONFIG);
 	printf("  Instruction cache prefetch %s, data cache prefetch %s\n",

sys/arm/mv/mvreg.h

@@ -355,6 +355,9 @@
 #define TCLK_300MHZ		300000000
 #define TCLK_667MHZ		667000000
 
+#define	A38X_CPU_DDR_CLK_MASK	0x00007c00
+#define	A38X_CPU_DDR_CLK_SHIFT	10
+
 /*
  * CPU Cache Configuration
  */

sys/arm/mv/mvvar.h

@@ -104,6 +104,7 @@ uint32_t ddr_target(int i);
 
 uint32_t cpu_extra_feat(void);
 uint32_t get_tclk(void);
+uint32_t get_cpu_freq(void);
 uint32_t get_l2clk(void);
 uint32_t read_cpu_ctrl(uint32_t);
 void write_cpu_ctrl(uint32_t, uint32_t);

sys/arm/mv/orion/orion.c

@@ -100,3 +100,10 @@ get_tclk(void)
 		panic("Unknown TCLK settings!");
 	}
 }
+
+uint32_t
+get_cpu_freq(void)
+{
+
+	return (0);
+}