Enhance Armada 38x SoC identification string
Add hw_clockrate and CPU frequency, basing on sample-at-reset configuration. Submitted by: Arnaud Ysmal <arnaud.ysmal@stormshield.eu> Marcin Wojtas <mw@semihalf.com> Obtained from: Stormshield, Semihalf Sponsored by: Stormshield Reviewed by: andrew Differential revision: https://reviews.freebsd.org/D10899
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=320005
@ -29,6 +29,7 @@
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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@ -43,6 +44,10 @@ int armada38x_scu_enable(void);
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int armada38x_win_set_iosync_barrier(void);
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int armada38x_mbus_optimization(void);
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static int hw_clockrate;
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SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
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&hw_clockrate, 0, "CPU instruction clock rate");
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uint32_t
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get_tclk(void)
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{
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@ -60,6 +65,29 @@ get_tclk(void)
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return (TCLK_200MHZ);
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}
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uint32_t
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get_cpu_freq(void)
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{
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uint32_t sar;
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static const uint32_t cpu_frequencies[] = {
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0, 0, 0, 0,
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1066, 0, 0, 0,
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1332, 0, 0, 0,
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1600, 0, 0, 0,
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1866, 0, 0, 2000
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};
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sar = (uint32_t)get_sar_value();
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sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
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if (sar >= nitems(cpu_frequencies))
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return (0);
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hw_clockrate = cpu_frequencies[sar];
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return (hw_clockrate * 1000 * 1000);
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}
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int
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armada38x_win_set_iosync_barrier(void)
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{
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@ -136,6 +136,13 @@ get_tclk(void)
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return (TCLK_200MHZ);
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}
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uint32_t
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get_cpu_freq(void)
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{
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return (0);
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}
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static uint32_t
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count_l2clk(void)
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{
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@ -109,3 +109,10 @@ get_tclk(void)
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panic("Unknown TCLK settings!");
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}
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}
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uint32_t
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get_cpu_freq(void)
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{
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return (0);
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}
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@ -79,3 +79,10 @@ get_tclk(void)
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return (TCLK_166MHZ);
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}
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uint32_t
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get_cpu_freq(void)
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{
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return (0);
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}
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@ -419,7 +419,7 @@ soc_id(uint32_t *dev, uint32_t *rev)
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static void
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soc_identify(void)
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{
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uint32_t d, r, size, mode;
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uint32_t d, r, size, mode, freq;
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const char *dev;
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const char *rev;
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@ -512,7 +512,11 @@ soc_identify(void)
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printf("%s", dev);
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if (*rev != '\0')
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printf(" rev %s", rev);
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printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
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printf(", TClock %dMHz", get_tclk() / 1000 / 1000);
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freq = get_cpu_freq();
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if (freq != 0)
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printf(", Frequency %dMHz", freq / 1000 / 1000);
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printf("\n");
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mode = read_cpu_ctrl(CPU_CONFIG);
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printf(" Instruction cache prefetch %s, data cache prefetch %s\n",
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@ -355,6 +355,9 @@
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#define TCLK_300MHZ 300000000
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#define TCLK_667MHZ 667000000
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#define A38X_CPU_DDR_CLK_MASK 0x00007c00
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#define A38X_CPU_DDR_CLK_SHIFT 10
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/*
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* CPU Cache Configuration
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*/
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@ -104,6 +104,7 @@ uint32_t ddr_target(int i);
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uint32_t cpu_extra_feat(void);
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uint32_t get_tclk(void);
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uint32_t get_cpu_freq(void);
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uint32_t get_l2clk(void);
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uint32_t read_cpu_ctrl(uint32_t);
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void write_cpu_ctrl(uint32_t, uint32_t);
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@ -100,3 +100,10 @@ get_tclk(void)
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panic("Unknown TCLK settings!");
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}
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}
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uint32_t
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get_cpu_freq(void)
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{
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return (0);
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}
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