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Mark 64-bit arm64 hypervisor registers with UL

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These are 64-bit. Mark them as unsigned long so we don't rely on
undefined behaviour or shift a 32-bit value more than 32 bits.

Sponsored by:	Innovate UK
Sponsored by:	The FreeBSD Foundation
This commit is contained in:
Andrew Turner 2022-09-28 14:39:45 +01:00
parent eee0f7aea4
commit 12c1c65d8a
1 changed files with 39 additions and 39 deletions
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78
sys/arm64/include/hypervisor.h
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@ -121,48 +121,48 @@
#define HPFAR_EL2_FIPA_MASK 0xfffffffff0
/* ICC_SRE_EL2 */
#define ICC_SRE_EL2_SRE (1U << 0)
#define ICC_SRE_EL2_EN (1U << 3)
#define ICC_SRE_EL2_SRE (1UL << 0)
#define ICC_SRE_EL2_EN (1UL << 3)
/* SCTLR_EL2 - System Control Register */
#define SCTLR_EL2_RES1 0x30c50830
#define SCTLR_EL2_M_SHIFT 0
#define SCTLR_EL2_M (0x1 << SCTLR_EL2_M_SHIFT)
#define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT)
#define SCTLR_EL2_A_SHIFT 1
#define SCTLR_EL2_A (0x1 << SCTLR_EL2_A_SHIFT)
#define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT)
#define SCTLR_EL2_C_SHIFT 2
#define SCTLR_EL2_C (0x1 << SCTLR_EL2_C_SHIFT)
#define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT)
#define SCTLR_EL2_SA_SHIFT 3
#define SCTLR_EL2_SA (0x1 << SCTLR_EL2_SA_SHIFT)
#define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT)
#define SCTLR_EL2_I_SHIFT 12
#define SCTLR_EL2_I (0x1 << SCTLR_EL2_I_SHIFT)
#define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT)
#define SCTLR_EL2_WXN_SHIFT 19
#define SCTLR_EL2_WXN (0x1 << SCTLR_EL2_WXN_SHIFT)
#define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT)
#define SCTLR_EL2_EE_SHIFT 25
#define SCTLR_EL2_EE (0x1 << SCTLR_EL2_EE_SHIFT)
#define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT)
/* TCR_EL2 - Translation Control Register */
#define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23))
#define TCR_EL2_T0SZ_SHIFT 0
#define TCR_EL2_T0SZ_MASK (0x3f << TCR_EL2_T0SZ_SHIFT)
#define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT)
#define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT)
/* Bits 7:6 are reserved */
#define TCR_EL2_IRGN0_SHIFT 8
#define TCR_EL2_IRGN0_MASK (0x3 << TCR_EL2_IRGN0_SHIFT)
#define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT)
#define TCR_EL2_ORGN0_SHIFT 10
#define TCR_EL2_ORGN0_MASK (0x3 << TCR_EL2_ORGN0_SHIFT)
#define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT)
#define TCR_EL2_SH0_SHIFT 12
#define TCR_EL2_SH0_MASK (0x3 << TCR_EL2_SH0_SHIFT)
#define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT)
#define TCR_EL2_TG0_SHIFT 14
#define TCR_EL2_TG0_MASK (0x3 << TCR_EL2_TG0_SHIFT)
#define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT)
#define TCR_EL2_PS_SHIFT 16
#define TCR_EL2_PS_32BITS (0 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_36BITS (1 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_40BITS (2 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_42BITS (3 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_44BITS (4 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_48BITS (5 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_52BITS (6 << TCR_EL2_PS_SHIFT) /* ARMv8.2-LPA */
#define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT)
/* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */
#define VMPIDR_EL2_U 0x0000000040000000
@ -170,31 +170,31 @@
#define VMPIDR_EL2_RES1 0x0000000080000000
/* VTCR_EL2 - Virtualization Translation Control Register */
#define VTCR_EL2_RES1 (0x1 << 31)
#define VTCR_EL2_RES1 (0x1UL << 31)
#define VTCR_EL2_T0SZ_MASK 0x3f
#define VTCR_EL2_SL0_SHIFT 6
#define VTCR_EL2_SL0_4K_LVL2 (0x0 << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_SL0_4K_LVL1 (0x1 << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_SL0_4K_LVL0 (0x2 << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_IRGN0_SHIFT 8
#define VTCR_EL2_IRGN0_WBWA (0x1 << VTCR_EL2_IRGN0_SHIFT)
#define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT)
#define VTCR_EL2_ORGN0_SHIFT 10
#define VTCR_EL2_ORGN0_WBWA (0x1 << VTCR_EL2_ORGN0_SHIFT)
#define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT)
#define VTCR_EL2_SH0_SHIFT 12
#define VTCR_EL2_SH0_NS (0x0 << VTCR_EL2_SH0_SHIFT)
#define VTCR_EL2_SH0_OS (0x2 << VTCR_EL2_SH0_SHIFT)
#define VTCR_EL2_SH0_IS (0x3 << VTCR_EL2_SH0_SHIFT)
#define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT)
#define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT)
#define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT)
#define VTCR_EL2_TG0_SHIFT 14
#define VTCR_EL2_TG0_4K (0x0 << VTCR_EL2_TG0_SHIFT)
#define VTCR_EL2_TG0_64K (0x1 << VTCR_EL2_TG0_SHIFT)
#define VTCR_EL2_TG0_16K (0x2 << VTCR_EL2_TG0_SHIFT)
#define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT)
#define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT)
#define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT)
#define VTCR_EL2_PS_SHIFT 16
#define VTCR_EL2_PS_32BIT (0x0 << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_36BIT (0x1 << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_40BIT (0x2 << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_42BIT (0x3 << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_44BIT (0x4 << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_48BIT (0x5 << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT)
#define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT)
/* VTTBR_EL2 - Virtualization Translation Table Base Register */
#define VTTBR_VMID_MASK 0xffff000000000000