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Add support for RockChip RK356X to DWC3 driver.

Browse Source 
For RK356x platform, we can set bit 26 of DWC3_GUCTL1 register
for usb 2.0 device.

Reviewed by:	manu
Differential Revision:	https://reviews.freebsd.org/D36211
This commit is contained in:
Søren Schmidt 2022-08-16 12:24:44 +00:00 committed by Ganbold Tsagaankhuu
parent 84a0be4a23
commit 1331c0f44b
3 changed files with 10 additions and 6 deletions
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6
sys/arm64/rockchip/rk_dwc3.c
View File

@ -141,11 +141,7 @@ rk_dwc3_attach(device_t dev)
clk_get_name(sc->clk_bus));
return (ENXIO);
}
if (sc->type == RK3399) {
if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) != 0) {
device_printf(dev, "Cannot get grf_clk clock\n");
return (ENXIO);
}
if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) == 0) {
err = clk_enable(sc->clk_grf);
if (err != 0) {
device_printf(dev, "Could not enable clock %s\n",

9
sys/dev/usb/controller/dwc3.c
View File

@ -366,6 +366,7 @@ snps_dwc3_common_attach(device_t dev, bool is_fdt)
#ifdef FDT
phandle_t node;
phy_t usb2_phy, usb3_phy;
uint32_t reg;
#endif
int error, rid;
@ -403,7 +404,13 @@ snps_dwc3_common_attach(device_t dev, bool is_fdt)
error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy);
if (error == 0 && usb3_phy != NULL)
phy_enable(usb3_phy);
else {
reg = DWC3_READ(sc, DWC3_GUCTL1);
if (bootverbose)
device_printf(dev, "Forcing USB2 clock only\n");
reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
DWC3_WRITE(sc, DWC3_GUCTL1, reg);
}
snps_dwc3_configure_phy(sc, node);
skip_phys:
#endif

1
sys/dev/usb/controller/dwc3.h
View File

@ -49,6 +49,7 @@
#define DWC3_GUCTL1 0xc11c
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28)
#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK (1 << 26)
#define DWC3_GSNPSID 0xc120
#define DWC3_GGPIO 0xc124