arm64: Print per-CPU cache summary
Summary: It can be useful to see a summary of CPU caches on bootup. This is done for most platforms already, so add this to arm64, in the form of (taken from Apple M1 pro test): L1 cache: 192KB (instruction), 128KB (data) L2 cache: 12288KB (unified) This is printed out per-CPU, only under bootverbose. Future refinements could instead determine if a cache level is shared with other cores (L2 is shared among cores on some SoCs, for instance), and perform a better calculation to the full true cache sizes. For instance, it's known that the M1 pro, on which this test was done, has 2 12MB L2 clusters, for a total of 24MB. Seeing each CPU with 12288KB L2 would make one think that there's 12MB * NCPUs, for possibly 120MB cache, which is incorrect. Sponsored by: Juniper Networks, Inc. Reviewed by: #arm64, andrew Differential Revision: https://reviews.freebsd.org/D35366
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Justin Hibbits
parent
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commit
139ba152c9
@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$");
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static void print_cpu_midr(struct sbuf *sb, u_int cpu);
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static void print_cpu_features(u_int cpu);
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static void print_cpu_caches(struct sbuf *sb, u_int);
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#ifdef COMPAT_FREEBSD32
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static u_long parse_cpu_features_hwcap32(void);
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#endif
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@ -103,6 +104,8 @@ static char cpu_model[64];
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SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
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cpu_model, sizeof(cpu_model), "Machine model");
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#define MAX_CACHES 8 /* Maximum number of caches supported
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architecturally. */
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/*
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* Per-CPU affinity as provided in MPIDR_EL1
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* Indexed by CPU number in logical order selected by the system.
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@ -135,6 +138,8 @@ struct cpu_desc {
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uint64_t mvfr0;
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uint64_t mvfr1;
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#endif
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uint64_t clidr;
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uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */
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};
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static struct cpu_desc cpu_desc[MAXCPU];
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@ -1805,6 +1810,7 @@ cpu_features_sysinit(void *dummy __unused)
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/* Fill in cpu_model for the hw.model sysctl */
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sbuf_new(&sb, cpu_model, sizeof(cpu_model), SBUF_FIXEDLEN);
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print_cpu_midr(&sb, 0);
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sbuf_finish(&sb);
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sbuf_delete(&sb);
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}
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@ -1978,6 +1984,62 @@ print_cpu_midr(struct sbuf *sb, u_int cpu)
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cpu_part_name, CPU_VAR(midr), CPU_REV(midr));
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}
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static void
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print_cpu_cache(u_int cpu, struct sbuf *sb, uint64_t ccs, bool icache,
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bool unified)
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{
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size_t cache_size;
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size_t line_size;
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/* LineSize is Log2(S) - 4. */
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line_size = 1 << ((ccs & CCSIDR_LineSize_MASK) + 4);
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/*
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* Calculate cache size (sets * ways * line size). There are different
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* formats depending on the FEAT_CCIDX bit in ID_AA64MMFR2 feature
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* register.
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*/
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if ((cpu_desc[cpu].id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64))
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cache_size = (CCSIDR_NSETS_64(ccs) + 1) *
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(CCSIDR_ASSOC_64(ccs) + 1);
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else
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cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1);
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cache_size *= line_size;
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sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024,
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icache ? "instruction" : unified ? "unified" : "data");
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}
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static void
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print_cpu_caches(struct sbuf *sb, u_int cpu)
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{
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/* Print out each cache combination */
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uint64_t clidr;
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int i = 1;
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clidr = cpu_desc[cpu].clidr;
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for (i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
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int j = 0;
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int ctype_m = (clidr & CLIDR_CTYPE_MASK);
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sbuf_printf(sb, " L%d cache: ", i + 1);
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if ((clidr & CLIDR_CTYPE_IO)) {
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print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j++],
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true, false);
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/* If there's more, add to the line. */
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if ((ctype_m & ~CLIDR_CTYPE_IO) != 0)
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sbuf_printf(sb, ", ");
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}
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if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) {
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print_cpu_cache(cpu, sb, cpu_desc[cpu].ccsidr[i][j],
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false, (clidr & CLIDR_CTYPE_UNIFIED));
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}
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sbuf_printf(sb, "\n");
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}
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sbuf_finish(sb);
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printf("%s", sbuf_data(sb));
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}
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static void
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print_cpu_features(u_int cpu)
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{
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@ -2107,6 +2169,8 @@ print_cpu_features(u_int cpu)
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print_id_register(sb, "AArch32 Media and VFP Features 1",
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cpu_desc[cpu].mvfr1, mvfr1_fields);
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#endif
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if (bootverbose)
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print_cpu_caches(sb, cpu);
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sbuf_delete(sb);
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sb = NULL;
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@ -2156,6 +2220,8 @@ identify_cache(uint64_t ctr)
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void
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identify_cpu(u_int cpu)
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{
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uint64_t clidr;
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/* Save affinity for current CPU */
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cpu_desc[cpu].mpidr = get_mpidr();
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CPU_AFFINITY(cpu) = cpu_desc[cpu].mpidr & CPU_AFF_MASK;
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@ -2170,6 +2236,25 @@ identify_cpu(u_int cpu)
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cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
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cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
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cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
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cpu_desc[cpu].clidr = READ_SPECIALREG(clidr_el1);
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clidr = cpu_desc[cpu].clidr;
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for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
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int j = 0;
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if ((clidr & CLIDR_CTYPE_IO)) {
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WRITE_SPECIALREG(csselr_el1,
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CSSELR_Level(i) | CSSELR_InD);
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cpu_desc[cpu].ccsidr[i][j++] =
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READ_SPECIALREG(ccsidr_el1);
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}
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if ((clidr & ~CLIDR_CTYPE_IO) == 0)
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continue;
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WRITE_SPECIALREG(csselr_el1, CSSELR_Level(i));
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cpu_desc[cpu].ccsidr[i][j] = READ_SPECIALREG(ccsidr_el1);
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}
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#ifdef COMPAT_FREEBSD32
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/* Only read aarch32 SRs if EL0-32 is available */
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if (ID_AA64PFR0_EL0_VAL(cpu_desc[cpu].id_aa64pfr0) ==
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@ -69,6 +69,32 @@
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#define UL(x) UINT64_C(x)
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/* CCSIDR_EL1 - Cache Size ID Register */
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#define CCSIDR_NumSets_MASK 0x0FFFE000
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#define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000
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#define CCSIDR_NumSets_SHIFT 13
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#define CCSIDR_NumSets64_SHIFT 32
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#define CCSIDR_Assoc_MASK 0x00001FF8
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#define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8
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#define CCSIDR_Assoc_SHIFT 3
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#define CCSIDR_Assoc64_SHIFT 3
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#define CCSIDR_LineSize_MASK 0x7
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#define CCSIDR_NSETS(idr) \
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(((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT)
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#define CCSIDR_ASSOC(idr) \
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(((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT)
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#define CCSIDR_NSETS_64(idr) \
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(((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT)
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#define CCSIDR_ASSOC_64(idr) \
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(((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT)
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/* CLIDR_EL1 - Cache level ID register */
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#define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */
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#define CLIDR_CTYPE_IO 0x1 /* Instruction only */
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#define CLIDR_CTYPE_DO 0x2 /* Data only */
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#define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */
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#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */
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/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
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#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
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#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
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@ -119,6 +145,10 @@
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#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
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#define CPACR_TTA (0x1 << 28)
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/* CSSELR_EL1 - Cache size selection register */
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#define CSSELR_Level(i) (i << 1)
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#define CSSELR_InD 0x00000001
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/* CTR_EL0 - Cache Type Register */
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#define CTR_RES1 (1 << 31)
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#define CTR_TminLine_SHIFT 32
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