Change reg in Marvell Armada38X pcie FDT
Ranges in pcie-controller are unused, so could be changed to match Linux device tree represntation. Same with interrupt-cells and interrupt-parent. In PCI controller driver ocd_data are used for matching driver and choose proper resources acquisition function. fdt_win_process_child have new argument which provide information about fdt node containing addresses of MMIO registers. Submitted by: Rafal Kozik <rk@semihalf.com> Reviewed by: manu [DT part] Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14751
This commit is contained in:
parent
d310c9e018
commit
13d464bf71
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=332017
@ -176,7 +176,7 @@ int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
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static int win_cpu_from_dt(void);
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static int fdt_win_setup(void);
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static int fdt_win_process_child(phandle_t, struct soc_node_spec *);
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static int fdt_win_process_child(phandle_t, struct soc_node_spec *, const char*);
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static uint32_t dev_mask = 0;
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static int cpu_wins_no = 0;
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@ -2757,7 +2757,7 @@ fdt_win_process(phandle_t child)
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if (!ofw_bus_node_is_compatible(child, soc_nodes[i].compat))
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continue;
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ret = fdt_win_process_child(child, &soc_nodes[i]);
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ret = fdt_win_process_child(child, &soc_nodes[i], "reg");
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if (ret != 0)
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return (ret);
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}
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@ -2766,7 +2766,8 @@ fdt_win_process(phandle_t child)
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}
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static int
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fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node)
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fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node,
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const char* mimo_reg_source)
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{
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int addr_cells, size_cells;
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pcell_t reg[8];
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@ -2778,8 +2779,7 @@ fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node)
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if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg))
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return (ENOMEM);
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if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0)
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if (OF_getprop(child, mimo_reg_source, ®, sizeof(reg)) <= 0)
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return (EINVAL);
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if (addr_cells <= 2)
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@ -2836,7 +2836,8 @@ fdt_win_setup(void)
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child_pci = OF_child(child);
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while (child_pci != 0) {
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err = fdt_win_process_child(child_pci,
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&soc_nodes[SOC_NODE_PCIE_ENTRY_IDX]);
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&soc_nodes[SOC_NODE_PCIE_ENTRY_IDX],
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"assigned-addresses");
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if (err != 0)
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return (err);
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@ -67,6 +67,9 @@ struct mv_pcib_ctrl_range {
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uint64_t size;
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};
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typedef int (*get_rl_t)(device_t dev, phandle_t node, pcell_t acells,
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pcell_t scells, struct resource_list *rl);
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struct mv_pcib_ctrl_softc {
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pcell_t addr_cells;
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pcell_t size_cells;
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@ -107,6 +110,13 @@ static device_method_t mv_pcib_ctrl_methods[] = {
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DEVMETHOD_END
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};
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static struct ofw_compat_data mv_pcib_ctrl_compat[] = {
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{"mrvl,pcie-ctrl", (uintptr_t)&ofw_bus_reg_to_rl},
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{"marvell,armada-370-pcie",
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(uintptr_t)&ofw_bus_assigned_addresses_to_rl},
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{NULL, (uintptr_t)NULL},
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};
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static driver_t mv_pcib_ctrl_driver = {
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"pcib_ctrl",
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mv_pcib_ctrl_methods,
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@ -124,8 +134,10 @@ static int
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mv_pcib_ctrl_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "mrvl,pcie-ctrl") &&
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!ofw_bus_is_compatible(dev, "marvell,armada-370-pcie"))
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, mv_pcib_ctrl_compat)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Marvell Integrated PCIe Bus Controller");
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@ -151,6 +163,7 @@ mv_pcib_ofw_bus_attach(device_t dev)
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struct mv_pcib_ctrl_softc *sc;
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device_t child;
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phandle_t parent, node;
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get_rl_t get_rl;
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parent = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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@ -189,7 +202,10 @@ mv_pcib_ofw_bus_attach(device_t dev)
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}
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resource_list_init(&di->di_rl);
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ofw_bus_reg_to_rl(child, node, sc->addr_cells,
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get_rl = (get_rl_t) ofw_bus_search_compatible(dev,
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mv_pcib_ctrl_compat)->ocd_data;
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if (get_rl != NULL)
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get_rl(child, node, sc->addr_cells,
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sc->size_cells, &di->di_rl);
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device_set_ivars(child, di);
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@ -88,23 +88,21 @@
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<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
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0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */
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0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */
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0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */
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0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */
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0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */
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0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */
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>;
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0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
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/* x1 port */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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reg = <0x0 0x0 0x80000 0x0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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bus-range = <0 255>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000
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0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>;
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interrupt-map-mask = <0 0 0 0>;
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@ -120,11 +118,10 @@
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0 0x0 0x40000 0x0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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bus-range = <0 255>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000
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0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>;
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interrupt-map-mask = <0 0 0 0>;
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@ -140,11 +137,10 @@
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
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reg = <0x0 0x0 0x44000 0x0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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bus-range = <0 255>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000
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0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>;
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interrupt-map-mask = <0 0 0 0>;
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@ -94,15 +94,14 @@
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0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
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0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */
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0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */
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0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */
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0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */
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0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */
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0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */
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0x82000000 0x0 0xf1800000 MBUS_ID(0x04, 0xb8) 0xf1800000 0 0x00100000 /* Port 3 MEM */
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0x81000000 0x0 0xf1900000 MBUS_ID(0x04, 0xb0) 0xf1900000 0 0x00100000 /* Port 3 IO */
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>;
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0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
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/*
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* This port can be either x4 or x1. When
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@ -112,16 +111,14 @@
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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reg = <0x0 0x0 0x80000 0x0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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bus-range = <0 255>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000
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0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 8>;
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@ -132,16 +129,14 @@
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0 0x0 0x40000 0x0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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bus-range = <0 255>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000
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0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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@ -152,16 +147,14 @@
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
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reg = <0x0 0x0 0x44000 0x0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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bus-range = <0 255>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000
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0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 6>;
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@ -175,16 +168,14 @@
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pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
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reg = <0x0 0x0 0x48000 0x0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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bus-range = <0 255>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1800000 0x0 0x00100000
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0x81000000 0x0 0x0 0x81000000 0x0 0xf1900000 0x0 0x00100000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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marvell,pcie-port = <3>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 7>;
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