Remove pd_prot and pd_cache members from struct arm_devmap_entry.
The struct is used for definition of static device mappings which should always have same protection and attributes.
This commit is contained in:
parent
d6686e08be
commit
1413a3ab64
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=295694
@ -71,8 +71,8 @@ generic_bs_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags,
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/*
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* We don't even examine the passed-in flags. For ARM, the CACHEABLE
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* flag doesn't make sense (we create PTE_DEVICE mappings), and the
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* LINEAR flag is just implied because we use kva_alloc(size).
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* flag doesn't make sense (we create VM_MEMATTR_DEVICE mappings), and
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* the LINEAR flag is just implied because we use kva_alloc(size).
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*/
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if ((va = pmap_mapdev(bpa, size)) == NULL)
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return (ENOMEM);
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@ -52,7 +52,6 @@ static boolean_t devmap_bootstrap_done = false;
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#if defined(__aarch64__)
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#define MAX_VADDR VM_MAX_KERNEL_ADDRESS
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#define PTE_DEVICE VM_MEMATTR_DEVICE
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#elif defined(__arm__)
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#define MAX_VADDR ARM_VECTORS_HIGH
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#endif
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@ -165,8 +164,6 @@ arm_devmap_add_entry(vm_paddr_t pa, vm_size_t sz)
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m->pd_va = akva_devmap_vaddr;
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m->pd_pa = pa;
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m->pd_size = sz;
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m->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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m->pd_cache = PTE_DEVICE;
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}
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/*
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@ -209,10 +206,10 @@ arm_devmap_bootstrap(vm_offset_t l1pt, const struct arm_devmap_entry *table)
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#if defined(__arm__)
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#if __ARM_ARCH >= 6
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pmap_preboot_map_attr(pd->pd_pa, pd->pd_va, pd->pd_size,
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pd->pd_prot, pd->pd_cache);
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VM_PROT_READ | VM_PROT_WRITE, VM_MEMATTR_DEVICE);
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#else
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pmap_map_chunk(l1pt, pd->pd_va, pd->pd_pa, pd->pd_size,
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pd->pd_prot, pd->pd_cache);
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VM_PROT_READ | VM_PROT_WRITE, PTE_DEVICE);
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#endif
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#elif defined(__aarch64__)
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pmap_kenter_device(pd->pd_va, pd->pd_size, pd->pd_pa);
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@ -270,7 +267,8 @@ arm_devmap_vtop(void * vpva, vm_size_t size)
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* range, otherwise it allocates kva space and maps the physical pages into it.
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*
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* This routine is intended to be used for mapping device memory, NOT real
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* memory; the mapping type is inherently PTE_DEVICE in pmap_kenter_device().
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* memory; the mapping type is inherently VM_MEMATTR_DEVICE in
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* pmap_kenter_device().
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*/
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void *
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pmap_mapdev(vm_offset_t pa, vm_size_t size)
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@ -128,8 +128,6 @@ const struct arm_devmap_entry at91_devmap[] = {
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0xdff00000,
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0xfff00000,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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/* There's a notion that we should do the rest of these lazily. */
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/*
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@ -152,16 +150,12 @@ const struct arm_devmap_entry at91_devmap[] = {
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AT91RM92_OHCI_VA_BASE,
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AT91RM92_OHCI_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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/* CompactFlash controller. Portion of EBI CS4 1MB */
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AT91RM92_CF_VA_BASE,
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AT91RM92_CF_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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/*
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* The next two should be good for the 9260, 9261 and 9G20 since
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@ -172,16 +166,12 @@ const struct arm_devmap_entry at91_devmap[] = {
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AT91SAM9G20_OHCI_VA_BASE,
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AT91SAM9G20_OHCI_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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/* EBI CS3 256MB */
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AT91SAM9G20_NAND_VA_BASE,
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AT91SAM9G20_NAND_BASE,
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AT91SAM9G20_NAND_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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/*
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* The next should be good for the 9G45.
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@ -191,10 +181,8 @@ const struct arm_devmap_entry at91_devmap[] = {
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AT91SAM9G45_OHCI_VA_BASE,
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AT91SAM9G45_OHCI_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ 0, 0, 0, 0, 0, }
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{ 0, 0, 0, }
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};
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#ifdef LINUX_BOOT_ABI
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@ -113,8 +113,6 @@ static const struct arm_devmap_entry econa_devmap[] = {
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ECONA_SDRAM_BASE, /*virtual*/
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ECONA_SDRAM_BASE, /*physical*/
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ECONA_SDRAM_SIZE, /*size*/
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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/*
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* Map the on-board devices VA == PA so that we can access them
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@ -128,8 +126,6 @@ static const struct arm_devmap_entry econa_devmap[] = {
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ECONA_IO_BASE, /*virtual*/
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ECONA_IO_BASE, /*physical*/
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ECONA_IO_SIZE, /*size*/
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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/*
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@ -138,8 +134,6 @@ static const struct arm_devmap_entry econa_devmap[] = {
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ECONA_OHCI_VBASE, /*virtual*/
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ECONA_OHCI_PBASE, /*physical*/
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ECONA_USB_SIZE, /*size*/
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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/*
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@ -148,15 +142,11 @@ static const struct arm_devmap_entry econa_devmap[] = {
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ECONA_CFI_VBASE, /*virtual*/
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ECONA_CFI_PBASE, /*physical*/
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ECONA_CFI_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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0,
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0,
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0,
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0,
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0,
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}
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};
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@ -136,7 +136,7 @@ imx6_late_init(platform_t plat)
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* Notably not mapped right now are HDMI, GPU, and other devices below ARMMP in
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* the memory map. When we get support for graphics it might make sense to
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* static map some of that area. Be careful with other things in that area such
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* as OCRAM that probably shouldn't be mapped as PTE_DEVICE memory.
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* as OCRAM that probably shouldn't be mapped as VM_MEMATTR_DEVICE memory.
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*/
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static int
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imx6_devmap_init(platform_t plat)
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@ -37,8 +37,6 @@ struct arm_devmap_entry {
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vm_offset_t pd_va; /* virtual address */
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vm_paddr_t pd_pa; /* physical address */
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vm_size_t pd_size; /* size of region */
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vm_prot_t pd_prot; /* protection code */
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int pd_cache; /* cache attributes */
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};
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/*
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@ -250,8 +250,6 @@ void pmap_preboot_map_attr(vm_paddr_t, vm_offset_t, vm_size_t, vm_prot_t,
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*/
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void vector_page_setprot(int);
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#define PTE_DEVICE VM_MEMATTR_DEVICE
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#endif /* _KERNEL */
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// -----------------------------------------------------------------------------
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@ -477,8 +477,6 @@ fdt_localbus_devmap(phandle_t dt_node, struct arm_devmap_entry *fdt_devmap,
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fdt_devmap[j].pd_va = localbus_virtmap[va_index].va;
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fdt_devmap[j].pd_pa = offset;
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fdt_devmap[j].pd_size = size;
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fdt_devmap[j].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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fdt_devmap[j].pd_cache = PTE_DEVICE;
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/* Copy data to structure used by localbus driver */
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localbus_banks[bank].va = fdt_devmap[j].pd_va;
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@ -271,7 +271,7 @@ platform_late_init(void)
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#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)
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static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
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{ 0, 0, 0, 0, 0, }
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{ 0, 0, 0, }
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};
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static int
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@ -302,8 +302,6 @@ platform_sram_devmap(struct arm_devmap_entry *map)
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map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
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map->pd_pa = base;
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map->pd_size = size;
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map->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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map->pd_cache = PTE_DEVICE;
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return (0);
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out:
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@ -368,8 +366,6 @@ platform_devmap_init(void)
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fdt_devmap[i].pd_va = fdt_immr_va;
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fdt_devmap[i].pd_pa = fdt_immr_pa;
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fdt_devmap[i].pd_size = fdt_immr_size;
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fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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fdt_devmap[i].pd_cache = PTE_DEVICE;
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i++;
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/*
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@ -233,15 +233,11 @@ mv_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, vm_offset_t io_va
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devmap->pd_va = (io_va ? io_va : io_space.base_parent);
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devmap->pd_pa = io_space.base_parent;
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devmap->pd_size = io_space.len;
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devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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devmap->pd_cache = PTE_DEVICE;
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devmap++;
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devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
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devmap->pd_pa = mem_space.base_parent;
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devmap->pd_size = mem_space.len;
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devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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devmap->pd_cache = PTE_DEVICE;
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return (0);
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}
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@ -82,45 +82,33 @@ const struct arm_devmap_entry db88f5xxx_devmap[] = {
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MV_BASE,
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MV_PHYS_BASE,
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MV_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCIE I/O */
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MV_PCIE_IO_BASE,
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MV_PCIE_IO_PHYS_BASE,
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MV_PCIE_IO_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCIE Memory */
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MV_PCIE_MEM_BASE,
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MV_PCIE_MEM_PHYS_BASE,
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MV_PCIE_MEM_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCI I/O */
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MV_PCI_IO_BASE,
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MV_PCI_IO_PHYS_BASE,
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MV_PCI_IO_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* PCI Memory */
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MV_PCI_MEM_BASE,
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MV_PCI_MEM_PHYS_BASE,
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MV_PCI_MEM_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ /* 7-seg LED */
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MV_DEV_CS0_BASE,
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MV_DEV_CS0_PHYS_BASE,
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MV_DEV_CS0_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{ 0, 0, 0, 0, 0, }
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{ 0, 0, 0, }
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};
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/*
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@ -82,8 +82,8 @@ platform_late_init(void)
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#define FDT_DEVMAP_MAX (2) /* FIXME */
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static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
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{ 0, 0, 0, 0, 0, },
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{ 0, 0, 0, 0, 0, }
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{ 0, 0, 0, },
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{ 0, 0, 0, }
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};
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@ -97,8 +97,6 @@ platform_devmap_init(void)
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fdt_devmap[i].pd_va = 0xf0100000;
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fdt_devmap[i].pd_pa = 0x10100000;
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fdt_devmap[i].pd_size = 0x01000000; /* 1 MB */
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fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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fdt_devmap[i].pd_cache = PTE_DEVICE;
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arm_devmap_register_table(&fdt_devmap[0]);
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return (0);
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@ -125,8 +125,6 @@ static const struct arm_devmap_entry iq81342_devmap[] = {
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IOP34X_VADDR,
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IOP34X_HWADDR,
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IOP34X_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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/*
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@ -136,22 +134,16 @@ static const struct arm_devmap_entry iq81342_devmap[] = {
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IOP34X_PCIX_OIOBAR_VADDR &~ (0x100000 - 1),
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IOP34X_PCIX_OIOBAR &~ (0x100000 - 1),
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0x100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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IOP34X_PCE1_VADDR,
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IOP34X_PCE1,
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IOP34X_PCE1_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_DEVICE,
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},
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{
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0,
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0,
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0,
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0,
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0,
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}
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};
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@ -119,32 +119,26 @@ struct pv_addr minidataclean;
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/* Static device mappings. */
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static const struct arm_devmap_entry ixp425_devmap[] = {
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/* Physical/Virtual address for I/O space */
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{ IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, },
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/* Expansion Bus */
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{ IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, },
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/* CFI Flash on the Expansion Bus */
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{ IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
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IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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IXP425_EXP_BUS_CS0_SIZE, },
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/* IXP425 PCI Configuration */
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{ IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, },
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/* SDRAM Controller */
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{ IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, },
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/* PCI Memory Space */
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{ IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, },
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/* Q-Mgr Memory Space */
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{ IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, },
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{ 0 },
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};
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@ -152,46 +146,36 @@ static const struct arm_devmap_entry ixp425_devmap[] = {
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/* Static device mappings. */
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static const struct arm_devmap_entry ixp435_devmap[] = {
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/* Physical/Virtual address for I/O space */
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{ IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, },
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{ IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, },
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/* IXP425 PCI Configuration */
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{ IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, },
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/* DDRII Controller NB: mapped same place as IXP425 */
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{ IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, },
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/* PCI Memory Space */
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{ IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, },
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/* Q-Mgr Memory Space */
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{ IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
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VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
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{ IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, },
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/* CFI Flash on the Expansion Bus */
|
||||
{ IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
|
||||
IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
|
||||
IXP425_EXP_BUS_CS0_SIZE, },
|
||||
|
||||
/* USB1 Memory Space */
|
||||
{ IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE,
|
||||
VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
|
||||
{ IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, },
|
||||
/* USB2 Memory Space */
|
||||
{ IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE,
|
||||
VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
|
||||
{ IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, },
|
||||
|
||||
/* GPS Memory Space */
|
||||
{ CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE,
|
||||
VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
|
||||
{ CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, },
|
||||
|
||||
/* RS485 Memory Space */
|
||||
{ CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE,
|
||||
VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
|
||||
{ CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, },
|
||||
|
||||
{ 0 }
|
||||
};
|
||||
|
@ -129,10 +129,8 @@ static const struct arm_devmap_entry pxa_devmap[] = {
|
||||
PXA2X0_PERIPH_START + PXA2X0_PERIPH_OFFSET,
|
||||
PXA2X0_PERIPH_START,
|
||||
PXA250_PERIPH_END - PXA2X0_PERIPH_START,
|
||||
VM_PROT_READ|VM_PROT_WRITE,
|
||||
PTE_DEVICE,
|
||||
},
|
||||
{ 0, 0, 0, 0, 0, }
|
||||
{ 0, 0, 0, }
|
||||
};
|
||||
|
||||
#define SDRAM_START 0xa0000000
|
||||
|
@ -37,8 +37,6 @@ struct arm_devmap_entry {
|
||||
vm_offset_t pd_va; /* virtual address */
|
||||
vm_paddr_t pd_pa; /* physical address */
|
||||
vm_size_t pd_size; /* size of region */
|
||||
vm_prot_t pd_prot; /* protection code */
|
||||
int pd_cache; /* cache attributes */
|
||||
};
|
||||
|
||||
/*
|
||||
@ -70,7 +68,7 @@ void arm_devmap_register_table(const struct arm_devmap_entry * _table);
|
||||
* custom initarm() routines in older code. If the table pointer is NULL, this
|
||||
* will use the table installed previously by arm_devmap_register_table().
|
||||
*/
|
||||
void arm_devmap_bootstrap(vm_offset_t _l1pt,
|
||||
void arm_devmap_bootstrap(vm_offset_t _l1pt,
|
||||
const struct arm_devmap_entry *_table);
|
||||
|
||||
/*
|
||||
|
Loading…
Reference in New Issue
Block a user