diff --git a/sys/dev/vr/if_vr.c b/sys/dev/vr/if_vr.c
index 1f4a07e5fb28..74a8d660f7bf 100644
--- a/sys/dev/vr/if_vr.c
+++ b/sys/dev/vr/if_vr.c
@@ -1407,6 +1407,15 @@ static void vr_init(xsc)
 	for (i = 0; i < ETHER_ADDR_LEN; i++)
 		CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
 
+	/* BCR0 and BCR1 can override the RXCFG and TXCFG registers,
+	 * so we must set both.
+	 */
+	VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
+	VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESHSTORENFWD);
+
+	VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
+	VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
+
 	VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
 	VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD);
 
diff --git a/sys/dev/vr/if_vrreg.h b/sys/dev/vr/if_vrreg.h
index c84f5c242804..73b074e8f182 100644
--- a/sys/dev/vr/if_vrreg.h
+++ b/sys/dev/vr/if_vrreg.h
@@ -277,6 +277,46 @@
 #define VR_STICKHW_WOL_STS	0x08
 #define VR_STICKHW_LEGWOL_ENB	0x80
 
+/*
+ * BCR0 register bits. (At least for the VT6102 chip.)
+ */
+#define VR_BCR0_DMA_LENGTH	0x07
+
+#define VR_BCR0_DMA_32BYTES	0x00
+#define VR_BCR0_DMA_64BYTES	0x01
+#define VR_BCR0_DMA_128BYTES	0x02
+#define VR_BCR0_DMA_256BYTES	0x03
+#define VR_BCR0_DMA_512BYTES	0x04
+#define VR_BCR0_DMA_1024BYTES	0x05
+#define VR_BCR0_DMA_STORENFWD	0x07
+
+#define VR_BCR0_RX_THRESH	0x38
+
+#define VR_BCR0_RXTHRESHCFG	0x00
+#define VR_BCR0_RXTHRESH64BYTES	0x08
+#define VR_BCR0_RXTHRESH128BYTES 0x10
+#define VR_BCR0_RXTHRESH256BYTES 0x18
+#define VR_BCR0_RXTHRESH512BYTES 0x20
+#define VR_BCR0_RXTHRESH1024BYTES 0x28
+#define VR_BCR0_RXTHRESHSTORENFWD 0x38
+#define VR_BCR0_EXTLED		0x40
+#define VR_BCR0_MED2		0x80
+
+/*
+ * BCR1 register bits. (At least for the VT6102 chip.)
+ */
+#define VR_BCR1_POT0		0x01
+#define VR_BCR1_POT1		0x02
+#define VR_BCR1_POT2		0x04
+#define VR_BCR1_TX_THRESH	0x38
+#define VR_BCR1_TXTHRESHCFG	0x00
+#define VR_BCR1_TXTHRESH64BYTES	0x08
+#define VR_BCR1_TXTHRESH128BYTES 0x10
+#define VR_BCR1_TXTHRESH256BYTES 0x18
+#define VR_BCR1_TXTHRESH512BYTES 0x20
+#define VR_BCR1_TXTHRESH1024BYTES 0x28
+#define VR_BCR1_TXTHRESHSTORENFWD 0x38
+
 /*
  * Rhine TX/RX list structure.
  */
diff --git a/sys/pci/if_vr.c b/sys/pci/if_vr.c
index 1f4a07e5fb28..74a8d660f7bf 100644
--- a/sys/pci/if_vr.c
+++ b/sys/pci/if_vr.c
@@ -1407,6 +1407,15 @@ static void vr_init(xsc)
 	for (i = 0; i < ETHER_ADDR_LEN; i++)
 		CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
 
+	/* BCR0 and BCR1 can override the RXCFG and TXCFG registers,
+	 * so we must set both.
+	 */
+	VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
+	VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESHSTORENFWD);
+
+	VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
+	VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
+
 	VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
 	VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD);
 
diff --git a/sys/pci/if_vrreg.h b/sys/pci/if_vrreg.h
index c84f5c242804..73b074e8f182 100644
--- a/sys/pci/if_vrreg.h
+++ b/sys/pci/if_vrreg.h
@@ -277,6 +277,46 @@
 #define VR_STICKHW_WOL_STS	0x08
 #define VR_STICKHW_LEGWOL_ENB	0x80
 
+/*
+ * BCR0 register bits. (At least for the VT6102 chip.)
+ */
+#define VR_BCR0_DMA_LENGTH	0x07
+
+#define VR_BCR0_DMA_32BYTES	0x00
+#define VR_BCR0_DMA_64BYTES	0x01
+#define VR_BCR0_DMA_128BYTES	0x02
+#define VR_BCR0_DMA_256BYTES	0x03
+#define VR_BCR0_DMA_512BYTES	0x04
+#define VR_BCR0_DMA_1024BYTES	0x05
+#define VR_BCR0_DMA_STORENFWD	0x07
+
+#define VR_BCR0_RX_THRESH	0x38
+
+#define VR_BCR0_RXTHRESHCFG	0x00
+#define VR_BCR0_RXTHRESH64BYTES	0x08
+#define VR_BCR0_RXTHRESH128BYTES 0x10
+#define VR_BCR0_RXTHRESH256BYTES 0x18
+#define VR_BCR0_RXTHRESH512BYTES 0x20
+#define VR_BCR0_RXTHRESH1024BYTES 0x28
+#define VR_BCR0_RXTHRESHSTORENFWD 0x38
+#define VR_BCR0_EXTLED		0x40
+#define VR_BCR0_MED2		0x80
+
+/*
+ * BCR1 register bits. (At least for the VT6102 chip.)
+ */
+#define VR_BCR1_POT0		0x01
+#define VR_BCR1_POT1		0x02
+#define VR_BCR1_POT2		0x04
+#define VR_BCR1_TX_THRESH	0x38
+#define VR_BCR1_TXTHRESHCFG	0x00
+#define VR_BCR1_TXTHRESH64BYTES	0x08
+#define VR_BCR1_TXTHRESH128BYTES 0x10
+#define VR_BCR1_TXTHRESH256BYTES 0x18
+#define VR_BCR1_TXTHRESH512BYTES 0x20
+#define VR_BCR1_TXTHRESH1024BYTES 0x28
+#define VR_BCR1_TXTHRESHSTORENFWD 0x38
+
 /*
  * Rhine TX/RX list structure.
  */