Rename disable_intr() to ia64_disable_intr() and rename enable_intr()

to ia64_enable_intr(). This reduces confusion with intr_disable() and
intr_restore().

Have configure_final() call ia64_finalize_intr() instead of enable_intr()
in preparation of adding support for binding interrupts to all CPUs.

sys/ia64/ia64/autoconf.c

@@ -39,15 +39,9 @@
 #include <sys/bus.h>
 #include <sys/cons.h>
 
-#include <machine/md_var.h>
 #include <machine/bootinfo.h>
-
-#include <cam/cam.h>
-#include <cam/cam_ccb.h>
-#include <cam/cam_sim.h>
-#include <cam/cam_periph.h>
-#include <cam/cam_xpt_sim.h>
-#include <cam/cam_debug.h>
+#include <machine/intr.h>
+#include <machine/md_var.h>
 
 static void	configure_first(void *);
 static void	configure(void *);
@@ -97,12 +91,9 @@ static void
 configure_final(void *dummy)
 {
 
-	/*
-	 * Now we're ready to handle (pending) interrupts.
-	 * XXX this is slightly misplaced.
-	 */
-	enable_intr();
-
 	cninit_finish();
+
+	ia64_finalize_intr();
+
 	cold = 0;
 }

sys/ia64/ia64/interrupt.c

@@ -280,6 +280,13 @@ ia64_teardown_intr(void *cookie)
 	return (intr_event_remove_handler(cookie));
 }
 
+void
+ia64_finalize_intr(void)
+{
+
+	ia64_enable_intr();
+}
+
 /*
  * Interrupt handlers.
  */
@@ -318,9 +325,9 @@ ia64_handle_intr(struct trapframe *tf)
  out:
 	if (TRAPF_USERMODE(tf)) {
 		while (td->td_flags & (TDF_ASTPENDING|TDF_NEEDRESCHED)) {
-			enable_intr();
+			ia64_enable_intr();
 			ast(tf);
-			disable_intr();
+			ia64_disable_intr();
 		}
 	}
 }

sys/ia64/ia64/mp_machdep.c

@@ -210,7 +210,7 @@ ia64_ap_startup(void)
 	ia64_set_itv(0x10000);
 	ia64_set_tpr(0);
 	ia64_srlz_d();
-	enable_intr();
+	ia64_enable_intr();
 
 	sched_throw(NULL);
 	/* NOTREACHED */

sys/ia64/ia64/trap.c

@@ -334,11 +334,11 @@ int
 do_ast(struct trapframe *tf)
 {
 
-	disable_intr();
+	ia64_disable_intr();
 	while (curthread->td_flags & (TDF_ASTPENDING|TDF_NEEDRESCHED)) {
-		enable_intr();
+		ia64_enable_intr();
 		ast(tf);
-		disable_intr();
+		ia64_disable_intr();
 	}
 	/*
 	 * Keep interrupts disabled. We return r10 as a favor to the EPC

sys/ia64/include/acpica_machdep.h

@@ -56,8 +56,8 @@
 
 #define	ACPI_ASM_MACROS
 #define	BREAKPOINT3
-#define	ACPI_DISABLE_IRQS() disable_intr()
-#define	ACPI_ENABLE_IRQS()  enable_intr()
+#define	ACPI_DISABLE_IRQS()	ia64_disable_intr()
+#define	ACPI_ENABLE_IRQS()	ia64_enable_intr()
 
 #define	ACPI_FLUSH_CPU_CACHE()	/* XXX ia64_fc()? */
 

sys/ia64/include/cpufunc.h

@@ -56,13 +56,13 @@ breakpoint(void)
 
 
 static __inline void
-disable_intr(void)
+ia64_disable_intr(void)
 {
 	__asm __volatile ("rsm psr.i");
 }
 
 static __inline void
-enable_intr(void)
+ia64_enable_intr(void)
 {
 	__asm __volatile ("ssm psr.i;; srlz.d");
 }
@@ -71,8 +71,9 @@ static __inline register_t
 intr_disable(void)
 {
 	register_t psr;
+
 	__asm __volatile ("mov %0=psr;;" : "=r"(psr));
-	disable_intr();
+	ia64_disable_intr();
 	return ((psr & IA64_PSR_I) ? 1 : 0);
 }
 
@@ -80,7 +81,7 @@ static __inline void
 intr_restore(register_t ie)
 {
 	if (ie)
-		enable_intr();
+		ia64_enable_intr();
 }
 
 #endif /* __GNUCLIKE_ASM */

sys/ia64/include/intr.h

@@ -65,6 +65,7 @@ typedef u_int (ia64_ihtype)(struct thread *, u_int, struct trapframe *);
 
 extern struct ia64_pib *ia64_pib;
 
+void	ia64_finalize_intr(void);
 void	ia64_handle_intr(struct trapframe *);
 int	ia64_setup_intr(const char *, int, driver_filter_t, driver_intr_t,
 	    void *, enum intr_type, void **);