Pull in r372186 from upstream llvm trunk (by Eli Friedman):
[ARM] VFPv2 only supports 16 D registers. r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 Pull in r372187 from upstream clang trunk (by Eli Friedman): [ARM] Update clang for removal of vfp2d16 and vfp2d16sp Matching fix for https://reviews.llvm.org/D67375 (r372186). Differential Revision: https://reviews.llvm.org/D67467 This should fix clang generating invalid opcodes for floating point operations on armv6. Requested by: mmel MFC after: 3 days
This commit is contained in:
parent
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=354097
@ -194,7 +194,7 @@ SubtargetFeatures ELFObjectFileBase::getARMFeatures() const {
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default:
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break;
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case ARMBuildAttrs::Not_Allowed:
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Features.AddFeature("vfp2d16sp", false);
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Features.AddFeature("vfp2sp", false);
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Features.AddFeature("vfp3d16sp", false);
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Features.AddFeature("vfp4d16sp", false);
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break;
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@ -176,10 +176,8 @@ bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
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// exist).
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{"+fpregs", "-fpregs", FPUVersion::VFPV2, FPURestriction::SP_D16},
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{"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::None},
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{"+vfp2d16", "-vfp2d16", FPUVersion::VFPV2, FPURestriction::D16},
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{"+vfp2d16sp", "-vfp2d16sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
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{"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::None},
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{"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
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{"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
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{"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
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{"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
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{"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
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@ -195,7 +193,7 @@ bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
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{"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
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{"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
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{"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
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{"+d32", "-d32", FPUVersion::VFPV2, FPURestriction::None},
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{"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
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};
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for (const auto &Info: FPUFeatureInfoList) {
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@ -57,12 +57,15 @@ def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true",
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"Extend FP to 32 double registers">;
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multiclass VFPver<string name, string query, string description,
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list<SubtargetFeature> prev = [],
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list<SubtargetFeature> otherimplies = []> {
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list<SubtargetFeature> prev,
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list<SubtargetFeature> otherimplies,
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list<SubtargetFeature> vfp2prev = []> {
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def _D16_SP: SubtargetFeature<
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name#"d16sp", query#"D16SP", "true",
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description#" with only 16 d-registers and no double precision",
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!foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # otherimplies>;
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!foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
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!foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
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otherimplies>;
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def _SP: SubtargetFeature<
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name#"sp", query#"SP", "true",
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description#" with no double precision",
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@ -72,6 +75,7 @@ multiclass VFPver<string name, string query, string description,
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name#"d16", query#"D16", "true",
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description#" with only 16 d-registers",
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!foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
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vfp2prev #
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otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
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def "": SubtargetFeature<
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name, query, "true", description,
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@ -80,11 +84,17 @@ multiclass VFPver<string name, string query, string description,
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!cast<SubtargetFeature>(NAME # "_SP")]>;
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}
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defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions",
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[], [FeatureFPRegs]>;
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def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
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"Enable VFP2 instructions with "
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"no double precision",
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[FeatureFPRegs]>;
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
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"Enable VFP2 instructions",
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[FeatureFP64, FeatureVFP2_SP]>;
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defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
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[FeatureVFP2]>;
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[], [], [FeatureVFP2]>;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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@ -98,7 +108,7 @@ defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
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[FeatureVFP3], [FeatureFP16]>;
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defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
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[FeatureVFP4]>;
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[FeatureVFP4], []>;
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Enable full half-precision "
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@ -71,7 +71,7 @@ def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,
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AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;
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def NoVFP : Predicate<"!Subtarget->hasVFP2Base()">;
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def HasVFP2 : Predicate<"Subtarget->hasVFP2Base()">,
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AssemblerPredicate<"FeatureVFP2_D16_SP", "VFP2">;
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AssemblerPredicate<"FeatureVFP2_SP", "VFP2">;
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def HasVFP3 : Predicate<"Subtarget->hasVFP3Base()">,
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AssemblerPredicate<"FeatureVFP3_D16_SP", "VFP3">;
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def HasVFP4 : Predicate<"Subtarget->hasVFP4Base()">,
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@ -179,11 +179,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
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bool HasVFPv3SP = false;
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bool HasVFPv4SP = false;
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bool HasFPARMv8SP = false;
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bool HasVFPv2D16 = false;
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bool HasVFPv3D16 = false;
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bool HasVFPv4D16 = false;
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bool HasFPARMv8D16 = false;
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bool HasVFPv2D16SP = false;
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bool HasVFPv3D16SP = false;
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bool HasVFPv4D16SP = false;
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bool HasFPARMv8D16SP = false;
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@ -600,7 +598,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
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bool hasARMOps() const { return !NoARM; }
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bool hasVFP2Base() const { return HasVFPv2D16SP; }
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bool hasVFP2Base() const { return HasVFPv2SP; }
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bool hasVFP3Base() const { return HasVFPv3D16SP; }
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bool hasVFP4Base() const { return HasVFPv4D16SP; }
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bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
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@ -11694,14 +11694,14 @@ bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
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{ ARM::AEK_CRYPTO, {Feature_HasV8Bit},
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{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
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{ ARM::AEK_FP, {Feature_HasV8Bit},
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{ARM::FeatureVFP2_D16_SP, ARM::FeatureFPARMv8} },
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{ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
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{ (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM),
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{Feature_HasV7Bit, Feature_IsNotMClassBit},
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{ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
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{ ARM::AEK_MP, {Feature_HasV7Bit, Feature_IsNotMClassBit},
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{ARM::FeatureMP} },
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{ ARM::AEK_SIMD, {Feature_HasV8Bit},
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{ARM::FeatureNEON, ARM::FeatureVFP2_D16_SP, ARM::FeatureFPARMv8} },
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{ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
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{ ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone} },
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// FIXME: Only available in A-class, isel not predicated
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{ ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization} },
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@ -249,12 +249,12 @@ void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
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: ARM::FK_VFPV3_D16)
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: (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
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: ARM::FK_VFPV3XD)));
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else if (STI.hasFeature(ARM::FeatureVFP2_D16_SP))
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else if (STI.hasFeature(ARM::FeatureVFP2_SP))
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emitFPU(ARM::FK_VFPV2);
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}
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// ABI_HardFP_use attribute to indicate single precision FP.
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if (STI.hasFeature(ARM::FeatureVFP2_D16_SP) && !STI.hasFeature(ARM::FeatureFP64))
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if (STI.hasFeature(ARM::FeatureVFP2_SP) && !STI.hasFeature(ARM::FeatureFP64))
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emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
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ARMBuildAttrs::HardFPSinglePrecision);
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@ -427,11 +427,10 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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for (const auto &Feature : Features) {
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if (Feature == "+soft-float") {
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SoftFloat = true;
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} else if (Feature == "+vfp2sp" || Feature == "+vfp2d16sp" ||
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Feature == "+vfp2" || Feature == "+vfp2d16") {
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} else if (Feature == "+vfp2sp" || Feature == "+vfp2") {
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FPU |= VFP2FPU;
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HW_FP |= HW_FP_SP;
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if (Feature == "+vfp2" || Feature == "+vfp2d16")
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if (Feature == "+vfp2")
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HW_FP |= HW_FP_DP;
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} else if (Feature == "+vfp3sp" || Feature == "+vfp3d16sp" ||
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Feature == "+vfp3" || Feature == "+vfp3d16") {
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@ -460,7 +460,7 @@ void arm::getARMTargetFeatures(const ToolChain &TC,
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// now just be explicit and disable all known dependent features
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// as well.
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for (std::string Feature : {
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"vfp2", "vfp2sp", "vfp2d16", "vfp2d16sp",
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"vfp2", "vfp2sp",
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"vfp3", "vfp3sp", "vfp3d16", "vfp3d16sp",
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"vfp4", "vfp4sp", "vfp4d16", "vfp4d16sp",
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"fp-armv8", "fp-armv8sp", "fp-armv8d16", "fp-armv8d16sp",
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