From 1a0329799c6d8bfb7eca89d0c8736736b8ab446c Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 18 May 2022 11:02:03 +0200 Subject: [PATCH] Apply llvm fix for "Invalid PPC CTR loop!" error on powerpcspe Merge commit d9d15af7873f from llvm git (Qiu Chaofan): [PowerPC] Treat llvm.fmuladd intrinsic as using CTR This fixes bug 55463, similar to D78668. This is a temporary fix since we will switch to post-isel CTR loop determination in the future. Reviewed By: dim, shchenz Differential Revision: https://reviews.llvm.org/D125746 MFC after: 2 weeks --- ...15af7873fe16d7a0dde4def30f40fa9901777.diff | 34 +++++++++++++++++++ .../Target/PowerPC/PPCTargetTransformInfo.cpp | 4 +-- 2 files changed, 35 insertions(+), 3 deletions(-) create mode 100644 commit-d9d15af7873fe16d7a0dde4def30f40fa9901777.diff diff --git a/commit-d9d15af7873fe16d7a0dde4def30f40fa9901777.diff b/commit-d9d15af7873fe16d7a0dde4def30f40fa9901777.diff new file mode 100644 index 000000000000..901213b03e93 --- /dev/null +++ b/commit-d9d15af7873fe16d7a0dde4def30f40fa9901777.diff @@ -0,0 +1,34 @@ +commit d9d15af7873fe16d7a0dde4def30f40fa9901777 +Author: Qiu Chaofan +Date: Wed May 18 15:55:02 2022 +0800 + + [PowerPC] Treat llvm.fmuladd intrinsic as using CTR + + This fixes bug 55463, similar to D78668. This is a temporary fix since + we will switch to post-isel CTR loop determination in the future. + + Reviewed By: dim, shchenz + + Differential Revision: https://reviews.llvm.org/D125746 + +diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +index 501cfa07efeb..7b956fd3478e 100644 +--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp ++++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +@@ -491,15 +491,13 @@ bool PPCTTIImpl::mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, + case Intrinsic::experimental_constrained_sin: + case Intrinsic::experimental_constrained_cos: + return true; +- // There is no corresponding FMA instruction for PPC double double. +- // Thus, we need to disable CTR loop generation for this type. +- case Intrinsic::fmuladd: + case Intrinsic::copysign: + if (CI->getArgOperand(0)->getType()->getScalarType()-> + isPPC_FP128Ty()) + return true; + else + continue; // ISD::FCOPYSIGN is never a library call. ++ case Intrinsic::fmuladd: + case Intrinsic::fma: Opcode = ISD::FMA; break; + case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; + case Intrinsic::floor: Opcode = ISD::FFLOOR; break; diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index cc5738a5d7b6..48be7e0860df 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -491,15 +491,13 @@ bool PPCTTIImpl::mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, case Intrinsic::experimental_constrained_sin: case Intrinsic::experimental_constrained_cos: return true; - // There is no corresponding FMA instruction for PPC double double. - // Thus, we need to disable CTR loop generation for this type. - case Intrinsic::fmuladd: case Intrinsic::copysign: if (CI->getArgOperand(0)->getType()->getScalarType()-> isPPC_FP128Ty()) return true; else continue; // ISD::FCOPYSIGN is never a library call. + case Intrinsic::fmuladd: case Intrinsic::fma: Opcode = ISD::FMA; break; case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; case Intrinsic::floor: Opcode = ISD::FFLOOR; break;