gnu binutils: FSGSBASE assembly/disassembly
Enable the in-tree binutils to assemble and disassemble amd64 FSGSBASE instructions (rdfsbase, rdgsbase, wrfsbase, wrgsbase), used in the base system since r322763. This gives one last gasp for in-tree gcc, and provides a small enhancement for in-tree binutils objdump. Reviewed by: dim, kib Approved by: markj (mentor) Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12222
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1a11bb8f76
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=323192
@ -1302,7 +1302,7 @@ static const unsigned char twobyte_uses_REPZ_prefix[256] = {
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/* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1, /* 7f */
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/* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
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/* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
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/* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
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/* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0, /* af */
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/* b0 */ 0,0,0,0,0,0,0,0,1,0,0,0,0,1,0,0, /* bf */
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/* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
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/* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
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@ -1793,10 +1793,10 @@ static const struct dis386 grps[][8] = {
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},
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/* GRP15 */
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{
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{ "fxsave", { Ev } },
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{ "fxrstor", { Ev } },
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{ "ldmxcsr", { Ev } },
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{ "stmxcsr", { Ev } },
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{ "fxsave", { { OP_0fae, v_mode } } },
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{ "fxrstor", { { OP_0fae, v_mode } } },
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{ "ldmxcsr", { { OP_0fae, v_mode } } },
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{ "stmxcsr", { { OP_0fae, v_mode } } },
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{ "xsave", { Ev } },
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{ "xrstor", { { OP_0fae, v_mode } } },
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{ "xsaveopt", { { OP_0fae, v_mode } } },
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@ -5997,19 +5997,34 @@ OP_0fae (int bytemode, int sizeflag)
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{
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if (modrm.mod == 3)
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{
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if (modrm.reg == 7)
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strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence");
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else if (modrm.reg == 6)
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strcpy (obuf + strlen (obuf) - sizeof ("xsaveopt") + 1, "mfence");
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else if (modrm.reg == 5)
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strcpy (obuf + strlen (obuf) - sizeof ("xrstor") + 1, "lfence");
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if (modrm.reg < 5 || modrm.rm != 0)
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if (modrm.reg >= 5 && modrm.reg <= 7 && modrm.rm == 0)
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{
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BadOp (); /* bad sfence, mfence, or lfence */
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if (modrm.reg == 7)
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strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence");
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else if (modrm.reg == 6)
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strcpy (obuf + strlen (obuf) - sizeof ("xsaveopt") + 1, "mfence");
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else if (modrm.reg == 5)
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strcpy (obuf + strlen (obuf) - sizeof ("xrstor") + 1, "lfence");
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bytemode = 0;
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}
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else if (modrm.reg <= 3 && (prefixes & PREFIX_REPZ) != 0)
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{
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if (modrm.reg == 0)
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strcpy (obuf + strlen (obuf) - sizeof ("fxsave") + 1, "rdfsbase");
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else if (modrm.reg == 1)
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strcpy (obuf + strlen (obuf) - sizeof ("fxrstor") + 1, "rdgsbase");
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else if (modrm.reg == 2)
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strcpy (obuf + strlen (obuf) - sizeof ("ldmxcsr") + 1, "wrfsbase");
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else if (modrm.reg == 3)
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strcpy (obuf + strlen (obuf) - sizeof ("stmxcsr") + 1, "wrgsbase");
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used_prefixes |= PREFIX_REPZ;
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bytemode = dq_mode;
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}
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else
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{
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BadOp ();
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return;
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}
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bytemode = 0;
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}
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OP_E (bytemode, sizeflag);
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@ -81,6 +81,7 @@ typedef struct template
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#define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */
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#define CpuRdRnd 0x20000000 /* Intel Random Number Generator extensions */
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#define CpuSMAP 0x40000000 /* Intel Supervisor Mode Access Prevention */
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#define CpuFSGSBase 0x80000000 /* Read/write fs/gs segment base registers */
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/* SSE4.1/4.2 Instructions required */
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#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
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@ -89,7 +90,8 @@ typedef struct template
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
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|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd|CpuSMAP)
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|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd|CpuSMAP \
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|CpuFSGSBase)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -1525,3 +1525,13 @@ pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|N
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// Intel Random Number Generator extensions
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rdrand, 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
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rdseed, 1, 0x0fc7, 0x7, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
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// Intel Supervisor Mode Access Prevention extensions
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clac, 0, 0x0f01, 0xca, CpuSMAP, NoSuf|ImmExt, { 0 }
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stac, 0, 0x0f01, 0xcb, CpuSMAP, NoSuf|ImmExt, { 0 }
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// Read/write fs/gs segment base registers
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rdfsbase, 1, 0xf30fae, 0x0, CpuFSGSBase|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64 }
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rdgsbase, 1, 0xf30fae, 0x1, CpuFSGSBase|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64 }
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wrfsbase, 1, 0xf30fae, 0x2, CpuFSGSBase|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64 }
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wrgsbase, 1, 0xf30fae, 0x3, CpuFSGSBase|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64 }
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@ -4400,6 +4400,20 @@ const template i386_optab[] =
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NoSuf|ImmExt, { 0, 0, 0 } },
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{"stac", 0, 0x0f01, 0xcb, CpuSMAP,
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NoSuf|ImmExt, { 0, 0, 0 } },
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/* Read/write fs/gs segment base registers */
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{"rdfsbase", 1, 0xf30fae, 0x0, CpuFSGSBase|Cpu64,
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Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
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{ Reg32|Reg64 } },
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{"rdgsbase", 1, 0xf30fae, 0x1, CpuFSGSBase|Cpu64,
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Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
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{ Reg32|Reg64 } },
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{"wrfsbase", 1, 0xf30fae, 0x2, CpuFSGSBase|Cpu64,
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Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
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{ Reg32|Reg64 } },
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{"wrgsbase", 1, 0xf30fae, 0x3, CpuFSGSBase|Cpu64,
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Modrm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
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{ Reg32|Reg64 } },
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{ NULL, 0, 0, 0, 0, 0, { 0 } }
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};
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