hwpmc: Bump Intel's IA32_PERFEVTSELx width to 64 bits.
Haswell added there bits 32/33 for TSX, and AlderLake added bit 34 for Adaptive PEBS Record. MFC after: 1 month
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@ -226,7 +226,8 @@ iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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uint8_t ev, umask;
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uint32_t caps, flags, config;
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uint32_t caps;
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uint64_t config, flags;
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const struct pmc_md_iap_op_pmcallocate *iap;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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@ -907,7 +908,7 @@ static int
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iap_start_pmc(int cpu, int ri)
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{
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struct pmc *pm;
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uint32_t evsel;
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uint64_t evsel;
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struct core_cpu *cc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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@ -48,7 +48,7 @@
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* Programmable PMCs.
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*/
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struct pmc_md_iap_op_pmcallocate {
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uint32_t pm_iap_config;
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uint64_t pm_iap_config;
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uint64_t pm_iap_rsp;
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};
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@ -75,9 +75,8 @@ struct pmc_md_iap_op_pmcallocate {
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* Fixed-function counters.
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*/
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#define IAF_MASK 0xF
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#define IAF_MASK 0x000000010000000f
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#define IAF_COUNTER_MASK 0x0000ffffffffffff
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#define IAF_CTR0 0x309
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#define IAF_CTR1 0x30A
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#define IAF_CTR2 0x30B
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@ -86,7 +85,17 @@ struct pmc_md_iap_op_pmcallocate {
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* The IAF_CTRL MSR is laid out in the following way.
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*
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* Bit Position Use
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* 63 - 12 Reserved (do not touch)
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* 63 - 45 Reserved (do not touch)
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* 44 Ctr 3 Adaptive Record (v5)
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* 43 - 41 Reserved (do not touch)
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* 40 Ctr 2 Adaptive Record (v5)
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* 39 - 37 Reserved (do not touch)
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* 36 Ctr 1 Adaptive Record (v5)
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* 35 - 33 Reserved (do not touch)
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* 32 Ctr 0 Adaptive Record (v5)
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* 15 Ctr 3 PMI
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* 14 Ctr 3 Any Thread (v3)
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* 13-12 Ctr 3 Enable
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* 11 Ctr 2 PMI
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* 10 Ctr 2 Any Thread (v3)
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* 9-8 Ctr 2 Enable
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@ -100,7 +109,6 @@ struct pmc_md_iap_op_pmcallocate {
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#define IAF_OFFSET 32
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#define IAF_CTRL 0x38D
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#define IAF_CTRL_MASK 0x0000000000000fff
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/*
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* Programmable counters.
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@ -113,7 +121,10 @@ struct pmc_md_iap_op_pmcallocate {
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* IAP_EVSEL(n) is laid out in the following way.
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*
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* Bit Position Use
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* 63-31 Reserved (do not touch)
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* 63-35 Reserved (do not touch)
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* 34 Adaptive Record (v5)
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* 33 IN_TX (v3)
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* 32 IN_TXCP (v3)
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* 31-24 Counter Mask
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* 23 Invert
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* 22 Enable
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@ -127,7 +138,6 @@ struct pmc_md_iap_op_pmcallocate {
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* 7-0 Event Select
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*/
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#define IAP_EVSEL_MASK 0x00000000ffffffff
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#define IAP_EVSEL0 0x186
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/*
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@ -142,22 +152,16 @@ struct pmc_md_iap_op_pmcallocate {
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* IA_GLOBAL_CTRL is laid out in the following way.
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*
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* Bit Position Use
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* 63-35 Reserved (do not touch)
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* 63-49 Reserved (do not touch)
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* 48 Perf Metrics Enable (v5)
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* 47-36 Reserved (do not touch)
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* 35 IAF Counter 3 Enable
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* 34 IAF Counter 2 Enable
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* 33 IAF Counter 1 Enable
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* 32 IAF Counter 0 Enable
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* 31-0 Depends on programmable counters
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*/
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/* The mask is only for the fixed porttion of the register. */
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#define IAF_GLOBAL_CTRL_MASK 0x0000000700000000
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/* The mask is only for the programmable porttion of the register. */
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#define IAP_GLOBAL_CTRL_MASK 0x00000000ffffffff
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/* The mask is for both the fixed and programmable porttions of the register. */
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#define IA_GLOBAL_CTRL_MASK 0x00000007ffffffff
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#define IA_GLOBAL_OVF_CTRL 0x390
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#define IA_GLOBAL_STATUS_RESET 0x390
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#define IA_GLOBAL_STATUS_SET 0x391 /* v4 */
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@ -183,7 +187,7 @@ struct pmc_md_iaf_pmc {
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};
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struct pmc_md_iap_pmc {
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uint32_t pm_iap_evsel;
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uint64_t pm_iap_evsel;
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uint64_t pm_iap_rsp;
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};
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@ -649,7 +649,7 @@ static int
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ucp_start_pmc(int cpu, int ri)
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{
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struct pmc *pm;
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uint32_t evsel;
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uint64_t evsel;
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struct uncore_cpu *cc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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@ -45,7 +45,7 @@ struct pmc_md_ucf_op_pmcallocate {
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* Programmable PMCs.
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*/
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struct pmc_md_ucp_op_pmcallocate {
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uint32_t pm_ucp_config;
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uint64_t pm_ucp_config;
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};
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#define UCP_EVSEL(C) ((C) & 0xFF)
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@ -106,7 +106,7 @@ struct pmc_md_ucf_pmc {
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};
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struct pmc_md_ucp_pmc {
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uint32_t pm_ucp_evsel;
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uint64_t pm_ucp_evsel;
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};
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/*
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