Driver for OpenCores I2C controller.
Add a Simple polled driver iicoc for the OpenCores I2C controller. This is used in Netlogic XLP processors. Submitted by: Sreekanth M. S. (kanthms at netlogicmicro com)
This commit is contained in:
Jayachandran C.
parent
c3c6df2c11
commit
1ab68cbb08
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=233539
@ -2530,6 +2530,7 @@ device smb
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# ic i2c network interface
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# iic i2c standard io
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# iicsmb i2c to smb bridge. Allow i2c i/o with smb commands.
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# iicoc simple polling driver for OpenCores I2C controller
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#
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# Supported interfaces:
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# bktr brooktree848 I2C software interface
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@ -2543,6 +2544,7 @@ device iicbb
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device ic
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device iic
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device iicsmb # smb over i2c bridge
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device iicoc # OpenCores I2C controller support
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# I2C peripheral devices
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#
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@ -1161,6 +1161,7 @@ dev/iicbus/iicbus_if.m optional iicbus
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dev/iicbus/iiconf.c optional iicbus
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dev/iicbus/iicsmb.c optional iicsmb \
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dependency "iicbus_if.h"
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dev/iicbus/iicoc.c optional iicoc
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dev/iir/iir.c optional iir
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dev/iir/iir_ctrl.c optional iir
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dev/iir/iir_pci.c optional iir pci
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390
sys/dev/iicbus/iicoc.c
Normal file
390
sys/dev/iicbus/iicoc.c
Normal file
@ -0,0 +1,390 @@
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/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/iicbus/iicoc.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "iicbus_if.h"
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static devclass_t iicoc_devclass;
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/*
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* Device methods
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*/
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static int iicoc_probe(device_t);
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static int iicoc_attach(device_t);
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static int iicoc_detach(device_t);
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static int iicoc_start(device_t dev, u_char slave, int timeout);
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static int iicoc_stop(device_t dev);
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static int iicoc_read(device_t dev, char *buf,
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int len, int *read, int last, int delay);
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static int iicoc_write(device_t dev, const char *buf,
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int len, int *sent, int timeout);
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static int iicoc_repeated_start(device_t dev, u_char slave, int timeout);
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struct iicoc_softc {
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device_t dev; /* Self */
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u_int reg_shift; /* Chip specific */
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u_int clockfreq;
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u_int i2cfreq;
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struct resource *mem_res; /* Memory resource */
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int mem_rid;
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int sc_started;
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uint8_t i2cdev_addr;
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device_t iicbus;
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struct mtx sc_mtx;
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};
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static void
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iicoc_dev_write(device_t dev, int reg, int value)
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{
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struct iicoc_softc *sc;
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sc = device_get_softc(dev);
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bus_write_1(sc->mem_res, reg<<sc->reg_shift, value);
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}
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static int
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iicoc_dev_read(device_t dev, int reg)
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{
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uint8_t val;
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struct iicoc_softc *sc;
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sc = device_get_softc(dev);
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val = bus_read_1(sc->mem_res, reg<<sc->reg_shift);
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return (val);
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}
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static int
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iicoc_wait_on_status(device_t dev, uint8_t bit)
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{
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int tries = I2C_TIMEOUT;
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uint8_t status;
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do {
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status = iicoc_dev_read(dev, OC_I2C_STATUS_REG);
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} while ((status & bit) != 0 && --tries > 0);
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return (tries == 0 ? -1: 0);
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}
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static int
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iicoc_rd_cmd(device_t dev, uint8_t cmd)
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{
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uint8_t data;
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iicoc_dev_write(dev, OC_I2C_CMD_REG, cmd);
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if (iicoc_wait_on_status(dev, OC_STATUS_TIP) < 0) {
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device_printf(dev, "read: Timeout waiting for TIP clear.\n");
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return (-1);
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}
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data = iicoc_dev_read(dev, OC_I2C_DATA_REG);
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return (data);
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}
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static int
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iicoc_wr_cmd(device_t dev, uint8_t data, uint8_t cmd)
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{
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iicoc_dev_write(dev, OC_I2C_DATA_REG, data);
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iicoc_dev_write(dev, OC_I2C_CMD_REG, cmd);
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if (iicoc_wait_on_status(dev, OC_STATUS_TIP) < 0) {
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device_printf(dev, "write: Timeout waiting for TIP clear.\n");
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return (-1);
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}
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return (0);
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}
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static int
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iicoc_wr_ack_cmd(device_t dev, uint8_t data, uint8_t cmd)
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{
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if (iicoc_wr_cmd(dev, data, cmd) < 0)
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return (-1);
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if (iicoc_dev_read(dev, OC_I2C_STATUS_REG) & OC_STATUS_NACK) {
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device_printf(dev, "write: I2C command ACK Error.\n");
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return (IIC_ENOACK);
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}
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return (0);
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}
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static int
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iicoc_init(device_t dev)
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{
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struct iicoc_softc *sc;
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int value;
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sc = device_get_softc(dev);
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value = iicoc_dev_read(dev, OC_I2C_CTRL_REG);
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iicoc_dev_write(dev, OC_I2C_CTRL_REG,
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value & ~(OC_CONTROL_EN | OC_CONTROL_IEN));
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value = (sc->clockfreq/(5 * sc->i2cfreq)) - 1;
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iicoc_dev_write(dev, OC_I2C_PRESCALE_LO_REG, value & 0xff);
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iicoc_dev_write(dev, OC_I2C_PRESCALE_HI_REG, value >> 8);
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value = iicoc_dev_read(dev, OC_I2C_CTRL_REG);
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iicoc_dev_write(dev, OC_I2C_CTRL_REG, value | OC_CONTROL_EN);
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value = iicoc_dev_read(dev, OC_I2C_CTRL_REG);
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/* return 0 on success, 1 on error */
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return ((value & OC_CONTROL_EN) == 0);
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}
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static int
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iicoc_probe(device_t dev)
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{
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struct iicoc_softc *sc;
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sc = device_get_softc(dev);
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if ((pci_get_vendor(dev) == 0x184e) &&
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(pci_get_device(dev) == 0x1011)) {
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sc->clockfreq = XLP_I2C_CLKFREQ;
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sc->i2cfreq = XLP_I2C_FREQ;
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sc->reg_shift = 2;
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device_set_desc(dev, "Netlogic XLP I2C Controller");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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/*
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* We add all the devices which we know about.
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* The generic attach routine will attach them if they are alive.
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*/
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static int
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iicoc_attach(device_t dev)
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{
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int bus;
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struct iicoc_softc *sc;
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sc = device_get_softc(dev);
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bus = device_get_unit(dev);
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sc->dev = dev;
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mtx_init(&sc->sc_mtx, "iicoc", "iicoc", MTX_DEF);
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sc->mem_rid = 0;
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sc->mem_res = bus_alloc_resource(dev,
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SYS_RES_MEMORY, &sc->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Could not allocate bus resource.\n");
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return (-1);
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}
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iicoc_init(dev);
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sc->iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->iicbus == NULL) {
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device_printf(dev, "Could not allocate iicbus instance.\n");
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return (-1);
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}
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bus_generic_attach(dev);
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return (0);
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}
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static int
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iicoc_detach(device_t dev)
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{
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bus_generic_detach(dev);
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return (0);
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}
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static int
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iicoc_start(device_t dev, u_char slave, int timeout)
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{
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int error = IIC_EBUSBSY;
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struct iicoc_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->sc_mtx);
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sc->i2cdev_addr = (slave >> 1);
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/* Verify the bus is idle */
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if (iicoc_wait_on_status(dev, OC_STATUS_BUSY) < 0)
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goto i2c_stx_error;
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/* Write Slave Address */
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if (iicoc_wr_ack_cmd(dev, slave, OC_COMMAND_START)) {
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device_printf(dev,
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"I2C write slave address [0x%x] failed.\n", slave);
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error = IIC_ENOACK;
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goto i2c_stx_error;
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}
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/* Verify Arbitration is not Lost */
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if (iicoc_dev_read(dev, OC_I2C_STATUS_REG) & OC_STATUS_AL) {
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device_printf(dev, "I2C Bus Arbitration Lost, Aborting.\n");
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error = IIC_EBUSERR;
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goto i2c_stx_error;
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}
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error = IIC_NOERR;
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mtx_unlock(&sc->sc_mtx);
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return (error);
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i2c_stx_error:
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iicoc_dev_write(dev, OC_I2C_CMD_REG, OC_COMMAND_STOP);
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iicoc_wait_on_status(dev, OC_STATUS_BUSY); /* wait for idle */
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mtx_unlock(&sc->sc_mtx);
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return (error);
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}
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static int
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iicoc_stop(device_t dev)
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{
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int error = 0;
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struct iicoc_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->sc_mtx);
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iicoc_dev_write(dev, OC_I2C_CMD_REG, OC_COMMAND_STOP);
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iicoc_wait_on_status(dev, OC_STATUS_BUSY); /* wait for idle */
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mtx_unlock(&sc->sc_mtx);
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return (error);
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}
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static int
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iicoc_write(device_t dev, const char *buf, int len,
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int *sent, int timeout /* us */ )
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{
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uint8_t value;
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int i;
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value = buf[0];
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/* Write Slave Offset */
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if (iicoc_wr_ack_cmd(dev, value, OC_COMMAND_WRITE)) {
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device_printf(dev, "I2C write slave offset failed.\n");
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goto i2c_tx_error;
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}
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for (i = 1; i < len; i++) {
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/* Write data byte */
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value = buf[i];
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if (iicoc_wr_cmd(dev, value, OC_COMMAND_WRITE)) {
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device_printf(dev, "I2C write data byte %d failed.\n",
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i);
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goto i2c_tx_error;
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}
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}
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*sent = len;
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return (IIC_NOERR);
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i2c_tx_error:
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return (IIC_EBUSERR);
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}
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static int
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iicoc_read(device_t dev, char *buf, int len, int *read, int last,
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int delay)
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{
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int data, i;
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uint8_t cmd;
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for (i = 0; i < len; i++) {
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/* Read data byte */
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cmd = (i == len - 1) ? OC_COMMAND_RDNACK : OC_COMMAND_READ;
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data = iicoc_rd_cmd(dev, cmd);
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if (data < 0) {
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device_printf(dev,
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"I2C read data byte %d failed.\n", i);
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goto i2c_rx_error;
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}
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buf[i] = (uint8_t)data;
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}
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*read = len;
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return (IIC_NOERR);
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i2c_rx_error:
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return (IIC_EBUSERR);
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}
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static int
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iicoc_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
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{
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int error;
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struct iicoc_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->sc_mtx);
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error = iicoc_init(dev);
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mtx_unlock(&sc->sc_mtx);
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return (error);
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}
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static int
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iicoc_repeated_start(device_t dev, u_char slave, int timeout)
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{
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return 0;
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}
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static device_method_t iicoc_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, iicoc_probe),
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DEVMETHOD(device_attach, iicoc_attach),
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DEVMETHOD(device_detach, iicoc_detach),
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/* iicbus interface */
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DEVMETHOD(iicbus_callback, iicbus_null_callback),
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DEVMETHOD(iicbus_repeated_start, iicoc_repeated_start),
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DEVMETHOD(iicbus_start, iicoc_start),
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DEVMETHOD(iicbus_stop, iicoc_stop),
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DEVMETHOD(iicbus_reset, iicoc_reset),
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DEVMETHOD(iicbus_write, iicoc_write),
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DEVMETHOD(iicbus_read, iicoc_read),
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DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
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DEVMETHOD_END
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};
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static driver_t iicoc_driver = {
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"iicoc",
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iicoc_methods,
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sizeof(struct iicoc_softc),
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};
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DRIVER_MODULE(iicoc, pci, iicoc_driver, iicoc_devclass, 0, 0);
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DRIVER_MODULE(iicbus, iicoc, iicbus_driver, iicbus_devclass, 0, 0);
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78
sys/dev/iicbus/iicoc.h
Normal file
78
sys/dev/iicbus/iicoc.h
Normal file
@ -0,0 +1,78 @@
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/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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* $FreeBSD$
|
||||
*/
|
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|
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#ifndef __OPENCORE_I2C_H__
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#define __OPENCORE_I2C_H__
|
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|
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/* I2C specific registers */
|
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#define OC_I2C_PRESCALE_LO_REG 0x00
|
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#define OC_I2C_PRESCALE_HI_REG 0x01
|
||||
#define OC_I2C_CTRL_REG 0x02
|
||||
#define OC_I2C_TRANSMIT_REG 0x03 /* tx and rx - same reg */
|
||||
#define OC_I2C_RECV_REG 0x03 /* tx and rx - same reg */
|
||||
#define OC_I2C_DATA_REG 0x03 /* tx and rx - same reg */
|
||||
#define OC_I2C_CMD_REG 0x04 /* cmd and status - same reg */
|
||||
#define OC_I2C_STATUS_REG 0x04 /* cmd and status - same reg */
|
||||
|
||||
#define XLP_I2C_CLKFREQ 133333333 /* XLP 133 MHz IO clock */
|
||||
#define XLP_I2C_FREQ 100000 /* default 100kHz */
|
||||
#define I2C_TIMEOUT 500000
|
||||
|
||||
/*
|
||||
* These defines pertain to the OpenCores
|
||||
* I2C Master Host Controller used in XLP
|
||||
*/
|
||||
|
||||
#define OC_PRESCALER_LO 0
|
||||
#define OC_PRESCALER_HI 1
|
||||
|
||||
#define OC_CONTROL 2
|
||||
#define OC_CONTROL_EN 0x80
|
||||
#define OC_CONTROL_IEN 0x40
|
||||
|
||||
#define OC_DATA 3 /* Data TX & RX Reg */
|
||||
|
||||
#define OC_COMMAND 4
|
||||
#define OC_COMMAND_START 0x90
|
||||
#define OC_COMMAND_STOP 0x40
|
||||
#define OC_COMMAND_READ 0x20
|
||||
#define OC_COMMAND_WRITE 0x10
|
||||
#define OC_COMMAND_RDACK 0x20
|
||||
#define OC_COMMAND_RDNACK 0x28
|
||||
#define OC_COMMAND_IACK 0x01 /* Not used */
|
||||
|
||||
#define OC_STATUS 4 /* Same as 'command' */
|
||||
#define OC_STATUS_NACK 0x80 /* Did not get an ACK */
|
||||
#define OC_STATUS_BUSY 0x40
|
||||
#define OC_STATUS_AL 0x20 /* Arbitration Lost */
|
||||
#define OC_STATUS_TIP 0x02 /* Transfer in Progress */
|
||||
#define OC_STATUS_IF 0x01 /* Intr. Pending Flag */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user