Add Altivec support for supported CPUs. This is derived from the FPU support
code, and also reducing the size of trapcode to fit inside a 32 byte handler slot. Reviewed by: grehan MFC after: 2 weeks
This commit is contained in:
Nathan Whitehorn
parent
9d13a605d4
commit
1ac37bcb77
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=188860
@ -103,6 +103,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm_object.h>
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#include <vm/vm_pager.h>
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#include <machine/altivec.h>
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#include <machine/bat.h>
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#include <machine/cpu.h>
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#include <machine/elf.h>
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@ -238,7 +239,6 @@ extern void *dsitrap, *dsisize;
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extern void *decrint, *decrsize;
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extern void *extint, *extsize;
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extern void *dblow, *dbsize;
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extern void *vectrap, *vectrapsize;
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u_int
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powerpc_init(u_int startkernel, u_int endkernel, u_int basekernel, void *mdp)
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@ -340,7 +340,7 @@ powerpc_init(u_int startkernel, u_int endkernel, u_int basekernel, void *mdp)
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bcopy(&trapcode, (void *)EXC_SC, (size_t)&trapsize);
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bcopy(&trapcode, (void *)EXC_TRC, (size_t)&trapsize);
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bcopy(&trapcode, (void *)EXC_FPA, (size_t)&trapsize);
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bcopy(&vectrap, (void *)EXC_VEC, (size_t)&vectrapsize);
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bcopy(&trapcode, (void *)EXC_VEC, (size_t)&trapsize);
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bcopy(&trapcode, (void *)EXC_VECAST, (size_t)&trapsize);
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bcopy(&trapcode, (void *)EXC_THRM, (size_t)&trapsize);
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bcopy(&trapcode, (void *)EXC_BPT, (size_t)&trapsize);
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@ -647,7 +647,21 @@ grab_mcontext(struct thread *td, mcontext_t *mcp, int flags)
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memcpy(mcp->mc_fpreg, pcb->pcb_fpu.fpr, 32*sizeof(double));
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}
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/* XXX Altivec context ? */
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/*
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* Repeat for Altivec context
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*/
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if (pcb->pcb_flags & PCB_VEC) {
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KASSERT(td == curthread,
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("get_mcontext: fp save not curthread"));
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critical_enter();
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save_vec(td);
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critical_exit();
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mcp->mc_flags |= _MC_AV_VALID;
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mcp->mc_vscr = pcb->pcb_vec.vscr;
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mcp->mc_vrsave = pcb->pcb_vec.vrsave;
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memcpy(mcp->mc_avec, pcb->pcb_vec.vr, sizeof(mcp->mc_avec));
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}
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mcp->mc_len = sizeof(*mcp);
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@ -701,7 +715,17 @@ set_mcontext(struct thread *td, const mcontext_t *mcp)
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memcpy(pcb->pcb_fpu.fpr, mcp->mc_fpreg, 32*sizeof(double));
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}
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/* XXX Altivec context? */
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if (mcp->mc_flags & _MC_AV_VALID) {
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if ((pcb->pcb_flags & PCB_VEC) != PCB_VEC) {
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critical_enter();
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enable_vec(td);
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critical_exit();
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}
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pcb->pcb_vec.vscr = mcp->mc_vscr;
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pcb->pcb_vec.vrsave = mcp->mc_vrsave;
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memcpy(pcb->pcb_vec.vr, mcp->mc_avec, sizeof(mcp->mc_avec));
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}
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return (0);
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}
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@ -106,8 +106,16 @@ ENTRY(cpu_switch)
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andi. %r6, %r6, PCB_FPU
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beq .L1
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bl save_fpu
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mr %r3,%r14 /* restore old thread ptr */
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.L1:
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lwz %r6,PCB_FLAGS(%r5)
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/* Save Altivec context if needed */
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andi. %r6, %r6, PCB_VEC
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beq .L2
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bl save_vec
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.L2:
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mr %r3,%r14 /* restore old thread ptr */
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bl pmap_deactivate /* Deactivate the current pmap */
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cpu_switchin:
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@ -122,12 +130,20 @@ cpu_switchin:
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lwz %r6, PCB_FLAGS(%r17)
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/* Restore FPU context if needed */
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andi. %r6, %r6, PCB_FPU
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beq .L2
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beq .L3
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mr %r3,%r15 /* Pass curthread to enable_fpu */
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bl enable_fpu
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.L3:
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lwz %r6, PCB_FLAGS(%r17)
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/* Restore Altivec context if needed */
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andi. %r6, %r6, PCB_VEC
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beq .L4
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mr %r3,%r15 /* Pass curthread to enable_vec */
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bl enable_vec
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/* thread to restore is in r3 */
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.L2:
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.L4:
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mr %r3,%r17 /* Recover PCB ptr */
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lmw %r12,PCB_CONTEXT(%r3) /* Load the non-volatile GP regs */
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mr %r2,%r12
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@ -65,6 +65,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm_map.h>
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#include <vm/vm_page.h>
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#include <machine/altivec.h>
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#include <machine/cpu.h>
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#include <machine/db_machdep.h>
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#include <machine/fpu.h>
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@ -188,24 +189,16 @@ trap(struct trapframe *frame)
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enable_fpu(td);
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break;
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#ifdef ALTIVEC
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case EXC_VEC:
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if ((vecthread = PCPU_GET(vecthread)) != NULL) {
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KASSERT(vecthread != td,
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("altivec already enabled"));
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save_vec(vecthread);
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}
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PCPU_SET(vecthread, td);
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td->td_pcb->pcb_veccpu = PCPU_GET(cpuid);
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KASSERT((td->td_pcb->pcb_flags & PCB_VEC) != PCB_VEC,
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("Altivec already enabled for thread"));
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enable_vec(td);
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frame->srr1 |= PSL_VEC;
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break;
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#else
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case EXC_VEC:
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case EXC_VECAST:
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printf("Vector assist exception!\n");
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sig = SIGILL;
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break;
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#endif /* ALTIVEC */
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case EXC_ALI:
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if (fix_unaligned(td, frame) != 0)
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@ -79,13 +79,13 @@
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/*
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* FRAME_SETUP assumes:
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* SPRG1 SP (1)
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* SPRG3 trap type
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* savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
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* r28 LR
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* r29 CR
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* r30 scratch
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* r31 scratch
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* r1 kernel stack
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* LR trap type (from calling address, mask with 0xff00)
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* SRR0/1 as at start of trap
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*/
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#define FRAME_SETUP(savearea) \
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@ -146,8 +146,7 @@
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lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
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mfxer %r3; \
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mfctr %r4; \
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mflr %r5; \
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andi. %r5,%r5,0xff00; /* convert LR to exc # */ \
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mfsprg3 %r5; \
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stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \
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stw %r4, FRAME_CTR+8(1); \
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stw %r5, FRAME_EXC+8(1); \
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@ -264,18 +263,10 @@ CNAME(rstsize) = . - CNAME(rstcode)
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.globl CNAME(trapcode),CNAME(trapsize)
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CNAME(trapcode):
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mtsprg1 %r1 /* save SP */
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GET_CPUINFO(%r1)
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stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
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stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
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stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
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stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
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mfsprg1 %r1 /* restore SP, in case of branch */
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mflr %r28 /* save LR */
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mfcr %r29 /* save CR */
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/* Test whether we already had PR set */
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mfsrr1 %r31
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mtcr %r31
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bla s_trap /* LR & 0xff00 is exception # */
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mflr %r1 /* Save the old LR in r1 */
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mtsprg2 %r1 /* And then in SPRG2 */
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li %r1, 0x20 /* How to get the vector from LR */
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bla generictrap /* LR & SPRG3 is exception # */
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CNAME(trapsize) = .-CNAME(trapcode)
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/*
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@ -296,10 +287,15 @@ CNAME(alitrap):
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mfsprg1 %r1 /* restore SP, in case of branch */
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mflr %r28 /* save LR */
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mfcr %r29 /* save CR */
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/* Put our exception vector in SPRG0 */
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li %r31, EXC_ALI
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mtsprg3 %r31
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/* Test whether we already had PR set */
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mfsrr1 %r31
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mtcr %r31
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bla s_trap /* LR & 0xff00 is exception # */
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bla s_trap
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CNAME(alisize) = .-CNAME(alitrap)
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/*
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@ -364,6 +360,11 @@ CNAME(dsisize) = .-CNAME(dsitrap)
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* Preamble code for DSI/ISI traps
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*/
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disitrap:
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/* Write the trap vector to SPRG0 by computing LR & 0xff00 */
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mflr %r1
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andi. %r1,%r1,0xff00
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mtsprg3 %r1
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GET_CPUINFO(%r1)
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lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
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stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
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@ -416,6 +417,47 @@ realtrap:
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mtcr %r1
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mfsprg1 %r1 /* restore SP (might have been
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overwritten) */
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bf 17,k_trap /* branch if PSL_PR is false */
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GET_CPUINFO(%r1)
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lwz %r1,PC_CURPCB(%r1)
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RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
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ba s_trap
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/*
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* generictrap does some standard setup for trap handling to minimize
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* the code that need be installed in the actual vectors. It expects
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* the following conditions.
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*
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* R1 - Trap vector = LR & (0xff00 | R1)
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* SPRG1 - Original R1 contents
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* SPRG2 - Original LR
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*/
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generictrap:
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/* Save R1 for computing the exception vector */
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mtsprg3 %r1
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/* Save interesting registers */
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GET_CPUINFO(%r1)
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stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
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stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
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stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
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stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
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mfsprg1 %r1 /* restore SP, in case of branch */
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mfsprg2 %r28 /* save LR */
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mfcr %r29 /* save CR */
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/* Compute the exception vector from the link register */
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mfsprg3 %r31
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ori %r31,%r31,0xff00
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mflr %r30
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and %r30,%r30,%r31
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mtsprg3 %r30
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/* Test whether we already had PR set */
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mfsrr1 %r31
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mtcr %r31
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s_trap:
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bf 17,k_trap /* branch if PSL_PR is false */
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GET_CPUINFO(%r1)
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@ -464,14 +506,6 @@ CNAME(asttrapexit):
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FRAME_LEAVE(PC_TEMPSAVE)
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rfi
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/*
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* Temporary: vector-unavailable traps are directed to vector-assist traps
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*/
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.globl CNAME(vectrap),CNAME(vectrapsize)
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CNAME(vectrap):
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ba EXC_VECAST
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CNAME(vectrapsize) = .-CNAME(vectrap)
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#if defined(KDB)
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/*
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* Deliberate entry to dbtrap
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@ -499,6 +533,14 @@ CNAME(breakpoint):
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* Now the kdb trap catching code.
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*/
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dbtrap:
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/* Write the trap vector to SPRG0 by computing LR & 0xff00 */
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mflr %r1
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andi. %r1,%r1,0xff00
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mtsprg3 %r1
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lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */
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addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l
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FRAME_SETUP(PC_DBSAVE)
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/* Call C trap code: */
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addi %r3,%r1,8
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@ -536,24 +578,25 @@ CNAME(dblow):
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mfcr %r29 /* save CR in r29 */
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mfsrr1 %r1
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mtcr %r1
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GET_CPUINFO(%r1)
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bf 17,1f /* branch if privileged */
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stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28 */
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mfsprg2 %r28 /* r29 holds cr ... */
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stw %r28,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) /* free r29 */
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stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) /* free r30 */
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stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) /* free r31 */
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mflr %r28 /* save LR */
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bla u_trap
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/* Unprivileged case */
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mtcr %r29 /* put the condition register back */
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mfsprg2 %r29 /* ... and r29 */
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mflr %r1 /* save LR */
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mtsprg2 %r1 /* And then in SPRG2 */
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li %r1, 0 /* How to get the vector from LR */
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bla generictrap /* and we look like a generic trap */
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1:
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/* Privileged, so drop to KDB */
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GET_CPUINFO(%r1)
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stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
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mfsprg2 %r28 /* r29 holds cr... */
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stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
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stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
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stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
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mflr %r28 /* save LR */
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lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */
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addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l
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bla dbtrap
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CNAME(dbsize) = .-CNAME(dblow)
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#endif /* KDB */
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36
sys/powerpc/include/altivec.h
Normal file
36
sys/powerpc/include/altivec.h
Normal file
@ -0,0 +1,36 @@
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/*-
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* Copyright (c) 2008 Nathan Whitehorn
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ALTIVEC_H_
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#define _MACHINE_ALTIVEC_H_
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void enable_vec(struct thread *);
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void save_vec(struct thread *);
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#endif /* _MACHINE_ALTIVEC_H_ */
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@ -47,12 +47,21 @@ struct pcb {
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copyin/copyout */
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int pcb_flags;
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#define PCB_FPU 1 /* Process had FPU initialized */
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#define PCB_VEC 2 /* Process had Altivec initialized */
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struct fpu {
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double fpr[32];
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double fpscr; /* FPSCR stored as double for easier access */
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} pcb_fpu; /* Floating point processor */
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unsigned int pcb_fpcpu; /* which CPU had our FPU
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stuff. */
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struct vec {
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uint32_t vr[32][4];
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register_t vrsave;
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register_t spare[2];
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register_t vscr;
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} pcb_vec __attribute__((aligned(16))); /* Vector processor */
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unsigned int pcb_veccpu; /* which CPU had our vector
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stuff. */
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union {
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struct {
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@ -39,6 +39,7 @@ struct pmap;
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int pc_inside_intr; \
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struct pmap *pc_curpmap; /* current pmap */ \
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struct thread *pc_fputhread; /* current fpu user */ \
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struct thread *pc_vecthread; /* current vec user */ \
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uintptr_t pc_hwref; \
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uint32_t pc_pir; \
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int pc_bsp:1; \
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152
sys/powerpc/powerpc/altivec.c
Normal file
152
sys/powerpc/powerpc/altivec.c
Normal file
@ -0,0 +1,152 @@
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/*-
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* Copyright (C) 1996 Wolfgang Solfrank.
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* Copyright (C) 1996 TooLs GmbH.
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* All rights reserved.
|
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by TooLs GmbH.
|
||||
* 4. The name of TooLs GmbH may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $NetBSD: fpu.c,v 1.5 2001/07/22 11:29:46 wiz Exp $
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/proc.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/limits.h>
|
||||
|
||||
#include <machine/altivec.h>
|
||||
#include <machine/pcb.h>
|
||||
#include <machine/psl.h>
|
||||
|
||||
void
|
||||
enable_vec(struct thread *td)
|
||||
{
|
||||
int msr;
|
||||
struct pcb *pcb;
|
||||
struct trapframe *tf;
|
||||
|
||||
pcb = td->td_pcb;
|
||||
tf = trapframe(td);
|
||||
|
||||
/*
|
||||
* Save the thread's Altivec CPU number, and set the CPU's current
|
||||
* vector thread
|
||||
*/
|
||||
td->td_pcb->pcb_veccpu = PCPU_GET(cpuid);
|
||||
PCPU_SET(vecthread, td);
|
||||
|
||||
/*
|
||||
* Enable the vector unit for when the thread returns from the
|
||||
* exception. If this is the first time the unit has been used by
|
||||
* the thread, initialise the vector registers and VSCR to 0, and
|
||||
* set the flag to indicate that the vector unit is in use.
|
||||
*/
|
||||
tf->srr1 |= PSL_VEC;
|
||||
if (!(pcb->pcb_flags & PCB_VEC)) {
|
||||
memset(&pcb->pcb_vec, 0, sizeof pcb->pcb_vec);
|
||||
pcb->pcb_flags |= PCB_VEC;
|
||||
}
|
||||
|
||||
/*
|
||||
* Temporarily enable the vector unit so the registers
|
||||
* can be restored.
|
||||
*/
|
||||
msr = mfmsr();
|
||||
mtmsr(msr | PSL_VEC);
|
||||
isync();
|
||||
|
||||
/*
|
||||
* Restore VSCR by first loading it into a vector and then into VSCR.
|
||||
* (this needs to done before loading the user's vector registers
|
||||
* since we need to use a scratch vector register)
|
||||
*/
|
||||
__asm __volatile("vxor 0,0,0; lvewx 0,0,%0; mtvscr 0" \
|
||||
:: "b"(&pcb->pcb_vec.vscr));
|
||||
|
||||
#define LVX(n) __asm ("lvx " #n ",0,%0" \
|
||||
:: "b"(&pcb->pcb_vec.vr[n]));
|
||||
LVX(0); LVX(1); LVX(2); LVX(3);
|
||||
LVX(4); LVX(5); LVX(6); LVX(7);
|
||||
LVX(8); LVX(9); LVX(10); LVX(11);
|
||||
LVX(12); LVX(13); LVX(14); LVX(15);
|
||||
LVX(16); LVX(17); LVX(18); LVX(19);
|
||||
LVX(20); LVX(21); LVX(22); LVX(23);
|
||||
LVX(24); LVX(25); LVX(26); LVX(27);
|
||||
LVX(28); LVX(29); LVX(30); LVX(31);
|
||||
#undef LVX
|
||||
|
||||
isync();
|
||||
mtmsr(msr);
|
||||
}
|
||||
|
||||
void
|
||||
save_vec(struct thread *td)
|
||||
{
|
||||
int msr;
|
||||
struct pcb *pcb;
|
||||
|
||||
pcb = td->td_pcb;
|
||||
|
||||
/*
|
||||
* Temporarily re-enable the vector unit during the save
|
||||
*/
|
||||
msr = mfmsr();
|
||||
mtmsr(msr | PSL_VEC);
|
||||
isync();
|
||||
|
||||
/*
|
||||
* Save the vector registers and VSCR to the PCB
|
||||
*/
|
||||
#define STVX(n) __asm ("stvx %1,0,%0" \
|
||||
:: "b"(pcb->pcb_vec.vr[n]), "n"(n));
|
||||
STVX(0); STVX(1); STVX(2); STVX(3);
|
||||
STVX(4); STVX(5); STVX(6); STVX(7);
|
||||
STVX(8); STVX(9); STVX(10); STVX(11);
|
||||
STVX(12); STVX(13); STVX(14); STVX(15);
|
||||
STVX(16); STVX(17); STVX(18); STVX(19);
|
||||
STVX(20); STVX(21); STVX(22); STVX(23);
|
||||
STVX(24); STVX(25); STVX(26); STVX(27);
|
||||
STVX(28); STVX(29); STVX(30); STVX(31);
|
||||
#undef STVX
|
||||
|
||||
__asm __volatile("mfvscr 0; stvewx 0,0,%0" :: "b"(&pcb->pcb_vec.vscr));
|
||||
|
||||
/*
|
||||
* Disable vector unit again
|
||||
*/
|
||||
isync();
|
||||
mtmsr(msr);
|
||||
|
||||
/*
|
||||
* Clear the current vec thread and pcb's CPU id
|
||||
* XXX should this be left clear to allow lazy save/restore ?
|
||||
*/
|
||||
pcb->pcb_veccpu = INT_MAX;
|
||||
PCPU_SET(vecthread, NULL);
|
||||
}
|
||||
|
||||
@ -171,6 +171,7 @@ ASSYM(PCB_LR, offsetof(struct pcb, pcb_lr));
|
||||
ASSYM(PCB_ONFAULT, offsetof(struct pcb, pcb_onfault));
|
||||
ASSYM(PCB_FLAGS, offsetof(struct pcb, pcb_flags));
|
||||
ASSYM(PCB_FPU, PCB_FPU);
|
||||
ASSYM(PCB_VEC, PCB_VEC);
|
||||
|
||||
ASSYM(PCB_AIM_USR, offsetof(struct pcb, pcb_cpu.aim.usr));
|
||||
ASSYM(PCB_BOOKE_CTR, offsetof(struct pcb, pcb_cpu.booke.ctr));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user