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Be more conservative when enabling write-combining on MIPS

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Some MIPS revisions do implement uncached-accelerate caching
attribute, but place extra requirement on access, such as
partial-word or out-of-sequence writes potentially having an
“unpredictable” effects.
This commit is contained in:
Alexander Kabaev 2016-12-28 13:48:00 +00:00
parent c75d636205
commit 1b664b2eea
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=310700
1 changed files with 1 additions and 10 deletions
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11
sys/mips/include/cpuregs.h
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@ -173,6 +173,7 @@
#if defined(CPU_XBURST)
#define MIPS_CCA_UA 0x01
#define MIPS_CCA_WC MIPS_CCA_UA
#endif
#ifndef MIPS_CCA_UNCACHED
@ -192,16 +193,6 @@
#endif
#endif
/*
* Use uncached-accelerated mode for write-combining maps, if one is defined,
* otherwise fall back to uncached
*/
#ifndef MIPS_CCA_WC
#ifdef MIPS_CCA_UA
#define MIPS_CCA_WC MIPS_CCA_UA
#endif
#endif
#define MIPS_PHYS_TO_XKPHYS(cca,x) \
((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \