Be more conservative when enabling write-combining on MIPS
Some MIPS revisions do implement uncached-accelerate caching attribute, but place extra requirement on access, such as partial-word or out-of-sequence writes potentially having an “unpredictable” effects.
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=310700
@ -173,6 +173,7 @@
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#if defined(CPU_XBURST)
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#define MIPS_CCA_UA 0x01
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#define MIPS_CCA_WC MIPS_CCA_UA
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#endif
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#ifndef MIPS_CCA_UNCACHED
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@ -192,16 +193,6 @@
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#endif
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#endif
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/*
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* Use uncached-accelerated mode for write-combining maps, if one is defined,
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* otherwise fall back to uncached
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*/
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#ifndef MIPS_CCA_WC
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#ifdef MIPS_CCA_UA
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#define MIPS_CCA_WC MIPS_CCA_UA
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#endif
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#endif
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#define MIPS_PHYS_TO_XKPHYS(cca,x) \
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((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
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#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
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