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On a context switch, handle the possibility that the old thread was

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preempted after an "ic" or "tlbi" instruction but before it performed a
"dsb" instruction.  The "ic" and "tlbi" instructions have unusual
synchronization requirements.  If the old thread migrates to a new
processor, its completion of a "dsb" instruction on that new processor does
not guarantee that the "ic" or "tlbi" instructions performed on the old
processor have completed.

This issue is not restricted to the kernel.  Since locore.S sets the UCI bit
in SCTLR, user-space programs can perform "ic ivau" instructions (as well as
some forms of the "dc" instruction).

Reviewed by:	andrew, kib, markj, mmel
X-MFC with:	r355145
Differential Revision:	https://reviews.freebsd.org/D22622
This commit is contained in:
Alan Cox 2019-12-05 19:25:49 +00:00
parent 65d2f9c12b
commit 1bef4955bc
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=355427
1 changed files with 11 additions and 1 deletions
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12
sys/arm64/arm64/pmap.c
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@ -5850,8 +5850,18 @@ pmap_activate_int(pmap_t pmap)
KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
if (pmap == PCPU_GET(curpmap))
if (pmap == PCPU_GET(curpmap)) {
/*
* Handle the possibility that the old thread was preempted
* after an "ic" or "tlbi" instruction but before it performed
* a "dsb" instruction. If the old thread migrates to a new
* processor, its completion of a "dsb" instruction on that
* new processor does not guarantee that the "ic" or "tlbi"
* instructions performed on the old processor have completed.
*/
dsb(ish);
return (false);
}
/*
* Ensure that the store to curpmap is globally visible before the