Add FPU support for MIPS setjmp(3)/longjmp(3).
This change saves/restores the callee-saved MIPS floating point
registers as documented by the o32/n32/n64 spec ("MIPSpro N32
ABI Handbook", Table 2-1) for the _setjmp(3), _longjmp(3),
setjmp(3) and longjmp(3) C library functions. This is only
included when the C library is built with hardware floating point
support (or when "SOFTFLOAT" is not defined).
Submitted by: sson
MFC after: 1 month
Sponsored by: DARPA, AFRL
This commit is contained in:
Brooks Davis
parent
0e97688fe1
commit
1e7bf26b33
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=274816
@ -61,9 +61,16 @@ __FBSDID("$FreeBSD$");
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LEAF(_setjmp)
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REG_PROLOGUE
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REG_LI v0, _JB_MAGIC__SETJMP
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REG_LI v0, _JB_MAGIC__SETJMP # sigcontext magic number
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REG_S v0, (_JB_MAGIC * SZREG)(a0)
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REG_S ra, (_JB_REG_RA * SZREG)(a0)
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* Registers s0..s7 are callee-saved.
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* The sp register is callee-saved.
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* The fp (or s8) register is callee-saved.
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* The gp register is callee-saved (for n32/n64).
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*/
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REG_S s0, (_JB_REG_S0 * SZREG)(a0)
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REG_S s1, (_JB_REG_S1 * SZREG)(a0)
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REG_S s2, (_JB_REG_S2 * SZREG)(a0)
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@ -72,11 +79,41 @@ LEAF(_setjmp)
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REG_S s5, (_JB_REG_S5 * SZREG)(a0)
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REG_S s6, (_JB_REG_S6 * SZREG)(a0)
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REG_S s7, (_JB_REG_S7 * SZREG)(a0)
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REG_S sp, (_JB_REG_SP * SZREG)(a0)
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REG_S s8, (_JB_REG_S8 * SZREG)(a0)
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#if defined(__mips_n32) || defined(__mips_n64)
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REG_S gp, (_JB_REG_GP * SZREG)(a0) # newabi gp is callee-saved
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#endif
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REG_S sp, (_JB_REG_SP * SZREG)(a0)
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
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* In N64, FP registers F24 .. F31 are callee-saved.
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* In O32, FP registers F20 .. F23 are callee-saved.
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*/
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#ifndef SOFTFLOAT
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cfc1 v0, $31 # too bad can't check if FP used
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#if defined(__mips_n64) || defined(__mips_n32)
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FP_S $f30, (_JB_FPREG_F30 * SZREG)(a0)
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FP_S $f28, (_JB_FPREG_F28 * SZREG)(a0)
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FP_S $f26, (_JB_FPREG_F26 * SZREG)(a0)
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FP_S $f24, (_JB_FPREG_F24 * SZREG)(a0)
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#endif
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#if defined(__mips_n32) || defined(__mips_o32) || defined(__mips_o64)
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FP_S $f22, (_JB_FPREG_F22 * SZREG)(a0)
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FP_S $f20, (_JB_FPREG_F20 * SZREG)(a0)
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#endif
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#if defined(__mips_o32) || defined(__mips_o64)
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FP_S $f21, (_JB_FPREG_F21 * SZREG)(a0)
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FP_S $f23, (_JB_FPREG_F23 * SZREG)(a0)
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#endif
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#if defined(__mips_n64)
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FP_S $f25, (_JB_FPREG_F25 * SZREG)(a0)
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FP_S $f27, (_JB_FPREG_F27 * SZREG)(a0)
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FP_S $f29, (_JB_FPREG_F29 * SZREG)(a0)
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FP_S $f31, (_JB_FPREG_F31 * SZREG)(a0)
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#endif
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INT_S v0, (_JB_FPREG_FCSR * SZREG)(a0)
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#endif /* ! SOFTFLOAT */
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REG_EPILOGUE
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j ra
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@ -94,6 +131,13 @@ LEAF(_longjmp)
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REG_LI t0, _JB_MAGIC__SETJMP
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bne v0, t0, botch # jump if error
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PTR_ADDU sp, sp, CALLFRAME_SIZ # does not matter, sanity
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* Registers s0..s7 are callee-saved.
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* The sp register is callee-saved.
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* The fp (or s8) register is callee-saved.
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* The gp register is callee-saved (for n32/n64).
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*/
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REG_L s0, (_JB_REG_S0 * SZREG)(a0)
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REG_L s1, (_JB_REG_S1 * SZREG)(a0)
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REG_L s2, (_JB_REG_S2 * SZREG)(a0)
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@ -102,11 +146,42 @@ LEAF(_longjmp)
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REG_L s5, (_JB_REG_S5 * SZREG)(a0)
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REG_L s6, (_JB_REG_S6 * SZREG)(a0)
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REG_L s7, (_JB_REG_S7 * SZREG)(a0)
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REG_L sp, (_JB_REG_SP * SZREG)(a0)
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REG_L s8, (_JB_REG_S8 * SZREG)(a0)
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#if defined(__mips_n32) || defined(__mips_n64)
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REG_L gp, (_JB_REG_GP * SZREG)(a0)
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#endif
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REG_L sp, (_JB_REG_SP * SZREG)(a0)
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REG_L s8, (_JB_REG_S8 * SZREG)(a0)
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#ifndef SOFTFLOAT
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# get fpu status
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INT_L v0, (_JB_FPREG_FCSR * SZREG)(a0)
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ctc1 v0, $31
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
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* In N64, FP registers F24 .. F31 are callee-saved.
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* In O32, FP registers F20 .. F23 are callee-saved.
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*/
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#if defined(__mips_n64) || defined(__mips_n32)
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FP_L $f30, (_JB_FPREG_F30 * SZREG)(a0)
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FP_L $f28, (_JB_FPREG_F28 * SZREG)(a0)
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FP_L $f26, (_JB_FPREG_F26 * SZREG)(a0)
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FP_L $f24, (_JB_FPREG_F24 * SZREG)(a0)
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#endif
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#if defined(__mips_n32) || defined(__mips_o32) || defined(__mips_o64)
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FP_L $f22, (_JB_FPREG_F22 * SZREG)(a0)
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FP_L $f20, (_JB_FPREG_F20 * SZREG)(a0)
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#endif
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#if defined(__mips_o32) || defined(__mips_o64)
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FP_L $f21, (_JB_FPREG_F21 * SZREG)(a0)
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FP_L $f23, (_JB_FPREG_F23 * SZREG)(a0)
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#endif
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#if defined(__mips_n64)
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FP_L $f25, (_JB_FPREG_F25 * SZREG)(a0)
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FP_L $f27, (_JB_FPREG_F27 * SZREG)(a0)
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FP_L $f29, (_JB_FPREG_F29 * SZREG)(a0)
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FP_L $f31, (_JB_FPREG_F31 * SZREG)(a0)
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#endif
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#endif /* ! SOFTFLOAT */
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REG_EPILOGUE
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move v0, a1 # get return value in 1st arg
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@ -86,6 +86,13 @@ NESTED(setjmp, SETJMP_FRAME_SIZE, ra)
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REG_LI v0, _JB_MAGIC_SETJMP
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REG_S v0, (_JB_MAGIC * SZREG)(a0)
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REG_S ra, (_JB_REG_RA * SZREG)(a0)
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* Registers s0..s7 are callee-saved.
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* The sp register is callee-saved.
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* The fp (or s8) register is callee-saved.
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* The gp register is callee-saved (for n32/n64).
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*/
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REG_S s0, (_JB_REG_S0 * SZREG)(a0)
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REG_S s1, (_JB_REG_S1 * SZREG)(a0)
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REG_S s2, (_JB_REG_S2 * SZREG)(a0)
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@ -99,6 +106,36 @@ NESTED(setjmp, SETJMP_FRAME_SIZE, ra)
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#if defined(__mips_n32) || defined(__mips_n64)
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REG_S gp, (_JB_REG_GP * SZREG)(a0)
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#endif
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#ifndef SOFTFLOAT
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
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* In N64, FP registers F24 .. F31 are callee-saved.
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* In O32, FP registers F20 .. F23 are callee-saved.
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*/
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cfc1 v0, $31
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INT_S v0, (_JB_FPREG_FCSR * SZREG)(a0)
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#if defined(__mips_o32) || defined(__mips_o64) || defined(__mips_n32)
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FP_S $f20, (_JB_FPREG_F20 * SZREG)(a0)
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FP_S $f22, (_JB_FPREG_F22 * SZREG)(a0)
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#endif
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#if defined(__mips_o32) || defined(__mips_o64)
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FP_S $f21, (_JB_FPREG_F21 * SZREG)(a0)
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FP_S $f23, (_JB_FPREG_F23 * SZREG)(a0)
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#endif
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#if defined(__mips_n32) || defined(__mips_n64)
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FP_S $f24, (_JB_FPREG_F24 * SZREG)(a0)
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FP_S $f26, (_JB_FPREG_F26 * SZREG)(a0)
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FP_S $f28, (_JB_FPREG_F28 * SZREG)(a0)
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FP_S $f30, (_JB_FPREG_F30 * SZREG)(a0)
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#endif
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#if defined(__mips_n64)
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FP_S $f25, (_JB_FPREG_F25 * SZREG)(a0)
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FP_S $f27, (_JB_FPREG_F27 * SZREG)(a0)
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FP_S $f29, (_JB_FPREG_F29 * SZREG)(a0)
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FP_S $f31, (_JB_FPREG_F31 * SZREG)(a0)
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#endif
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#endif /* ! SOFTFLOAT */
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move v0, zero
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jr ra
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@ -133,6 +170,13 @@ NESTED(longjmp, LONGJMP_FRAME_SIZE, ra)
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REG_L a1, (CALLFRAME_SIZ + SZREG)(sp) # restore return value
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REG_L ra, (_JB_REG_RA * SZREG)(a0)
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* Registers s0..s7 are callee-saved.
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* The sp register is callee-saved.
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* The fp (or s8) register is callee-saved.
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* The gp register is callee-saved (for n32/n64).
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*/
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REG_L s0, (_JB_REG_S0 * SZREG)(a0)
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REG_L s1, (_JB_REG_S1 * SZREG)(a0)
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REG_L s2, (_JB_REG_S2 * SZREG)(a0)
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@ -146,6 +190,36 @@ NESTED(longjmp, LONGJMP_FRAME_SIZE, ra)
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#if defined(__mips_n32) || defined(__mips_n64)
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REG_L gp, (_JB_REG_GP * SZREG)(a0)
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#endif
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#ifndef SOFTFLOAT
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/*
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* From "MIPSpro N32 ABI Handbook", Table 2-1:
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* In N32, FP registers F20, F22, F24, F26, F28, F30 are callee-saved.
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* In N64, FP registers F23 .. F31 are callee-saved.
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* In O32, FP registers F20 .. F23 are callee-saved.
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*/
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INT_L v0, (_JB_FPREG_FCSR * SZREG)(a0)
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ctc1 v0, $31
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#if defined(__mips_n64) || defined(__mips_n32)
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FP_L $f30, (_JB_FPREG_F30 * SZREG)(a0)
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FP_L $f28, (_JB_FPREG_F28 * SZREG)(a0)
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FP_L $f26, (_JB_FPREG_F26 * SZREG)(a0)
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FP_L $f24, (_JB_FPREG_F24 * SZREG)(a0)
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#endif
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#if defined(__mips_n32) || defined(__mips_o32) || defined(__mips_o64)
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FP_L $f22, (_JB_FPREG_F22 * SZREG)(a0)
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FP_L $f20, (_JB_FPREG_F20 * SZREG)(a0)
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#endif
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#if defined(__mips_o32) || defined(__mips_o64)
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FP_L $f21, (_JB_FPREG_F21 * SZREG)(a0)
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FP_L $f23, (_JB_FPREG_F23 * SZREG)(a0)
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#endif
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#if defined(__mips_n64)
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FP_L $f25, (_JB_FPREG_F25 * SZREG)(a0)
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FP_L $f27, (_JB_FPREG_F27 * SZREG)(a0)
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FP_L $f29, (_JB_FPREG_F29 * SZREG)(a0)
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FP_L $f31, (_JB_FPREG_F31 * SZREG)(a0)
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#endif
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#endif /* ! SOFTFLOAT */
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move v0, a1
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j ra
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@ -667,6 +667,20 @@ _C_LABEL(x):
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#define _JB_SIGMASK 13
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#define _JB_FPREG_F20 14
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#define _JB_FPREG_F21 15
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#define _JB_FPREG_F22 16
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#define _JB_FPREG_F23 17
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#define _JB_FPREG_F24 18
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#define _JB_FPREG_F25 19
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#define _JB_FPREG_F26 20
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#define _JB_FPREG_F27 21
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#define _JB_FPREG_F28 22
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#define _JB_FPREG_F29 23
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#define _JB_FPREG_F30 24
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#define _JB_FPREG_F31 25
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#define _JB_FPREG_FCSR 26
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/*
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* Various macros for dealing with TLB hazards
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* (a) why so many?
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