Add Intel Ivy Bridge support to hwpmc(9).
Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
This commit is contained in:
parent
448ba34319
commit
1e862e5ad0
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=240164
@ -28,6 +28,7 @@ MAN+= pmc.atom.3
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MAN+= pmc.core.3
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MAN+= pmc.core2.3
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MAN+= pmc.iaf.3
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MAN+= pmc.ivybridge.3
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MAN+= pmc.ucf.3
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MAN+= pmc.k7.3
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MAN+= pmc.k8.3
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@ -183,6 +183,11 @@ static const struct pmc_event_descr corei7_event_table[] =
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__PMC_EV_ALIAS_COREI7()
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};
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static const struct pmc_event_descr ivybridge_event_table[] =
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{
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__PMC_EV_ALIAS_IVYBRIDGE()
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};
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static const struct pmc_event_descr sandybridge_event_table[] =
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{
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__PMC_EV_ALIAS_SANDYBRIDGE()
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@ -222,6 +227,7 @@ PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
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PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
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PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
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PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
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PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
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PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
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PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
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PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
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@ -259,6 +265,7 @@ PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
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PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
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PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
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PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
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PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
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PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
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PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
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PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
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@ -365,14 +372,14 @@ static struct pmc_op_getdyneventinfo soft_event_info;
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/* Event masks for events */
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struct pmc_masks {
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const char *pm_name;
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const uint32_t pm_value;
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const uint64_t pm_value;
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};
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#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
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#define NULLMASK { .pm_name = NULL }
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#if defined(__amd64__) || defined(__i386__)
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static int
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pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
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pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
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{
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const struct pmc_masks *pm;
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char *q, *r;
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@ -561,6 +568,8 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = {
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#define atom_aliases_without_iaf core2_aliases_without_iaf
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#define corei7_aliases core2_aliases
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#define corei7_aliases_without_iaf core2_aliases_without_iaf
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#define ivybridge_aliases core2_aliases
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#define ivybridge_aliases_without_iaf core2_aliases_without_iaf
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#define sandybridge_aliases core2_aliases
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#define sandybridge_aliases_without_iaf core2_aliases_without_iaf
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#define westmere_aliases core2_aliases
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@ -663,7 +672,7 @@ static struct pmc_masks iap_transition_mask[] = {
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NULLMASK
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};
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static struct pmc_masks iap_rsp_mask[] = {
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static struct pmc_masks iap_rsp_mask_i7_wm[] = {
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PMCMASK(DMND_DATA_RD, (1 << 0)),
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PMCMASK(DMND_RFO, (1 << 1)),
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PMCMASK(DMND_IFETCH, (1 << 2)),
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@ -682,12 +691,43 @@ static struct pmc_masks iap_rsp_mask[] = {
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NULLMASK
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};
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static struct pmc_masks iap_rsp_mask_sb_ib[] = {
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PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
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PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
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PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
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PMCMASK(REQ_WB, (1ULL << 3)),
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PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)),
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PMCMASK(REQ_PF_RFO, (1ULL << 5)),
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PMCMASK(REQ_PF_IFETCH, (1ULL << 6)),
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PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)),
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PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)),
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PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)),
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PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)),
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PMCMASK(REQ_STRM_ST, (1ULL << 11)),
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PMCMASK(REQ_OTHER, (1ULL << 15)),
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PMCMASK(RES_ANY, (1ULL << 16)),
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PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
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PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
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PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
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PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
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PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
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PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
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PMCMASK(RES_SNOOP_SNPI_NONE, (1ULL << 31)),
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PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
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PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
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PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
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PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
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PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
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PMCMASK(RES_NON_DRAM, (1ULL << 37)),
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NULLMASK
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};
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static int
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iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
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struct pmc_op_pmcallocate *pmc_config)
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{
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char *e, *p, *q;
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uint32_t cachestate, evmask, rsp;
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uint64_t cachestate, evmask, rsp;
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int count, n;
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pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
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@ -753,7 +793,13 @@ iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
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} else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
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cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
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if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
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n = pmc_parse_mask(iap_rsp_mask, p, &rsp);
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n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
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} else
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return (-1);
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} else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
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cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) {
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if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
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n = pmc_parse_mask(iap_rsp_mask_sb_ib, p, &rsp);
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} else
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return (-1);
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} else
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@ -1072,7 +1118,8 @@ k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
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{
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char *e, *p, *q;
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int n;
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uint32_t count, evmask;
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uint32_t count;
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uint64_t evmask;
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const struct pmc_masks *pm, *pmask;
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pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
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@ -1554,7 +1601,8 @@ p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
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char *e, *p, *q;
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int count, has_tag, has_busreqtype, n;
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uint32_t evmask, cccractivemask;
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uint32_t cccractivemask;
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uint64_t evmask;
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const struct pmc_masks *pm, *pmask;
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pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
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@ -1982,7 +2030,7 @@ p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
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struct pmc_op_pmcallocate *pmc_config)
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{
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char *e, *p, *q;
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uint32_t evmask;
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uint64_t evmask;
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int count, n;
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const struct pmc_masks *pm, *pmask;
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@ -2622,6 +2670,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
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ev = corei7_event_table;
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count = PMC_EVENT_TABLE_SIZE(corei7);
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break;
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case PMC_CPU_INTEL_IVYBRIDGE:
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ev = ivybridge_event_table;
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count = PMC_EVENT_TABLE_SIZE(ivybridge);
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break;
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case PMC_CPU_INTEL_SANDYBRIDGE:
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ev = sandybridge_event_table;
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count = PMC_EVENT_TABLE_SIZE(sandybridge);
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@ -2914,6 +2966,9 @@ pmc_init(void)
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pmc_class_table[n++] = &corei7uc_class_table_descr;
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PMC_MDEP_INIT_INTEL_V2(corei7);
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break;
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case PMC_CPU_INTEL_IVYBRIDGE:
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PMC_MDEP_INIT_INTEL_V2(ivybridge);
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break;
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case PMC_CPU_INTEL_SANDYBRIDGE:
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pmc_class_table[n++] = &ucf_class_table_descr;
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pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
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@ -3049,6 +3104,10 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
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ev = corei7_event_table;
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evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
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break;
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case PMC_CPU_INTEL_IVYBRIDGE:
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ev = ivybridge_event_table;
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evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
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break;
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case PMC_CPU_INTEL_SANDYBRIDGE:
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ev = sandybridge_event_table;
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evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
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lib/libpmc/pmc.ivybridge.3
Normal file
880
lib/libpmc/pmc.ivybridge.3
Normal file
@ -0,0 +1,880 @@
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.\" Copyright (c) 2012 Fabien Thomas. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd August 24, 2012
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.Dt PMC.IVYBRIDGE 3
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.Os
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.Sh NAME
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.Nm pmc.ivybridge
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.Nd measurement events for
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.Tn Intel
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.Tn Ivy Bridge
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn "Ivy Bridge"
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CPUs contain PMCs conforming to version 2 of the
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.Tn Intel
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performance measurement architecture.
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These CPUs may contain up to three classes of PMCs:
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.Bl -tag -width "Li PMC_CLASS_IAP"
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.It Li PMC_CLASS_IAF
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Fixed-function counters that count only one hardware event per counter.
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.It Li PMC_CLASS_IAP
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Programmable counters that may be configured to count one of a defined
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set of hardware events.
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.El
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.Pp
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The number of PMCs available in each class and their widths need to be
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determined at run time by calling
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.Xr pmc_cpuinfo 3 .
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.Pp
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Intel Ivy Bridge PMCs are documented in
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.Rs
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.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
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Intel(R) 64 and IA-32 Architectures Software Developers Manual"
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.%T "Volume 3B: System Programming Guide, Part 2"
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.%N "Order Number: 253669-043US"
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.%D May 2012
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.%Q "Intel Corporation"
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.Re
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.Ss IVYBRIDGE FIXED FUNCTION PMCS
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These PMCs and their supported events are documented in
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.Xr pmc.iaf 3 .
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.Ss IVYBRIDGE PROGRAMMABLE PMCS
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The programmable PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta Yes
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta Yes
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li rsp= Ns Ar value
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Configure the Off-core Response bits.
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.Bl -tag -width indent
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.It Li REQ_DMND_DATA_RD
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Counts the number of demand and DCU prefetch data reads of full and partial
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cachelines as well as demand data page table entry cacheline reads. Does not
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count L2 data read prefetches or instruction fetches.
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.It Li REQ_DMND_RFO
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Counts the number of demand and DCU prefetch reads for ownership (RFO)
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requests generated by a write to data cacheline. Does not count L2 RFO
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prefetches.
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.It Li REQ_DMND_IFETCH
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Counts the number of demand and DCU prefetch instruction cacheline reads.
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Does not count L2 code read prefetches.
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.It Li REQ_WB
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Counts the number of writeback (modified to exclusive) transactions.
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.It Li REQ_PF_DATA_RD
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Counts the number of data cacheline reads generated by L2 prefetchers.
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.It Li REQ_PF_RFO
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Counts the number of RFO requests generated by L2 prefetchers.
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.It Li REQ_PF_IFETCH
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Counts the number of code reads generated by L2 prefetchers.
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.It Li REQ_PF_LLC_DATA_RD
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L2 prefetcher to L3 for loads.
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.It Li REQ_PF_LLC_RFO
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RFO requests generated by L2 prefetcher
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.It Li REQ_PF_LLC_IFETCH
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L2 prefetcher to L3 for instruction fetches.
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.It Li REQ_BUS_LOCKS
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Bus lock and split lock requests.
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.It Li REQ_STRM_ST
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Streaming store requests.
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.It Li REQ_OTHER
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Any other request that crosses IDI, including I/O.
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.It Li RES_ANY
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Catch all value for any response types.
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.It Li RES_SUPPLIER_NO_SUPP
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No Supplier Information available.
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.It Li RES_SUPPLIER_LLC_HITM
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M-state initial lookup stat in L3.
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.It Li RES_SUPPLIER_LLC_HITE
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E-state.
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.It Li RES_SUPPLIER_LLC_HITS
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S-state.
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.It Li RES_SUPPLIER_LLC_HITF
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F-state.
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.It Li RES_SUPPLIER_LOCAL
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Local DRAM Controller.
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.It Li RES_SNOOP_SNPI_NONE
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No details on snoop-related information.
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.It Li RES_SNOOP_SNP_NO_NEEDED
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No snoop was needed to satisfy the request.
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.It Li RES_SNOOP_SNP_MISS
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A snoop was needed and it missed all snooped caches:
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-For LLC Hit, ReslHitl was returned by all cores
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-For LLC Miss, Rspl was returned by all sockets and data was returned from
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DRAM.
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.It Li RES_SNOOP_HIT_NO_FWD
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A snoop was needed and it hits in at least one snooped cache. Hit denotes a
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cache-line was valid before snoop effect. This includes:
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-Snoop Hit w/ Invalidation (LLC Hit, RFO)
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-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
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-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
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In the LLC Miss case, data is returned from DRAM.
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.It Li RES_SNOOP_HIT_FWD
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A snoop was needed and data was forwarded from a remote socket.
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This includes:
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-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
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.It Li RES_SNOOP_HITM
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A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
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cache-line was in modified state before effect as a results of snoop. This
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includes:
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-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
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-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
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-Snoop MtoS (LLC Hit, IFetch/Data_RD).
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.It Li RES_NON_DRAM
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Target was non-DRAM system address. This includes MMIO transactions.
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.El
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
|
||||
events measured in a cycle is greater than or equal to
|
||||
.Ar value .
|
||||
.It Li edge
|
||||
Configure the PMC to count the number of de-asserted to asserted
|
||||
transitions of the conditions expressed by the other qualifiers.
|
||||
If specified, the counter will increment only once whenever a
|
||||
condition becomes true, irrespective of the number of clocks during
|
||||
which the condition remains true.
|
||||
.It Li inv
|
||||
Invert the sense of comparison when the
|
||||
.Dq Li cmask
|
||||
qualifier is present, making the counter increment when the number of
|
||||
events per cycle is less than the value specified by the
|
||||
.Dq Li cmask
|
||||
qualifier.
|
||||
.It Li os
|
||||
Configure the PMC to count events happening at processor privilege
|
||||
level 0.
|
||||
.It Li usr
|
||||
Configure the PMC to count events occurring at privilege levels 1, 2
|
||||
or 3.
|
||||
.El
|
||||
.Pp
|
||||
If neither of the
|
||||
.Dq Li os
|
||||
or
|
||||
.Dq Li usr
|
||||
qualifiers are specified, the default is to enable both.
|
||||
.Ss Event Specifiers (Programmable PMCs)
|
||||
Ivy Bridge programmable PMCs support the following events:
|
||||
.Bl -tag -width indent
|
||||
.It Li LD_BLOCKS.STORE_FORWARD
|
||||
.Pq Event 03H , Umask 02H
|
||||
loads blocked by overlapping with store buffer that cannot be forwarded .
|
||||
.It Li MISALIGN_MEM_REF.LOADS
|
||||
.Pq Event 05H , Umask 01H
|
||||
Speculative cache-line split load uops dispatched to L1D.
|
||||
.It Li MISALIGN_MEM_REF.STORES
|
||||
.Pq Event 05H , Umask 02H
|
||||
Speculative cache-line split Store- address uops dispatched to L1D.
|
||||
.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
|
||||
.Pq Event 07H , Umask 01H
|
||||
False dependencies in MOB due to partial compare on address.
|
||||
.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK
|
||||
.Pq Event 08H , Umask 81H
|
||||
Misses in all TLB levels that cause a page walk of any page size from demand loads.
|
||||
.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED
|
||||
.Pq Event 08H , Umask 82H
|
||||
Misses in all TLB levels that caused page walk completed of any size by demand loads.
|
||||
.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION
|
||||
.Pq Event 08H , Umask 84H
|
||||
Cycle PMH is busy with a walk due to demand loads.
|
||||
.It Li UOPS_ISSUED.ANY
|
||||
.Pq Event 0EH , Umask 01H
|
||||
Increments each cycle the # of Uops issued by the RAT to RS.
|
||||
Set Cmask = 1, Inv = 1to count stalled cycles.
|
||||
Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
|
||||
.It Li UOPS_ISSUED.FLAGS_MERGE
|
||||
.Pq Event 0EH , Umask 10H
|
||||
Number of flags-merge uops allocated. Such uops adds delay.
|
||||
.It Li UOPS_ISSUED.SLOW_LEA
|
||||
.Pq Event 0EH , Umask 20H
|
||||
Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2
|
||||
sources + immediate) regardless if as a result of LEA instruction or not.
|
||||
.It Li UOPS_ISSUED.SINGLE_MUL
|
||||
.Pq Event 0EH , Umask 40H
|
||||
Number of multiply packed/scalar single precision uops allocated.
|
||||
.It Li ARITH.FPU_DIV_ACTIVE
|
||||
.Pq Event 14H , Umask 01H
|
||||
Cycles that the divider is active, includes INT and FP. Set 'edge =1,
|
||||
cmask=1' to count the number of divides.
|
||||
.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
|
||||
.Pq Event 24H , Umask 01H
|
||||
Demand Data Read requests that hit L2 cache.
|
||||
.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
|
||||
.Pq Event 24H , Umask 03H
|
||||
Counts any demand and L1 HW prefetch data load requests to L2.
|
||||
.It Li L2_RQSTS.RFO_HITS
|
||||
.Pq Event 24H , Umask 04H
|
||||
Counts the number of store RFO requests that hit the L2 cache.
|
||||
.It Li L2_RQSTS.RFO_MISS
|
||||
.Pq Event 24H , Umask 08H
|
||||
Counts the number of store RFO requests that miss the L2 cache.
|
||||
.It Li L2_RQSTS.ALL_RFO
|
||||
.Pq Event 24H , Umask 0CH
|
||||
Counts all L2 store RFO requests.
|
||||
.It Li L2_RQSTS.CODE_RD_HIT
|
||||
.Pq Event 24H , Umask 10H
|
||||
Number of instruction fetches that hit the L2 cache.
|
||||
.It Li L2_RQSTS.CODE_RD_MISS
|
||||
.Pq Event 24H , Umask 20H
|
||||
Number of instruction fetches that missed the L2 cache.
|
||||
.It Li L2_RQSTS.ALL_CODE_RD
|
||||
.Pq Event 24H , Umask 30H
|
||||
Counts all L2 code requests.
|
||||
.It Li L2_RQSTS.PF_HIT
|
||||
.Pq Event 24H , Umask 40H
|
||||
Counts all L2 HW prefetcher requests that hit L2.
|
||||
.It Li L2_RQSTS.PF_MISS
|
||||
.Pq Event 24H , Umask 80H
|
||||
Counts all L2 HW prefetcher requests that missed L2.
|
||||
.It Li L2_RQSTS.ALL_PF
|
||||
.Pq Event 24H , Umask C0H
|
||||
Counts all L2 HW prefetcher requests.
|
||||
.It Li L2_STORE_LOCK_RQSTS.MISS
|
||||
.Pq Event 27H , Umask 01H
|
||||
RFOs that miss cache lines.
|
||||
.It Li L2_STORE_LOCK_RQSTS.HIT_M
|
||||
.Pq Event 27H , Umask 08H
|
||||
RFOs that hit cache lines in M state.
|
||||
.It Li L2_STORE_LOCK_RQSTS.ALL
|
||||
.Pq Event 27H , Umask 0FH
|
||||
RFOs that access cache lines in any state.
|
||||
.It Li L2_L1D_WB_RQSTS.MISS
|
||||
.Pq Event 28H , Umask 01H
|
||||
Not rejected writebacks that missed LLC.
|
||||
.It Li L2_L1D_WB_RQSTS.HIT_E
|
||||
.Pq Event 28H , Umask 04H
|
||||
Not rejected writebacks from L1D to L2 cache lines in E state.
|
||||
.It Li L2_L1D_WB_RQSTS.HIT_M
|
||||
.Pq Event 28H , Umask 08H
|
||||
Not rejected writebacks from L1D to L2 cache lines in M state.
|
||||
.It Li L2_L1D_WB_RQSTS.ALL
|
||||
.Pq Event 28H , Umask 0FH
|
||||
Not rejected writebacks from L1D to L2 cache lines in any state.
|
||||
.It Li LONGEST_LAT_CACHE.REFERENCE
|
||||
.Pq Event 2EH , Umask 4FH
|
||||
This event counts requests originating from the core that reference a cache
|
||||
line in the last level cache.
|
||||
.It Li LONGEST_LAT_CACHE.MISS
|
||||
.Pq Event 2EH , Umask 41H
|
||||
This event counts each cache miss condition for references to the last level
|
||||
cache.
|
||||
.It Li CPU_CLK_UNHALTED.THREAD_P
|
||||
.Pq Event 3CH , Umask 00H
|
||||
Counts the number of thread cycles while the thread is not in a halt state.
|
||||
The thread enters the halt state when it is running the HLT instruction. The
|
||||
core frequency may change from time to time due to power or thermal
|
||||
throttling.
|
||||
.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
|
||||
.Pq Event 3CH , Umask 01H
|
||||
Increments at the frequency of XCLK (100 MHz) when not halted.
|
||||
.It Li L1D_PEND_MISS.PENDING
|
||||
.Pq Event 48H , Umask 01H
|
||||
Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1
|
||||
and Edge =1 to count occurrences.
|
||||
Counter 2 only.
|
||||
Set Cmask = 1 to count cycles.
|
||||
.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
|
||||
.Pq Event 49H , Umask 01H
|
||||
Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G).
|
||||
.It Li DTLB_STORE_MISSES.WALK_COMPLETED
|
||||
.Pq Event 49H , Umask 02H
|
||||
Miss in all TLB levels causes a page walk that completes of any page size
|
||||
(4K/2M/4M/1G).
|
||||
.It Li DTLB_STORE_MISSES.WALK_DURATION
|
||||
.Pq Event 49H , Umask 04H
|
||||
Cycles PMH is busy with this walk.
|
||||
.It Li DTLB_STORE_MISSES.STLB_HIT
|
||||
.Pq Event 49H , Umask 10H
|
||||
Store operations that miss the first TLB level but hit the second and do not
|
||||
cause page walks.
|
||||
.It Li LOAD_HIT_PRE.SW_PF
|
||||
.Pq Event 4CH , Umask 01H
|
||||
Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
|
||||
.It Li LOAD_HIT_PRE.HW_PF
|
||||
.Pq Event 4CH , Umask 02H
|
||||
Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
|
||||
.It Li L1D.REPLACEMENT
|
||||
.Pq Event 51H , Umask 01H
|
||||
Counts the number of lines brought into the L1 data cache.
|
||||
.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
|
||||
.Pq Event 58H , Umask 01H
|
||||
Number of integer Move Elimination candidate uops that were not eliminated.
|
||||
.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED
|
||||
.Pq Event 58H , Umask 02H
|
||||
Number of SIMD Move Elimination candidate uops that were not eliminated.
|
||||
.It Li MOVE_ELIMINATION.INT_ELIMINATED
|
||||
.Pq Event 58H , Umask 04H
|
||||
Number of integer Move Elimination candidate uops that were eliminated.
|
||||
.It Li MOVE_ELIMINATION.SIMD_ELIMINATED
|
||||
.Pq Event 58H , Umask 08H
|
||||
Number of SIMD Move Elimination candidate uops that were eliminated.
|
||||
.It Li CPL_CYCLES.RING0
|
||||
.Pq Event 5CH , Umask 01H
|
||||
Unhalted core cycles when the thread is in ring 0.
|
||||
Use Edge to count transition.
|
||||
.It Li CPL_CYCLES.RING123
|
||||
.Pq Event 5CH , Umask 02H
|
||||
Unhalted core cycles when the thread is not in ring 0.
|
||||
.It Li RS_EVENTS.EMPTY_CYCLES
|
||||
.Pq Event 5EH , Umask 01H
|
||||
Cycles the RS is empty for the thread.
|
||||
.It Li TLB_ACCESS.LOAD_STLB_HIT
|
||||
.Pq Event 5FH , Umask 01H
|
||||
Counts load operations that missed 1st level DTLB but hit the 2nd level.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
|
||||
.Pq Event 60H , Umask 01H
|
||||
Offcore outstanding Demand Data Read transactions in SQ to uncore. Set
|
||||
Cmask=1 to count cycles.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
|
||||
.Pq Event 60H , Umask 02H
|
||||
Offcore outstanding Demand Code Read transactions in SQ to uncore. Set
|
||||
Cmask=1 to count cycles.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
|
||||
.Pq Event 60H , Umask 04H
|
||||
Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to
|
||||
count cycles.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
|
||||
.Pq Event 60H , Umask 08H
|
||||
Offcore outstanding cacheable data read transactions in SQ to uncore. Set
|
||||
Cmask=1 to count cycles.
|
||||
.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
|
||||
.Pq Event 63H , Umask 01H
|
||||
Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
|
||||
.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
|
||||
.Pq Event 63H , Umask 02H
|
||||
Cycles in which the L1D is locked.
|
||||
.It Li IDQ.EMPTY
|
||||
.Pq Event 79H , Umask 02H
|
||||
Counts cycles the IDQ is empty.
|
||||
.It Li IDQ.MITE_UOPS
|
||||
.Pq Event 79H , Umask 04H
|
||||
Increment each cycle # of uops delivered to IDQ from MITE path.
|
||||
Can combine Umask 04H and 20H.
|
||||
Set Cmask = 1 to count cycles.
|
||||
.It Li IDQ.DSB_UOPS
|
||||
.Pq Event 79H , Umask 08H
|
||||
Increment each cycle. # of uops delivered to IDQ from DSB path.
|
||||
Can combine Umask 08H and 10H
|
||||
Set Cmask = 1 to count cycles.
|
||||
.It Li IDQ.MS_DSB_UOPS
|
||||
.Pq Event 79H , Umask 10H
|
||||
Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set
|
||||
Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.
|
||||
Can combine Umask 04H, 08H.
|
||||
.It Li IDQ.MS_MITE_UOPS
|
||||
.Pq Event 79H , Umask 20H
|
||||
Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set
|
||||
Cmask = 1 to count cycles.
|
||||
Can combine Umask 04H, 08H.
|
||||
.It Li IDQ.MS_UOPS
|
||||
.Pq Event 79H , Umask 30H
|
||||
Increment each cycle # of uops delivered to IDQ from MS by either DSB or
|
||||
MITE. Set Cmask = 1 to count cycles.
|
||||
Can combine Umask 04H, 08H.
|
||||
.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
|
||||
.Pq Event 79H , Umask 18H
|
||||
Counts cycles DSB is delivered at least one uops. Set Cmask = 1.
|
||||
.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
|
||||
.Pq Event 79H , Umask 18H
|
||||
Counts cycles DSB is delivered four uops. Set Cmask = 4.
|
||||
.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
|
||||
.Pq Event 79H , Umask 24H
|
||||
Counts cycles MITE is delivered at least one uops. Set Cmask = 1.
|
||||
.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
|
||||
.Pq Event 79H , Umask 24H
|
||||
Counts cycles MITE is delivered four uops. Set Cmask = 4.
|
||||
.It Li IDQ.MITE_ALL_UOPS
|
||||
.Pq Event 79H , Umask 3CH
|
||||
# of uops delivered to IDQ from any path.
|
||||
.It Li ICACHE.MISSES
|
||||
.Pq Event 80H , Umask 02H
|
||||
Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
|
||||
Includes UC accesses.
|
||||
.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
|
||||
.Pq Event 85H , Umask 01H
|
||||
Misses in all ITLB levels that cause page walks.
|
||||
.It Li ITLB_MISSES.WALK_COMPLETED
|
||||
.Pq Event 85H , Umask 02H
|
||||
Misses in all ITLB levels that cause completed page walks.
|
||||
.It Li ITLB_MISSES.WALK_DURATION
|
||||
.Pq Event 85H , Umask 04H
|
||||
Cycle PMH is busy with a walk.
|
||||
.It Li ITLB_MISSES.STLB_HIT
|
||||
.Pq Event 85H , Umask 10H
|
||||
Number of cache load STLB hits. No page walk.
|
||||
.It Li ILD_STALL.LCP
|
||||
.Pq Event 87H , Umask 01H
|
||||
Stalls caused by changing prefix length of the instruction.
|
||||
.It Li ILD_STALL.IQ_FULL
|
||||
.Pq Event 87H , Umask 04H
|
||||
Stall cycles due to IQ is full.
|
||||
.It Li BR_INST_EXEC.COND
|
||||
.Pq Event 88H , Umask 01H
|
||||
Qualify conditional near branch instructions executed, but not necessarily
|
||||
retired.
|
||||
Must combine with umask 40H, 80H.
|
||||
.It Li BR_INST_EXEC.DIRECT_JMP
|
||||
.Pq Event 88H , Umask 02H
|
||||
Qualify all unconditional near branch instructions excluding calls and
|
||||
indirect branches.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 88H , Umask 04H
|
||||
Qualify executed indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.RETURN_NEAR
|
||||
.Pq Event 88H , Umask 08H
|
||||
Qualify indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 10H
|
||||
Qualify unconditional near call branch instructions, excluding non call
|
||||
branch, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 20H
|
||||
Qualify indirect near calls, including both register and memory indirect,
|
||||
executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.NONTAKEN
|
||||
.Pq Event 88H , Umask 40H
|
||||
Qualify non-taken near branches executed.
|
||||
Applicable to umask 01H only.
|
||||
.It Li BR_INST_EXEC.TAKEN
|
||||
.Pq Event 88H , Umask 80H
|
||||
Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H,
|
||||
10H, 20H.
|
||||
.It Li BR_INST_EXEC.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li BR_MISP_EXEC.COND
|
||||
.Pq Event 89H , Umask 01H
|
||||
Qualify conditional near branch instructions mispredicted.
|
||||
Must combine with umask 40H, 80H.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 89H , Umask 04H
|
||||
Qualify mispredicted indirect near branch instructions that are not calls
|
||||
nor returns.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.RETURN_NEAR
|
||||
.Pq Event 89H , Umask 08H
|
||||
Qualify mispredicted indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 10H
|
||||
Qualify mispredicted unconditional near call branch instructions, excluding
|
||||
non call branch, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 20H
|
||||
Qualify mispredicted indirect near calls, including both register and memory
|
||||
indirect, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.NONTAKEN
|
||||
.Pq Event 89H , Umask 40H
|
||||
Qualify mispredicted non-taken near branches executed.
|
||||
Applicable to umask 01H only.
|
||||
.It Li BR_MISP_EXEC.TAKEN
|
||||
.Pq Event 89H , Umask 80H
|
||||
Qualify mispredicted taken near branches executed. Must combine with
|
||||
01H,02H, 04H, 08H, 10H, 20H.
|
||||
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
||||
.Pq Event 89H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
||||
.Pq Event 9CH , Umask 01H
|
||||
Count number of non-delivered uops to RAT per thread.
|
||||
Use Cmask to qualify uop b/w.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_0
|
||||
.Pq Event A1H , Umask 01H
|
||||
Cycles which a Uop is dispatched on port 0.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_1
|
||||
.Pq Event A1H , Umask 02H
|
||||
Cycles which a Uop is dispatched on port 1.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
|
||||
.Pq Event A1H , Umask 04H
|
||||
Cycles which a load uop is dispatched on port 2.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
|
||||
.Pq Event A1H , Umask 08H
|
||||
Cycles which a store address uop is dispatched on port 2.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_2
|
||||
.Pq Event A1H , Umask 0CH
|
||||
Cycles which a Uop is dispatched on port 2.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
|
||||
.Pq Event A1H , Umask 10H
|
||||
Cycles which a load uop is dispatched on port 3.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
|
||||
.Pq Event A1H , Umask 20H
|
||||
Cycles which a store address uop is dispatched on port 3.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_3
|
||||
.Pq Event A1H , Umask 30H
|
||||
Cycles which a Uop is dispatched on port 3.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_4
|
||||
.Pq Event A1H , Umask 40H
|
||||
Cycles which a Uop is dispatched on port 4.
|
||||
.It Li UOPS_DISPATCHED_PORT.PORT_5
|
||||
.Pq Event A1H , Umask 80H
|
||||
Cycles which a Uop is dispatched on port 5.
|
||||
.It Li RESOURCE_STALLS.ANY
|
||||
.Pq Event A2H , Umask 01H
|
||||
Cycles Allocation is stalled due to Resource Related reason.
|
||||
.It Li RESOURCE_STALLS.RS
|
||||
.Pq Event A2H , Umask 04H
|
||||
Cycles stalled due to no eligible RS entry available.
|
||||
.It Li RESOURCE_STALLS.SB
|
||||
.Pq Event A2H , Umask 08H
|
||||
Cycles stalled due to no store buffers available. (not including draining
|
||||
form sync).
|
||||
.It Li RESOURCE_STALLS.ROB
|
||||
.Pq Event A2H , Umask 10H
|
||||
Cycles stalled due to re-order buffer full.
|
||||
.It Li DSB2MITE_SWITCHES.COUNT
|
||||
.Pq Event ABH , Umask 01H
|
||||
Number of DSB to MITE switches.
|
||||
.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
|
||||
.Pq Event ABH , Umask 02H
|
||||
Cycles DSB to MITE switches caused delay.
|
||||
.It Li DSB_FILL.EXCEED_DSB_LINES
|
||||
.Pq Event ACH , Umask 08H
|
||||
DSB Fill encountered > 3 DSB lines.
|
||||
.It Li ITLB.ITLB_FLUSH
|
||||
.Pq Event AEH , Umask 01H
|
||||
Counts the number of ITLB flushes, includes 4k/2M/4M pages.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
|
||||
.Pq Event B0H , Umask 01H
|
||||
Demand data read requests sent to uncore.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
|
||||
.Pq Event B0H , Umask 02H
|
||||
Demand code read requests sent to uncore.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND_RFO
|
||||
.Pq Event B0H , Umask 04H
|
||||
Demand RFO read requests sent to uncore, including regular RFOs, locks,
|
||||
ItoM.
|
||||
.It Li OFFCORE_REQUESTS.ALL_DATA_RD
|
||||
.Pq Event B0H , Umask 08H
|
||||
Data read requests sent to uncore (demand and prefetch).
|
||||
.It Li UOPS_EXECUTED.THREAD
|
||||
.Pq Event B1H , Umask 01H
|
||||
Counts total number of uops to be executed per-thread each cycle. Set Cmask
|
||||
= 1, INV =1 to count stall cycles.
|
||||
.It Li UOPS_EXECUTED.CORE
|
||||
.Pq Event B1H , Umask 02H
|
||||
Counts total number of uops to be executed per-core each cycle.
|
||||
Do not need to set ANY.
|
||||
.It Li OFF_CORE_RESPONSE_0
|
||||
.Pq Event B7H , Umask 01H
|
||||
Off-core Response Performance Monitoring.
|
||||
PMC0 only.
|
||||
Requires programming MSR 01A6H.
|
||||
.It Li OFF_CORE_RESPONSE_1
|
||||
.Pq Event BBH , Umask 01H
|
||||
Off-core Response Performance Monitoring.
|
||||
PMC3 only.
|
||||
Requires programming MSR 01A7H.
|
||||
.It Li TLB_FLUSH.DTLB_THREAD
|
||||
.Pq Event BDH , Umask 01H
|
||||
DTLB flush attempts of the thread- specific entries.
|
||||
.It Li TLB_FLUSH.STLB_ANY
|
||||
.Pq Event BDH , Umask 20H
|
||||
Count number of STLB flush attempts.
|
||||
.It Li INST_RETIRED.ANY_P
|
||||
.Pq Event C0H , Umask 00H
|
||||
Number of instructions at retirement.
|
||||
.It Li INST_RETIRED.ALL
|
||||
.Pq Event C0H , Umask 01H
|
||||
Precise instruction retired event with HW to reduce effect of PEBS shadow in
|
||||
IP distribution.
|
||||
PMC1 only.
|
||||
Must quiesce other PMCs.
|
||||
.It Li OTHER_ASSISTS.AVX_STORE
|
||||
.Pq Event C1H , Umask 08H
|
||||
Number of assists associated with 256-bit AVX store operations.
|
||||
.It Li OTHER_ASSISTS.AVX_TO_SSE
|
||||
.Pq Event C1H , Umask 10H
|
||||
Number of transitions from AVX- 256 to legacy SSE when penalty applicable.
|
||||
.It Li OTHER_ASSISTS.SSE_TO_AVX
|
||||
.Pq Event C1H , Umask 20H
|
||||
Number of transitions from SSE to AVX-256 when penalty applicable.
|
||||
.It Li UOPS_RETIRED.ALL
|
||||
.Pq Event C2H , Umask 01H
|
||||
Counts the number of micro-ops retired, Use cmask=1 and invert to count
|
||||
active cycles or stalled cycles.
|
||||
Supports PEBS, use Any=1 for core granular.
|
||||
.It Li UOPS_RETIRED.RETIRE_SLOTS
|
||||
.Pq Event C2H , Umask 02H
|
||||
Counts the number of retirement slots used each cycle.
|
||||
.It Li MACHINE_CLEARS.MEMORY_ORDERING
|
||||
.Pq Event C3H , Umask 02H
|
||||
Counts the number of machine clears due to memory order conflicts.
|
||||
.It Li MACHINE_CLEARS.SMC
|
||||
.Pq Event C3H , Umask 04H
|
||||
Number of self-modifying-code machine clears detected.
|
||||
.It Li MACHINE_CLEARS.MASKMOV
|
||||
.Pq Event C3H , Umask 20H
|
||||
Counts the number of executed AVX masked load operations that refer to an
|
||||
illegal address range with the mask bits set to 0.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C4H , Umask 00H
|
||||
Branch instructions at retirement.
|
||||
.It Li BR_INST_RETIRED.CONDITIONAL
|
||||
.Pq Event C4H , Umask 01H
|
||||
Counts the number of conditional branch instructions retired.
|
||||
Supports PEBS.
|
||||
.It Li BR_INST_RETIRED.NEAR_CALL
|
||||
.Pq Event C4H , Umask 02H
|
||||
Direct and indirect near call instructions retired.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C4H , Umask 04H
|
||||
Counts the number of branch instructions retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_RETURN
|
||||
.Pq Event C4H , Umask 08H
|
||||
Counts the number of near return instructions retired.
|
||||
.It Li BR_INST_RETIRED.NOT_TAKEN
|
||||
.Pq Event C4H , Umask 10H
|
||||
Counts the number of not taken branch instructions retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_TAKEN
|
||||
.Pq Event C4H , Umask 20H
|
||||
Number of near taken branches retired.
|
||||
.It Li BR_INST_RETIRED.FAR_BRANCH
|
||||
.Pq Event C4H , Umask 40H
|
||||
Number of far branches retired.
|
||||
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C5H , Umask 00H
|
||||
Mispredicted branch instructions at retirement.
|
||||
.It Li BR_MISP_RETIRED.CONDITIONAL
|
||||
.Pq Event C5H , Umask 01H
|
||||
Mispredicted conditional branch instructions retired.
|
||||
Supports PEBS.
|
||||
.It Li BR_MISP_RETIRED.NEAR_CALL
|
||||
.Pq Event C5H , Umask 02H
|
||||
Direct and indirect mispredicted near call instructions retired.
|
||||
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C5H , Umask 04H
|
||||
Mispredicted macro branch instructions retired.
|
||||
.It Li BR_MISP_RETIRED.NOT_TAKEN
|
||||
.Pq Event C5H , Umask 10H
|
||||
Mispredicted not taken branch instructions retired.
|
||||
.It Li BR_MISP_RETIRED.TAKEN
|
||||
.Pq Event C5H , Umask 20H
|
||||
Mispredicted taken branch instructions retired.
|
||||
.It Li FP_ASSIST.X87_OUTPUT
|
||||
.Pq Event CAH , Umask 02H
|
||||
Number of X87 FP assists due to Output values.
|
||||
.It Li FP_ASSIST.X87_INPUT
|
||||
.Pq Event CAH , Umask 04H
|
||||
Number of X87 FP assists due to input values.
|
||||
.It Li FP_ASSIST.SIMD_OUTPUT
|
||||
.Pq Event CAH , Umask 08H
|
||||
Number of SIMD FP assists due to Output values.
|
||||
.It Li FP_ASSIST.SIMD_INPUT
|
||||
.Pq Event CAH , Umask 10H
|
||||
Number of SIMD FP assists due to input values.
|
||||
.It Li FP_ASSIST.ANY
|
||||
.Pq Event CAH , Umask 1EH
|
||||
Cycles with any input/output SSE* or FP assists.
|
||||
.It Li ROB_MISC_EVENTS.LBR_INSERTS
|
||||
.Pq Event CCH , Umask 20H
|
||||
Count cases of saving new LBR records by hardware.
|
||||
.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
|
||||
.Pq Event CDH , Umask 01H
|
||||
Sample loads with specified latency threshold.
|
||||
PMC3 only.
|
||||
Specify threshold in MSR 0x3F6.
|
||||
.It Li MEM_TRANS_RETIRED.PRECISE_STORE
|
||||
.Pq Event CDH , Umask 02H
|
||||
Sample stores and collect precise store operation via PEBS record.
|
||||
PMC3 only.
|
||||
.It Li MEM_UOP_RETIRED.LOADS
|
||||
.Pq Event D0H , Umask 01H
|
||||
Qualify retired memory uops that are loads. Combine with umask 10H, 20H,
|
||||
40H, 80H.
|
||||
Supports PEBS.
|
||||
.It Li MEM_UOP_RETIRED.STORES
|
||||
.Pq Event D0H , Umask 02H
|
||||
Qualify retired memory uops that are stores. Combine with umask 10H, 20H,
|
||||
40H, 80H.
|
||||
.It Li MEM_UOP_RETIRED.STLB_MISS
|
||||
.Pq Event D0H , Umask 10H
|
||||
Qualify retired memory uops with STLB miss. Must combine with umask 01H,
|
||||
02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.LOCK
|
||||
.Pq Event D0H , Umask 20H
|
||||
Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to
|
||||
produce counts.
|
||||
.It Li MEM_UOP_RETIRED.SPLIT
|
||||
.Pq Event D0H , Umask 40H
|
||||
Qualify retired memory uops with line split. Must combine with umask 01H,
|
||||
02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.ALL
|
||||
.Pq Event D0H , Umask 80H
|
||||
Qualify any retired memory uops. Must combine with umask 01H, 02H, to
|
||||
produce counts.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.Pq Event D1H , Umask 01H
|
||||
Retired load uops with L1 cache hits as data sources.
|
||||
Supports PEBS.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
|
||||
.Pq Event D1H , Umask 02H
|
||||
Retired load uops with L2 cache hits as data sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
||||
.Pq Event D1H , Umask 04H
|
||||
Retired load uops with LLC cache hits as data sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
|
||||
.Pq Event D1H , Umask 40H
|
||||
Retired load uops which data sources were load uops missed L1 but hit FB due
|
||||
to preceding miss to the same cache line with data not ready.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
|
||||
.Pq Event D2H , Umask 01H
|
||||
Retired load uops which data sources were LLC hit and cross-core snoop
|
||||
missed in on-pkg core cache.
|
||||
Supports PEBS.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
|
||||
.Pq Event D2H , Umask 02H
|
||||
Retired load uops which data sources were LLC and cross-core snoop hits in
|
||||
on-pkg core cache.
|
||||
Supports PEBS.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
|
||||
.Pq Event D2H , Umask 04H
|
||||
Retired load uops which data sources were HitM responses from shared LLC.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
|
||||
.Pq Event D2H , Umask 08H
|
||||
Retired load uops which data sources were hits in LLC without snoops
|
||||
required.
|
||||
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
|
||||
.Pq Event D3H , Umask 01H
|
||||
Retired load uops which data sources missed LLC but serviced from local
|
||||
dram.
|
||||
Supports PEBS.
|
||||
.It Li L2_TRANS.DEMAND_DATA_RD
|
||||
.Pq Event F0H , Umask 01H
|
||||
Demand Data Read requests that access L2 cache.
|
||||
.It Li L2_TRANS.RFO
|
||||
.Pq Event F0H , Umask 02H
|
||||
RFO requests that access L2 cache.
|
||||
.It Li L2_TRANS.CODE_RD
|
||||
.Pq Event F0H , Umask 04H
|
||||
L2 cache accesses when fetching instructions.
|
||||
.It Li L2_TRANS.ALL_PF
|
||||
.Pq Event F0H , Umask 08H
|
||||
Any MLC or LLC HW prefetch accessing L2, including rejects.
|
||||
.It Li L2_TRANS.L1D_WB
|
||||
.Pq Event F0H , Umask 10H
|
||||
L1D writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.L2_FILL
|
||||
.Pq Event F0H , Umask 20H
|
||||
L2 fill requests that access L2 cache.
|
||||
.It Li L2_TRANS.L2_WB
|
||||
.Pq Event F0H , Umask 40H
|
||||
L2 writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.ALL_REQUESTS
|
||||
.Pq Event F0H , Umask 80H
|
||||
Transactions accessing L2 pipe.
|
||||
.It Li L2_LINES_IN.I
|
||||
.Pq Event F1H , Umask 01H
|
||||
L2 cache lines in I state filling L2.
|
||||
Counting does not cover rejects.
|
||||
.It Li L2_LINES_IN.S
|
||||
.Pq Event F1H , Umask 02H
|
||||
L2 cache lines in S state filling L2.
|
||||
Counting does not cover rejects.
|
||||
.It Li L2_LINES_IN.E
|
||||
.Pq Event F1H , Umask 04H
|
||||
L2 cache lines in E state filling L2.
|
||||
Counting does not cover rejects.
|
||||
.It Li L2_LINES_IN.ALL
|
||||
.Pq Event F1H , Umask 07H
|
||||
L2 cache lines filling L2.
|
||||
Counting does not cover rejects.
|
||||
.It Li L2_LINES_OUT.DEMAND_CLEAN
|
||||
.Pq Event F2H , Umask 01H
|
||||
Clean L2 cache lines evicted by demand.
|
||||
.It Li L2_LINES_OUT.DEMAND_DIRTY
|
||||
.Pq Event F2H , Umask 02H
|
||||
Dirty L2 cache lines evicted by demand.
|
||||
.It Li L2_LINES_OUT.PF_CLEAN
|
||||
.Pq Event F2H , Umask 04H
|
||||
Clean L2 cache lines evicted by the MLC prefetcher.
|
||||
.It Li L2_LINES_OUT.PF_DIRTY
|
||||
.Pq Event F2H , Umask 08H
|
||||
Dirty L2 cache lines evicted by the MLC prefetcher.
|
||||
.El
|
||||
.Sh SEE ALSO
|
||||
.Xr pmc 3 ,
|
||||
.Xr pmc.atom 3 ,
|
||||
.Xr pmc.core 3 ,
|
||||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.ucf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.corei7 3 ,
|
||||
.Xr pmc.corei7uc 3 ,
|
||||
.Xr pmc.sandybridge 3 ,
|
||||
.Xr pmc.sandybridgeuc 3 ,
|
||||
.Xr pmc.westmere 3 ,
|
||||
.Xr pmc.westmereuc 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc_cpuinfo 3 ,
|
||||
.Xr pmclog 3 ,
|
||||
.Xr hwpmc 4
|
||||
.Sh HISTORY
|
||||
The
|
||||
.Nm pmc
|
||||
library first appeared in
|
||||
.Fx 6.0 .
|
||||
.Sh AUTHORS
|
||||
The
|
||||
.Lb libpmc
|
||||
library was written by
|
||||
.An "Joseph Koshy"
|
||||
.Aq jkoshy@FreeBSD.org .
|
||||
The support for the Ivy Bridge
|
||||
microarchitecture was written by
|
||||
.An "Fabien Thomas"
|
||||
.Aq fabient@FreeBSD.org .
|
@ -93,55 +93,80 @@ qualifiers:
|
||||
.It Li rsp= Ns Ar value
|
||||
Configure the Off-core Response bits.
|
||||
.Bl -tag -width indent
|
||||
.It Li DMND_DATA_RD
|
||||
Counts the number of demand and DCU prefetch data reads of full
|
||||
and partial cachelines as well as demand data page table entry
|
||||
cacheline reads.
|
||||
Does not count L2 data read prefetches or instruction fetches.
|
||||
.It Li DMND_RFO
|
||||
Counts the number of demand and DCU prefetch reads for ownership
|
||||
(RFO) requests generated by a write to data cacheline.
|
||||
Does not count L2 RFO.
|
||||
.It Li DMND_IFETCH
|
||||
Counts the number of demand and DCU prefetch instruction cacheline
|
||||
reads.
|
||||
.It Li REQ_DMND_DATA_RD
|
||||
Counts the number of demand and DCU prefetch data reads of full and partial
|
||||
cachelines as well as demand data page table entry cacheline reads. Does not
|
||||
count L2 data read prefetches or instruction fetches.
|
||||
.It Li REQ_DMND_RFO
|
||||
Counts the number of demand and DCU prefetch reads for ownership (RFO)
|
||||
requests generated by a write to data cacheline. Does not count L2 RFO
|
||||
prefetches.
|
||||
.It Li REQ_DMND_IFETCH
|
||||
Counts the number of demand and DCU prefetch instruction cacheline reads.
|
||||
Does not count L2 code read prefetches.
|
||||
.It Li WB
|
||||
.It Li REQ_WB
|
||||
Counts the number of writeback (modified to exclusive) transactions.
|
||||
.It Li PF_DATA_RD
|
||||
.It Li REQ_PF_DATA_RD
|
||||
Counts the number of data cacheline reads generated by L2 prefetchers.
|
||||
.It Li PF_RFO
|
||||
.It Li REQ_PF_RFO
|
||||
Counts the number of RFO requests generated by L2 prefetchers.
|
||||
.It Li PF_IFETCH
|
||||
.It Li REQ_PF_IFETCH
|
||||
Counts the number of code reads generated by L2 prefetchers.
|
||||
.It Li OTHER
|
||||
Counts one of the following transaction types, including L3 invalidate,
|
||||
I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
|
||||
lock, unlock, split lock.
|
||||
.It Li UNCORE_HIT
|
||||
L3 Hit: local or remote home requests that hit L3 cache in the uncore
|
||||
with no coherency actions required (snooping).
|
||||
.It Li OTHER_CORE_HIT_SNP
|
||||
L3 Hit: local or remote home requests that hit L3 cache in the uncore
|
||||
and was serviced by another core with a cross core snoop where no modified
|
||||
copies were found (clean).
|
||||
.It Li OTHER_CORE_HITM
|
||||
L3 Hit: local or remote home requests that hit L3 cache in the uncore
|
||||
and was serviced by another core with a cross core snoop where modified
|
||||
copies were found (HITM).
|
||||
.It Li REMOTE_CACHE_FWD
|
||||
L3 Miss: local homed requests that missed the L3 cache and was serviced
|
||||
by forwarded data following a cross package snoop where no modified
|
||||
copies found.
|
||||
(Remote home requests are not counted)
|
||||
.It Li REMOTE_DRAM
|
||||
L3 Miss: remote home requests that missed the L3 cache and were serviced
|
||||
by remote DRAM.
|
||||
.It Li LOCAL_DRAM
|
||||
L3 Miss: local home requests that missed the L3 cache and were serviced
|
||||
by local DRAM.
|
||||
.It Li NON_DRAM
|
||||
Non-DRAM requests that were serviced by IOH.
|
||||
.It Li REQ_PF_LLC_DATA_RD
|
||||
L2 prefetcher to L3 for loads.
|
||||
.It Li REQ_PF_LLC_RFO
|
||||
RFO requests generated by L2 prefetcher
|
||||
.It Li REQ_PF_LLC_IFETCH
|
||||
L2 prefetcher to L3 for instruction fetches.
|
||||
.It Li REQ_BUS_LOCKS
|
||||
Bus lock and split lock requests.
|
||||
.It Li REQ_STRM_ST
|
||||
Streaming store requests.
|
||||
.It Li REQ_OTHER
|
||||
Any other request that crosses IDI, including I/O.
|
||||
.It Li RES_ANY
|
||||
Catch all value for any response types.
|
||||
.It Li RES_SUPPLIER_NO_SUPP
|
||||
No Supplier Information available.
|
||||
.It Li RES_SUPPLIER_LLC_HITM
|
||||
M-state initial lookup stat in L3.
|
||||
.It Li RES_SUPPLIER_LLC_HITE
|
||||
E-state.
|
||||
.It Li RES_SUPPLIER_LLC_HITS
|
||||
S-state.
|
||||
.It Li RES_SUPPLIER_LLC_HITF
|
||||
F-state.
|
||||
.It Li RES_SUPPLIER_LOCAL
|
||||
Local DRAM Controller.
|
||||
.It Li RES_SNOOP_SNPI_NONE
|
||||
No details on snoop-related information.
|
||||
.It Li RES_SNOOP_SNP_NO_NEEDED
|
||||
No snoop was needed to satisfy the request.
|
||||
.It Li RES_SNOOP_SNP_MISS
|
||||
A snoop was needed and it missed all snooped caches:
|
||||
-For LLC Hit, ReslHitl was returned by all cores
|
||||
-For LLC Miss, Rspl was returned by all sockets and data was returned from
|
||||
DRAM.
|
||||
.It Li RES_SNOOP_HIT_NO_FWD
|
||||
A snoop was needed and it hits in at least one snooped cache. Hit denotes a
|
||||
cache-line was valid before snoop effect. This includes:
|
||||
-Snoop Hit w/ Invalidation (LLC Hit, RFO)
|
||||
-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
|
||||
-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
|
||||
In the LLC Miss case, data is returned from DRAM.
|
||||
.It Li RES_SNOOP_HIT_FWD
|
||||
A snoop was needed and data was forwarded from a remote socket.
|
||||
This includes:
|
||||
-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
|
||||
.It Li RES_SNOOP_HITM
|
||||
A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
|
||||
cache-line was in modified state before effect as a results of snoop. This
|
||||
includes:
|
||||
-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
|
||||
-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
|
||||
-Snoop MtoS (LLC Hit, IFetch/Data_RD).
|
||||
.It Li RES_NON_DRAM
|
||||
Target was non-DRAM system address. This includes MMIO transactions.
|
||||
.El
|
||||
.It Li cmask= Ns Ar value
|
||||
Configure the PMC to increment only if the number of configured
|
||||
|
@ -547,7 +547,7 @@ struct iap_event_descr {
|
||||
enum pmc_event iap_ev;
|
||||
unsigned char iap_evcode;
|
||||
unsigned char iap_umask;
|
||||
unsigned char iap_flags;
|
||||
unsigned int iap_flags;
|
||||
};
|
||||
|
||||
#define IAP_F_CC (1 << 0) /* CPU: Core */
|
||||
@ -557,8 +557,9 @@ struct iap_event_descr {
|
||||
#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
|
||||
#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
|
||||
#define IAP_F_WM (1 << 5) /* CPU: Westmere */
|
||||
#define IAP_F_SB (1 << 6) /* CPU: Sandy Brdige */
|
||||
#define IAP_F_FM (1 << 7) /* Fixed mask */
|
||||
#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */
|
||||
#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */
|
||||
#define IAP_F_FM (1 << 8) /* Fixed mask */
|
||||
|
||||
#define IAP_F_ALLCPUSCORE2 \
|
||||
(IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
|
||||
@ -600,7 +601,7 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
|
||||
IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
|
||||
IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
|
||||
IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
|
||||
@ -613,8 +614,8 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
|
||||
IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
|
||||
IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
|
||||
|
||||
IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
|
||||
@ -627,7 +628,7 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
|
||||
IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
|
||||
@ -648,6 +649,9 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O),
|
||||
IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7),
|
||||
IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB),
|
||||
|
||||
IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
|
||||
IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
|
||||
@ -666,8 +670,11 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB),
|
||||
|
||||
IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB),
|
||||
|
||||
IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
|
||||
IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
@ -712,7 +719,7 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
|
||||
IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
|
||||
IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
@ -737,18 +744,18 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
|
||||
|
||||
IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
@ -768,12 +775,12 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
|
||||
IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
@ -782,11 +789,11 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB),
|
||||
IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB),
|
||||
|
||||
IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
|
||||
IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
|
||||
@ -799,9 +806,9 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
|
||||
IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
|
||||
IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
|
||||
IAP_F_ALLCPUSCORE2),
|
||||
@ -814,9 +821,9 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
|
||||
IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
|
||||
IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
|
||||
@ -857,17 +864,17 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
|
||||
IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
|
||||
|
||||
IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7),
|
||||
IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O),
|
||||
IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7),
|
||||
@ -880,8 +887,8 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
|
||||
|
||||
@ -898,7 +905,7 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
|
||||
|
||||
IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
@ -910,6 +917,11 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB),
|
||||
|
||||
IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB),
|
||||
@ -919,19 +931,21 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB),
|
||||
|
||||
IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB),
|
||||
|
||||
IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB),
|
||||
IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
@ -943,9 +957,9 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
|
||||
IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
|
||||
@ -986,12 +1000,15 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
|
||||
IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
|
||||
|
||||
IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB),
|
||||
IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB),
|
||||
|
||||
IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
|
||||
|
||||
@ -1007,7 +1024,7 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
|
||||
IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
|
||||
IAP_F_WM),
|
||||
IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
@ -1028,12 +1045,12 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O),
|
||||
IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O),
|
||||
IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
|
||||
@ -1042,53 +1059,53 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
@ -1103,40 +1120,40 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
|
||||
IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
|
||||
IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
@ -1154,25 +1171,25 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
|
||||
|
||||
IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB),
|
||||
|
||||
IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB),
|
||||
IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
|
||||
IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
|
||||
IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
@ -1180,9 +1197,9 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
@ -1219,7 +1236,7 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
|
||||
IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
@ -1229,17 +1246,17 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
|
||||
|
||||
IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB),
|
||||
|
||||
IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
@ -1249,16 +1266,16 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
|
||||
IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
@ -1270,36 +1287,36 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
|
||||
IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
|
||||
IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
@ -1326,13 +1343,13 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM),
|
||||
@ -1353,44 +1370,46 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
|
||||
|
||||
IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB),
|
||||
IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB),
|
||||
IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
|
||||
|
||||
IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB),
|
||||
|
||||
IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
|
||||
@ -1457,38 +1476,38 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
|
||||
IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB),
|
||||
IAP_F_SB | IAP_F_IB),
|
||||
IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB),
|
||||
IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
@ -1685,7 +1704,7 @@ iap_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri)
|
||||
* Events valid only on counter 2.
|
||||
*/
|
||||
case PMC_EV_IAP_EVENT_48H_01H:
|
||||
mask = 0x2;
|
||||
mask = 0x4;
|
||||
break;
|
||||
default:
|
||||
mask = ~0; /* Any row index is ok. */
|
||||
@ -1694,6 +1713,25 @@ iap_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri)
|
||||
return (mask & (1 << ri));
|
||||
}
|
||||
|
||||
static int
|
||||
iap_event_ivybridge_ok_on_counter(enum pmc_event pe, int ri)
|
||||
{
|
||||
uint32_t mask;
|
||||
|
||||
switch (pe) {
|
||||
/*
|
||||
* Events valid only on counter 2.
|
||||
*/
|
||||
case PMC_EV_IAP_EVENT_48H_01H:
|
||||
mask = 0x4;
|
||||
break;
|
||||
default:
|
||||
mask = ~0; /* Any row index is ok. */
|
||||
}
|
||||
|
||||
return (mask & (1 << ri));
|
||||
}
|
||||
|
||||
static int
|
||||
iap_event_ok_on_counter(enum pmc_event pe, int ri)
|
||||
{
|
||||
@ -1770,6 +1808,10 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
|
||||
if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
|
||||
return (EINVAL);
|
||||
break;
|
||||
case PMC_CPU_INTEL_IVYBRIDGE:
|
||||
if (iap_event_ivybridge_ok_on_counter(ev, ri) == 0)
|
||||
return (EINVAL);
|
||||
break;
|
||||
case PMC_CPU_INTEL_SANDYBRIDGE:
|
||||
if (iap_event_sandybridge_ok_on_counter(ev, ri) == 0)
|
||||
return (EINVAL);
|
||||
@ -1805,6 +1847,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
|
||||
case PMC_CPU_INTEL_COREI7:
|
||||
cpuflag = IAP_F_I7;
|
||||
break;
|
||||
case PMC_CPU_INTEL_IVYBRIDGE:
|
||||
cpuflag = IAP_F_IB;
|
||||
break;
|
||||
case PMC_CPU_INTEL_SANDYBRIDGE:
|
||||
cpuflag = IAP_F_SB;
|
||||
break;
|
||||
@ -1910,10 +1955,15 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
|
||||
if (core_cputype == PMC_CPU_INTEL_COREI7 &&
|
||||
ev == PMC_EV_IAP_EVENT_BBH_01H)
|
||||
return (EINVAL);
|
||||
if (a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK)
|
||||
if ((core_cputype == PMC_CPU_INTEL_COREI7 ||
|
||||
core_cputype == PMC_CPU_INTEL_WESTMERE) &&
|
||||
a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
|
||||
return (EINVAL);
|
||||
pm->pm_md.pm_iap.pm_iap_rsp =
|
||||
a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK;
|
||||
else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
|
||||
core_cputype == PMC_CPU_INTEL_IVYBRIDGE) &&
|
||||
a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB)
|
||||
return (EINVAL);
|
||||
pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp;
|
||||
}
|
||||
|
||||
if (caps & PMC_CAP_THRESHOLD)
|
||||
|
@ -46,7 +46,7 @@ struct pmc_md_iaf_op_pmcallocate {
|
||||
*/
|
||||
struct pmc_md_iap_op_pmcallocate {
|
||||
uint32_t pm_iap_config;
|
||||
uint32_t pm_iap_rsp;
|
||||
uint64_t pm_iap_rsp;
|
||||
};
|
||||
|
||||
#define IAP_EVSEL(C) ((C) & 0xFF)
|
||||
@ -60,7 +60,8 @@ struct pmc_md_iap_op_pmcallocate {
|
||||
#define IAP_INV (1 << 23)
|
||||
#define IAP_CMASK(C) (((C) & 0xFF) << 24)
|
||||
|
||||
#define IA_OFFCORE_RSP_MASK 0xF7FF
|
||||
#define IA_OFFCORE_RSP_MASK_I7WM 0x000000F7FF
|
||||
#define IA_OFFCORE_RSP_MASK_SBIB 0x3F807F8FFF
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
@ -167,7 +168,7 @@ struct pmc_md_iaf_pmc {
|
||||
|
||||
struct pmc_md_iap_pmc {
|
||||
uint32_t pm_iap_evsel;
|
||||
uint32_t pm_iap_rsp;
|
||||
uint64_t pm_iap_rsp;
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -146,6 +146,10 @@ pmc_intel_initialize(void)
|
||||
cputype = PMC_CPU_INTEL_SANDYBRIDGE;
|
||||
nclasses = 5;
|
||||
break;
|
||||
case 0x3A: /* Per Intel document 253669-043US 05/2012. */
|
||||
cputype = PMC_CPU_INTEL_IVYBRIDGE;
|
||||
nclasses = 3;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#if defined(__i386__) || defined(__amd64__)
|
||||
@ -184,6 +188,7 @@ pmc_intel_initialize(void)
|
||||
case PMC_CPU_INTEL_CORE2:
|
||||
case PMC_CPU_INTEL_CORE2EXTREME:
|
||||
case PMC_CPU_INTEL_COREI7:
|
||||
case PMC_CPU_INTEL_IVYBRIDGE:
|
||||
case PMC_CPU_INTEL_SANDYBRIDGE:
|
||||
case PMC_CPU_INTEL_WESTMERE:
|
||||
error = pmc_core_initialize(pmc_mdep, ncpus);
|
||||
@ -266,6 +271,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
|
||||
case PMC_CPU_INTEL_CORE2:
|
||||
case PMC_CPU_INTEL_CORE2EXTREME:
|
||||
case PMC_CPU_INTEL_COREI7:
|
||||
case PMC_CPU_INTEL_IVYBRIDGE:
|
||||
case PMC_CPU_INTEL_SANDYBRIDGE:
|
||||
case PMC_CPU_INTEL_WESTMERE:
|
||||
pmc_core_finalize(md);
|
||||
|
@ -510,6 +510,9 @@ __PMC_EV(IAP, EVENT_08H_10H) \
|
||||
__PMC_EV(IAP, EVENT_08H_20H) \
|
||||
__PMC_EV(IAP, EVENT_08H_40H) \
|
||||
__PMC_EV(IAP, EVENT_08H_80H) \
|
||||
__PMC_EV(IAP, EVENT_08H_81H) \
|
||||
__PMC_EV(IAP, EVENT_08H_82H) \
|
||||
__PMC_EV(IAP, EVENT_08H_84H) \
|
||||
__PMC_EV(IAP, EVENT_09H_01H) \
|
||||
__PMC_EV(IAP, EVENT_09H_02H) \
|
||||
__PMC_EV(IAP, EVENT_09H_04H) \
|
||||
@ -524,6 +527,9 @@ __PMC_EV(IAP, EVENT_0DH_03H) \
|
||||
__PMC_EV(IAP, EVENT_0DH_40H) \
|
||||
__PMC_EV(IAP, EVENT_0EH_01H) \
|
||||
__PMC_EV(IAP, EVENT_0EH_02H) \
|
||||
__PMC_EV(IAP, EVENT_0EH_10H) \
|
||||
__PMC_EV(IAP, EVENT_0EH_20H) \
|
||||
__PMC_EV(IAP, EVENT_0EH_40H) \
|
||||
__PMC_EV(IAP, EVENT_0FH_01H) \
|
||||
__PMC_EV(IAP, EVENT_0FH_02H) \
|
||||
__PMC_EV(IAP, EVENT_0FH_08H) \
|
||||
@ -701,6 +707,10 @@ __PMC_EV(IAP, EVENT_51H_04H) \
|
||||
__PMC_EV(IAP, EVENT_51H_08H) \
|
||||
__PMC_EV(IAP, EVENT_52H_01H) \
|
||||
__PMC_EV(IAP, EVENT_53H_01H) \
|
||||
__PMC_EV(IAP, EVENT_58H_01H) \
|
||||
__PMC_EV(IAP, EVENT_58H_02H) \
|
||||
__PMC_EV(IAP, EVENT_58H_04H) \
|
||||
__PMC_EV(IAP, EVENT_58H_08H) \
|
||||
__PMC_EV(IAP, EVENT_59H_20H) \
|
||||
__PMC_EV(IAP, EVENT_59H_40H) \
|
||||
__PMC_EV(IAP, EVENT_59H_80H) \
|
||||
@ -711,6 +721,7 @@ __PMC_EV(IAP, EVENT_5BH_4FH) \
|
||||
__PMC_EV(IAP, EVENT_5CH_01H) \
|
||||
__PMC_EV(IAP, EVENT_5CH_02H) \
|
||||
__PMC_EV(IAP, EVENT_5EH_01H) \
|
||||
__PMC_EV(IAP, EVENT_5FH_01H) \
|
||||
__PMC_EV(IAP, EVENT_60H) \
|
||||
__PMC_EV(IAP, EVENT_60H_01H) \
|
||||
__PMC_EV(IAP, EVENT_60H_02H) \
|
||||
@ -746,6 +757,9 @@ __PMC_EV(IAP, EVENT_79H_08H) \
|
||||
__PMC_EV(IAP, EVENT_79H_10H) \
|
||||
__PMC_EV(IAP, EVENT_79H_20H) \
|
||||
__PMC_EV(IAP, EVENT_79H_30H) \
|
||||
__PMC_EV(IAP, EVENT_79H_18H) \
|
||||
__PMC_EV(IAP, EVENT_79H_24H) \
|
||||
__PMC_EV(IAP, EVENT_79H_3CH) \
|
||||
__PMC_EV(IAP, EVENT_7AH) \
|
||||
__PMC_EV(IAP, EVENT_7BH) \
|
||||
__PMC_EV(IAP, EVENT_7DH) \
|
||||
@ -1001,6 +1015,7 @@ __PMC_EV(IAP, EVENT_D2H_04H) \
|
||||
__PMC_EV(IAP, EVENT_D2H_08H) \
|
||||
__PMC_EV(IAP, EVENT_D2H_0FH) \
|
||||
__PMC_EV(IAP, EVENT_D2H_10H) \
|
||||
__PMC_EV(IAP, EVENT_D3H_01H) \
|
||||
__PMC_EV(IAP, EVENT_D4H_01H) \
|
||||
__PMC_EV(IAP, EVENT_D4H_02H) \
|
||||
__PMC_EV(IAP, EVENT_D4H_04H) \
|
||||
@ -2378,6 +2393,191 @@ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \
|
||||
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \
|
||||
__PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H)
|
||||
|
||||
#define __PMC_EV_ALIAS_IVYBRIDGE() \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
|
||||
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
|
||||
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", IAP_EVENT_08H_82H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", IAP_EVENT_08H_84H) \
|
||||
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \
|
||||
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
|
||||
__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \
|
||||
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \
|
||||
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \
|
||||
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \
|
||||
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \
|
||||
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \
|
||||
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \
|
||||
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \
|
||||
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \
|
||||
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \
|
||||
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
|
||||
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
|
||||
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
|
||||
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
|
||||
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
|
||||
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_49H_01H) \
|
||||
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \
|
||||
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \
|
||||
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \
|
||||
__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \
|
||||
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
|
||||
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", IAP_EVENT_58H_01H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", IAP_EVENT_58H_02H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
|
||||
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
|
||||
__PMC_EV_ALIAS("TLB_ACCESS.LOAD_STLB_HIT", IAP_EVENT_5FH_01H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", IAP_EVENT_60H_01H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", IAP_EVENT_60H_02H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", IAP_EVENT_60H_04H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", IAP_EVENT_60H_08H) \
|
||||
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", IAP_EVENT_63H_01H) \
|
||||
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
|
||||
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
|
||||
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
|
||||
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
|
||||
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
|
||||
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
|
||||
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
|
||||
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
|
||||
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_4_UOPS", IAP_EVENT_79H_18H) \
|
||||
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \
|
||||
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \
|
||||
__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \
|
||||
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_88H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_89H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \
|
||||
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
|
||||
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
|
||||
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
|
||||
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
|
||||
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \
|
||||
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \
|
||||
__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \
|
||||
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
|
||||
__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
|
||||
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
|
||||
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
|
||||
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
|
||||
__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \
|
||||
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
|
||||
__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \
|
||||
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \
|
||||
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \
|
||||
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \
|
||||
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
|
||||
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
|
||||
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
|
||||
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \
|
||||
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
|
||||
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
|
||||
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
|
||||
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
|
||||
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
|
||||
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", IAP_EVENT_D2H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", IAP_EVENT_D2H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", IAP_EVENT_D2H_04H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", IAP_EVENT_D2H_08H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", IAP_EVENT_D3H_01H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
|
||||
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \
|
||||
__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H)
|
||||
|
||||
/*
|
||||
* Aliases for Sandy Bridge PMC events (253669-039US May 2011)
|
||||
*/
|
||||
|
@ -87,6 +87,7 @@
|
||||
__PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
|
||||
__PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
|
||||
__PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \
|
||||
__PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \
|
||||
__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
|
||||
__PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
|
||||
__PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
|
||||
|
Loading…
Reference in New Issue
Block a user