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Cleanup address range checks in ioat(4).

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- Deduce allowed address range for bus_dma(9) from the hardware version.
Different versions (CPU generations) have different documented limits.
 - Remove difference between address ranges for src/dst and crc.  At least
docs for few recent generations of CPUs do not mention anything like that,
while older are already limited with above limits.
 - Remove address assertions from arguments.  While I do not think the
addresses out of allowed ranges should realistically happen there due to
the platforms physical address limitations, there is now bus_dma(9) to
make sure of that, preferably via IOMMU.
 - Since crc now has the same address range as src/dst, remove crc_dmamap,
reusing dst2_dmamap instead.

Discussed with:	cem
MFC after:	2 weeks
Sponsored by:	iXsystems, Inc.
This commit is contained in:
Alexander Motin 2019-11-15 22:47:59 +00:00
parent b141dd5ddf
commit 1f4a469d36
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=354752
2 changed files with 26 additions and 69 deletions
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93
sys/dev/ioat/ioat.c
View File

@ -64,7 +64,10 @@ __FBSDID("$FreeBSD$");
#include "ioat_internal.h"
#ifndef BUS_SPACE_MAXADDR_40BIT
#define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL
#define BUS_SPACE_MAXADDR_40BIT MIN(BUS_SPACE_MAXADDR, 0xFFFFFFFFFFULL)
#endif
#ifndef BUS_SPACE_MAXADDR_46BIT
#define BUS_SPACE_MAXADDR_46BIT MIN(BUS_SPACE_MAXADDR, 0x3FFFFFFFFFFFULL)
#endif
static int ioat_probe(device_t device);
@ -413,17 +416,6 @@ ioat_detach(device_t device)
bus_dma_tag_destroy(ioat->data_tag);
}
if (ioat->data_crc_tag != NULL) {
for (i = 0; i < 1 << ioat->ring_size_order; i++) {
error = ioat_bus_dmamap_destroy(ioat, __func__,
ioat->data_crc_tag, ioat->ring[i].crc_dmamap);
if (error != 0)
return (error);
}
bus_dma_tag_destroy(ioat->data_crc_tag);
}
if (ioat->ring != NULL)
ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring);
@ -514,6 +506,7 @@ ioat3_attach(device_t device)
struct ioat_descriptor *ring;
struct ioat_dma_hw_descriptor *dma_hw_desc;
void *hw_desc;
bus_addr_t lowaddr;
size_t ringsz;
int i, num_descriptors;
int error;
@ -549,16 +542,25 @@ ioat3_attach(device_t device)
ioat->is_submitter_processing = FALSE;
bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
if (ioat->version >= IOAT_VER_3_3)
lowaddr = BUS_SPACE_MAXADDR_48BIT;
else if (ioat->version >= IOAT_VER_3_2)
lowaddr = BUS_SPACE_MAXADDR_46BIT;
else
lowaddr = BUS_SPACE_MAXADDR_40BIT;
error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
sizeof(uint64_t), 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
&ioat->comp_update_tag);
if (error != 0)
return (error);
error = bus_dmamem_alloc(ioat->comp_update_tag,
(void **)&ioat->comp_update, BUS_DMA_ZERO | BUS_DMA_WAITOK,
&ioat->comp_update_map);
if (ioat->comp_update == NULL)
return (ENOMEM);
if (error != 0)
return (error);
error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
@ -571,9 +573,8 @@ ioat3_attach(device_t device)
ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors;
error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
2 * 1024 * 1024, 0x0, (bus_addr_t)BUS_SPACE_MAXADDR_40BIT,
BUS_SPACE_MAXADDR, NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL,
&ioat->hw_desc_tag);
2 * 1024 * 1024, 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag);
if (error != 0)
return (error);
@ -590,24 +591,11 @@ ioat3_attach(device_t device)
ioat->hw_desc_ring = hw_desc;
error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
1, 0, BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL,
ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL,
&ioat->data_crc_tag);
if (error != 0) {
ioat_log_message(0, "%s: bus_dma_tag_create failed %d\n",
__func__, error);
return (error);
}
error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
1, 0, BUS_SPACE_MAXADDR_48BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL,
&ioat->data_tag);
if (error != 0) {
ioat_log_message(0, "%s: bus_dma_tag_create failed %d\n",
__func__, error);
if (error != 0)
return (error);
}
ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT,
DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK);
@ -647,14 +635,6 @@ ioat3_attach(device_t device)
error);
return (error);
}
error = bus_dmamap_create(ioat->data_crc_tag, 0,
&ring[i].crc_dmamap);
if (error != 0) {
ioat_log_message(0,
"%s: bus_dmamap_create failed %d\n", __func__,
error);
return (error);
}
}
for (i = 0; i < num_descriptors; i++) {
@ -853,7 +833,6 @@ ioat_process_events(struct ioat_softc *ioat, boolean_t intr)
bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap);
bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap);
bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap);
bus_dmamap_unload(ioat->data_crc_tag, desc->crc_dmamap);
if (dmadesc->callback_fn != NULL)
dmadesc->callback_fn(dmadesc->callback_arg, 0);
@ -1223,10 +1202,6 @@ ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
struct ioat_softc *ioat;
ioat = to_ioat_softc(dmaengine);
KASSERT(((src | dst) & (0xffffull << 48)) == 0,
("%s: high 16 bits of src/dst are not zero", __func__));
desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn,
callback_arg, flags);
if (desc == NULL)
@ -1257,8 +1232,6 @@ ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
ioat = to_ioat_softc(dmaengine);
CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
KASSERT(((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) == 0,
("%s: high 16 bits of src/dst are not zero", __func__));
KASSERT(((src1 | src2 | dst1 | dst2) & PAGE_MASK) == 0,
("%s: addresses are not page-aligned", __func__));
@ -1340,8 +1313,6 @@ ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
KASSERT((ioat->capabilities & IOAT_DMACAP_MOVECRC) != 0,
("%s: device lacks MOVECRC capability", __func__));
KASSERT(((src | dst) & (0xffffffull << 40)) == 0,
("%s: high 24 bits of src/dst are not zero", __func__));
teststore = (flags & _DMA_CRC_TESTSTORE);
KASSERT(teststore != _DMA_CRC_TESTSTORE,
("%s: TEST and STORE invalid", __func__));
@ -1361,10 +1332,6 @@ ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
break;
}
KASSERT((flags & DMA_CRC_INLINE) != 0 ||
(crcptr & (0xffffffull << 40)) == 0,
("%s: high 24 bits of crcptr are not zero", __func__));
desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
callback_arg, flags & ~_DMA_CRC_FLAGS);
if (desc == NULL)
@ -1374,8 +1341,8 @@ ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
if ((flags & DMA_CRC_INLINE) == 0) {
nseg = -1;
error = _bus_dmamap_load_phys(ioat->data_crc_tag,
desc->crc_dmamap, crcptr, sizeof(uint32_t), 0,
error = _bus_dmamap_load_phys(ioat->data_tag,
desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
&seg, &nseg);
if (error != 0) {
ioat_log_message(0, "%s: _bus_dmamap_load_phys"
@ -1416,8 +1383,6 @@ ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
KASSERT((ioat->capabilities & IOAT_DMACAP_CRC) != 0,
("%s: device lacks CRC capability", __func__));
KASSERT((src & (0xffffffull << 40)) == 0,
("%s: high 24 bits of src are not zero", __func__));
teststore = (flags & _DMA_CRC_TESTSTORE);
KASSERT(teststore != _DMA_CRC_TESTSTORE,
("%s: TEST and STORE invalid", __func__));
@ -1437,10 +1402,6 @@ ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
break;
}
KASSERT((flags & DMA_CRC_INLINE) != 0 ||
(crcptr & (0xffffffull << 40)) == 0,
("%s: high 24 bits of crcptr are not zero", __func__));
desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
callback_arg, flags & ~_DMA_CRC_FLAGS);
if (desc == NULL)
@ -1450,8 +1411,8 @@ ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
if ((flags & DMA_CRC_INLINE) == 0) {
nseg = -1;
error = _bus_dmamap_load_phys(ioat->data_crc_tag,
desc->crc_dmamap, crcptr, sizeof(uint32_t), 0,
error = _bus_dmamap_load_phys(ioat->data_tag,
desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
&seg, &nseg);
if (error != 0) {
ioat_log_message(0, "%s: _bus_dmamap_load_phys"
@ -1488,8 +1449,6 @@ ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
KASSERT((ioat->capabilities & IOAT_DMACAP_BFILL) != 0,
("%s: device lacks BFILL capability", __func__));
KASSERT((dst & (0xffffull << 48)) == 0,
("%s: high 16 bits of crcptr are not zero", __func__));
desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst,
callback_fn, callback_arg, flags);

2
sys/dev/ioat/ioat_internal.h
View File

@ -418,7 +418,6 @@ struct ioat_descriptor {
bus_dmamap_t dst_dmamap;
bus_dmamap_t src2_dmamap;
bus_dmamap_t dst2_dmamap;
bus_dmamap_t crc_dmamap;
};
/* Unused by this driver at this time. */
@ -465,7 +464,6 @@ struct ioat_softc {
bus_dmamap_t hw_desc_map;
bus_dma_tag_t data_tag;
bus_dma_tag_t data_crc_tag;
bus_dma_tag_t comp_update_tag;
bus_dmamap_t comp_update_map;