For machines which support PCID but not have INVPCID instruction,
i.e. SandyBridge and IvyBridge, correct a race between pmap_activate() and invltlb_pcid_handler(). Reported by and tested by: Slawa Olhovchenkov <slw@zxy.spb.ru> MFC after: 1 week
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parent
70e7268bd5
commit
20692187ea
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=306350
@ -6842,6 +6842,7 @@ pmap_activate_sw(struct thread *td)
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{
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pmap_t oldpmap, pmap;
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uint64_t cached, cr3;
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register_t rflags;
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u_int cpuid;
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oldpmap = PCPU_GET(curpmap);
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@ -6865,16 +6866,43 @@ pmap_activate_sw(struct thread *td)
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pmap == kernel_pmap,
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("non-kernel pmap thread %p pmap %p cpu %d pcid %#x",
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td, pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
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/*
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* If the INVPCID instruction is not available,
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* invltlb_pcid_handler() is used for handle
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* invalidate_all IPI, which checks for curpmap ==
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* smp_tlb_pmap. Below operations sequence has a
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* window where %CR3 is loaded with the new pmap's
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* PML4 address, but curpmap value is not yet updated.
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* This causes invltlb IPI handler, called between the
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* updates, to execute as NOP, which leaves stale TLB
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* entries.
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*
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* Note that the most typical use of
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* pmap_activate_sw(), from the context switch, is
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* immune to this race, because interrupts are
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* disabled (while the thread lock is owned), and IPI
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* happends after curpmap is updated. Protect other
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* callers in a similar way, by disabling interrupts
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* around the %cr3 register reload and curpmap
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* assignment.
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*/
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if (!invpcid_works)
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rflags = intr_disable();
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if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) {
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load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
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cached);
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if (cached)
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PCPU_INC(pm_save_cnt);
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}
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PCPU_SET(curpmap, pmap);
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if (!invpcid_works)
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intr_restore(rflags);
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} else if (cr3 != pmap->pm_cr3) {
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load_cr3(pmap->pm_cr3);
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PCPU_SET(curpmap, pmap);
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}
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PCPU_SET(curpmap, pmap);
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#ifdef SMP
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CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
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#else
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