Remove Ralink RT1310 support
This armv5 SoC is being removed consistent with the removal of armv5 support, per discussions in arm@ mailing list.
This commit is contained in:
parent
51691e26d0
commit
20d4864396
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=357395
@ -1,79 +0,0 @@
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#
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# Custom kernel for RT1310 boards.
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#
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# $FreeBSD$
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#
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#NO_UNIVERSE
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ident RT1310
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include "std.arm"
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include "../ralink/std.ralink"
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# Flattened Device Tree
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options FDT
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options FDT_DTB_STATIC
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makeoptions FDT_DTS_FILE=wzr2-g300n.dts
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makeoptions MODULES_OVERRIDE=""
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#makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
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options SCHED_4BSD # 4BSD scheduler
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options INET # InterNETworking
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options FFS # Berkeley Fast Filesystem
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options TMPFS # Efficient memory filesystem
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options MSDOSFS
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options ROOTDEVNAME=\"cd9660:/dev/cfid0s.rootfs.uzip\"
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options SYSVSHM # SYSV-style shared memory
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options SYSVMSG # SYSV-style message queues
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options SYSVSEM # SYSV-style semaphores
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options _KPOSIX_PRIORITY_SCHEDULING # Posix P1003_1B real-time extensions
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options MUTEX_NOINLINE
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options RWLOCK_NOINLINE
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options NO_FFS_SNAPSHOT
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options NO_SWAPPING
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# Debugging
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options ALT_BREAK_TO_DEBUGGER
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options DDB
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#options DEADLKRES # Enable the deadlock resolver
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#options DIAGNOSTIC
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#options INVARIANTS # Enable calls of extra sanity checking
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#options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS
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options KDB
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options WITNESS # Enable checks to detect deadlocks and cycles
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options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed
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#options WITNESS_KDB
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# Pseudo devices
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device loop
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device md
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device pty
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# Serial ports
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device uart
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device uart_ns8250
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# Flash
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device cfi
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device cfid
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# Networking
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device ether
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device mii
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device bpf
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device fv
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# etherswitch
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device mdio
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device etherswitch
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device miiproxy
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device ip17x
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# GPIO
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device gpio
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device gpioled
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device rt1310gpio
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@ -1,7 +0,0 @@
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# $FreeBSD$
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arm/ralink/rt1310_machdep.c standard
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arm/ralink/rt1310_intc.c standard
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arm/ralink/rt1310_gpio.c optional rt1310gpio
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arm/ralink/rt1310_timer.c standard
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arm/ralink/if_fv.c optional fv
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File diff suppressed because it is too large
Load Diff
@ -1,452 +0,0 @@
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/*-
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* Copyright (C) 2007
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* Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWFV IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE FV DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWFV, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __IF_FVREG_H__
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#define __IF_FVREG_H__
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struct fv_desc {
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uint32_t fv_stat;
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uint32_t fv_devcs;
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uint32_t fv_addr;
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uint32_t fv_link;
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};
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#define FV_DMASIZE(len) ((len) & ((1 << 11)-1))
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#define FV_PKTSIZE(len) ((len & 0xffff0000) >> 16)
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#define FV_RX_RING_CNT 128
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#define FV_TX_RING_CNT 128
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#define FV_TX_RING_SIZE sizeof(struct fv_desc) * FV_TX_RING_CNT
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#define FV_RX_RING_SIZE sizeof(struct fv_desc) * FV_RX_RING_CNT
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#define FV_RING_ALIGN sizeof(struct fv_desc)
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#define FV_RX_ALIGN sizeof(uint32_t)
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#define FV_MAXFRAGS 8
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#define FV_TX_INTR_THRESH 8
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#define FV_TX_RING_ADDR(sc, i) \
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((sc)->fv_rdata.fv_tx_ring_paddr + sizeof(struct fv_desc) * (i))
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#define FV_RX_RING_ADDR(sc, i) \
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((sc)->fv_rdata.fv_rx_ring_paddr + sizeof(struct fv_desc) * (i))
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#define FV_INC(x,y) (x) = (((x) + 1) % y)
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struct fv_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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};
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struct fv_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct fv_desc *desc;
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/* Use this values on error instead of allocating new mbuf */
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uint32_t saved_ctl, saved_ca;
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};
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struct fv_chain_data {
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bus_dma_tag_t fv_parent_tag;
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bus_dma_tag_t fv_tx_tag;
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struct fv_txdesc fv_txdesc[FV_TX_RING_CNT];
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bus_dma_tag_t fv_rx_tag;
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struct fv_rxdesc fv_rxdesc[FV_RX_RING_CNT];
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bus_dma_tag_t fv_tx_ring_tag;
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bus_dma_tag_t fv_rx_ring_tag;
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bus_dmamap_t fv_tx_ring_map;
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bus_dmamap_t fv_rx_ring_map;
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bus_dmamap_t fv_rx_sparemap;
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int fv_tx_pkts;
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int fv_tx_prod;
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int fv_tx_cons;
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int fv_tx_cnt;
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int fv_rx_cons;
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bus_dma_tag_t fv_sf_tag;
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bus_dmamap_t fv_sf_buff_map;
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uint32_t *fv_sf_buff;
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};
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struct fv_ring_data {
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struct fv_desc *fv_rx_ring;
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struct fv_desc *fv_tx_ring;
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bus_addr_t fv_rx_ring_paddr;
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bus_addr_t fv_tx_ring_paddr;
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bus_addr_t fv_sf_paddr;
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};
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struct fv_softc {
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struct ifnet *fv_ifp; /* interface info */
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bus_space_handle_t fv_bhandle; /* bus space handle */
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bus_space_tag_t fv_btag; /* bus space tag */
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device_t fv_dev;
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uint8_t fv_eaddr[ETHER_ADDR_LEN];
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struct resource *fv_res;
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int fv_rid;
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struct resource *fv_irq;
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void *fv_intrhand;
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u_int32_t sc_inten; /* copy of CSR_INTEN */
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u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */
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u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */
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#ifdef MII
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device_t fv_miibus;
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#else
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struct ifmedia fv_ifmedia;
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#endif
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#ifdef FV_MDIO
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device_t fv_miiproxy;
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#endif
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int fv_if_flags;
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bus_dma_tag_t fv_parent_tag;
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bus_dma_tag_t fv_tag;
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struct mtx fv_mtx;
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phandle_t fv_ofw;
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struct callout fv_stat_callout;
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struct task fv_link_task;
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struct fv_chain_data fv_cdata;
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struct fv_ring_data fv_rdata;
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int fv_link_status;
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int fv_detach;
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};
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#define FV_LOCK(_sc) mtx_lock(&(_sc)->fv_mtx)
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#define FV_UNLOCK(_sc) mtx_unlock(&(_sc)->fv_mtx)
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#define FV_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->fv_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->fv_btag, sc->fv_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->fv_btag, sc->fv_bhandle, reg)
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/* $NetBSD: aereg.h,v 1.2 2008/04/28 20:23:28 martin Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWFV IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE FV DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWFV, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Descriptor Status bits common to transmit and receive.
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*/
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#define ADSTAT_OWN 0x80000000 /* Tulip owns descriptor */
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#define ADSTAT_ES 0x00008000 /* Error Summary */
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/*
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* Descriptor Status bits for Receive Descriptor.
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*/
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#define ADSTAT_Rx_FF 0x40000000 /* Filtering Fail */
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#define ADSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */
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#define ADSTAT_Rx_DE 0x00004000 /* Descriptor Error */
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#define ADSTAT_Rx_LE 0x00001000 /* Length Error */
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#define ADSTAT_Rx_RF 0x00000800 /* Runt Frame */
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#define ADSTAT_Rx_MF 0x00000400 /* Multicast Frame */
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#define ADSTAT_Rx_FS 0x00000200 /* First Descriptor */
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#define ADSTAT_Rx_LS 0x00000100 /* Last Descriptor */
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#define ADSTAT_Rx_TL 0x00000080 /* Frame Too Long */
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#define ADSTAT_Rx_CS 0x00000040 /* Collision Seen */
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#define ADSTAT_Rx_RT 0x00000020 /* Frame Type */
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#define ADSTAT_Rx_RW 0x00000010 /* Receive Watchdog */
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#define ADSTAT_Rx_RE 0x00000008 /* Report on MII Error */
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#define ADSTAT_Rx_DB 0x00000004 /* Dribbling Bit */
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#define ADSTAT_Rx_CE 0x00000002 /* CRC Error */
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#define ADSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */
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#define ADSTAT_Rx_LENGTH(x) (((x) & ADSTAT_Rx_FL) >> 16)
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/*
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* Descriptor Status bits for Transmit Descriptor.
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*/
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#define ADSTAT_Tx_ES 0x00008000 /* Error Summary */
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#define ADSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */
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#define ADSTAT_Tx_LO 0x00000800 /* Loss of Carrier */
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#define ADSTAT_Tx_NC 0x00000400 /* No Carrier */
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#define ADSTAT_Tx_LC 0x00000200 /* Late Collision */
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#define ADSTAT_Tx_EC 0x00000100 /* Excessive Collisions */
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#define ADSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */
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#define ADSTAT_Tx_CC 0x00000078 /* Collision Count */
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#define ADSTAT_Tx_ED 0x00000004 /* Excessive Deferral */
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#define ADSTAT_Tx_UF 0x00000002 /* Underflow Error */
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#define ADSTAT_Tx_DE 0x00000001 /* Deferred */
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#define ADSTAT_Tx_COLLISIONS(x) (((x) & ADSTAT_Tx_CC) >> 3)
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/*
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* Descriptor Control bits common to transmit and receive.
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*/
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#define ADCTL_SIZE1 0x000007ff /* Size of buffer 1 */
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#define ADCTL_SIZE1_SHIFT 0
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#define ADCTL_SIZE2 0x003ff800 /* Size of buffer 2 */
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#define ADCTL_SIZE2_SHIFT 11
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#define ADCTL_ER 0x02000000 /* End of Ring */
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#define ADCTL_CH 0x01000000 /* Second Address Chained */
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/*
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* Descriptor Control bits for Transmit Descriptor.
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*/
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#define ADCTL_Tx_IC 0x80000000 /* Interrupt on Completion */
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#define ADCTL_Tx_LS 0x40000000 /* Last Segment */
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#define ADCTL_Tx_FS 0x20000000 /* First Segment */
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#define ADCTL_Tx_SETUP 0x08000000 /* Setup frame */
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#define ADCTL_Tx_AC 0x04000000 /* Add CRC Disable */
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#define ADCTL_Tx_DPD 0x00800000 /* Disabled Padding */
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/*
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* Control registers.
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*/
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/* tese are registers only found on this part */
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#ifdef NOTUSE
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#define CSR_MACCTL 0x0000 /* mac control */
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#define CSR_MACHI 0x0004
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#define CSR_MACLO 0x0008
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#define CSR_HTHI 0x000C /* multicast table high */
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#define CSR_HTLO 0x0010 /* multicast table low */
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#define CSR_MIIADDR 0x0014 /* mii address */
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#define CSR_MIIDATA 0x0018 /* mii data */
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#define CSR_FLOWC 0x001C /* flow control */
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#define CSR_VL1 0x0020 /* vlan 1 tag */
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#endif
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/* these are more or less normal Tulip registers */
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#define CSR_BUSMODE (0x08*0) /* bus mode */
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#define CSR_TXPOLL (0x08*1) /* tx poll demand */
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#define CSR_RXPOLL (0x08*2) /* rx poll demand */
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#define CSR_RXLIST (0x08*3) /* rx base descriptor address */
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#define CSR_TXLIST (0x08*4) /* tx base descriptor address */
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#define CSR_STATUS (0x08*5) /* (interrupt) status */
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#define CSR_OPMODE (0x08*6) /* operation mode */
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#define CSR_INTEN (0x08*7) /* interrupt enable */
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#define CSR_MISSED (0x08*8) /* missed frame counter */
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#ifdef NOTUSE
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#define CSR_HTBA 0x1050 /* host tx buffer address (ro) */
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#define CSR_HRBA 0x1054 /* host rx buffer address (ro) */
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#endif
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#define CSR_MIIMNG (0x08*9) /* MII Management Register */
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#define CSR_FULLDUP (0x08*11) /* Full Duplex Register */
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/* 21143 like register */
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#define FULLDUP_CS 0x80000000 /* Cycle Size */
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#define FULLDUP_TT_SHIFT 27 /* Transmit Timer */
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#define FULLDUP_NTP_SHIFT 24 /* Number of Transmit Packets */
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#define FULLDUP_RT_SHIFT 20 /* Receive Timer */
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#define FULLDUP_NRP_SHIFT 17 /* Number of Receive Packets */
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#define FULLDUP_CON_MODE 0x00010000 /* Continuous Mode */
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#define FULLDUP_TIM_SHIFT 0 /* Timer Value */
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/* CSR_MACCTL - Mac Control */
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#define MACCTL_RE 0x00000004 /* rx enable */
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#define MACCTL_TE 0x00000008 /* tx enable */
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#define MACCTL_DC 0x00000020 /* deferral check */
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#define MACCTL_PSTR 0x00000100 /* automatic pad strip */
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#define MACCTL_DTRY 0x00000400 /* disable retry */
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#define MACCTL_DBF 0x00000800 /* disable broadcast frames */
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#define MACCTL_LCC 0x00001000 /* late collision control */
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#define MACCTL_HASH 0x00002000 /* hash filtering enable */
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#define MACCTL_HO 0x00008000 /* disable perfect filtering */
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#define MACCTL_PB 0x00010000 /* pass bad frames */
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#define MACCTL_IF 0x00020000 /* inverse filtering */
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#define MACCTL_PR 0x00040000 /* promiscuous mode */
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#define MACCTL_PM 0x00080000 /* pass all multicast */
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#define MACCTL_FDX 0x00100000 /* full duplex mode */
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#define MACCTL_LOOP 0x00600000 /* loopback mask */
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#define MACCTL_LOOP_INT 0x00200000 /* internal loopback */
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#define MACCTL_LOOP_EXT 0x00400000 /* external loopback */
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#define MACCTL_LOOP_NONE 0x00000000
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#define MACCTL_DRO 0x00800000 /* disable receive own */
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#define MACCTL_PS 0x08000000 /* port select, 0 = mii */
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#define MACCTL_HBD 0x10000000 /* heartbeat disable */
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#define MACCTL_BLE 0x40000000 /* mac big endian */
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#define MACCTL_RA 0x80000000 /* receive all packets */
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/* CSR_MIIADDR - MII Addess */
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#define MIIADDR_BUSY 0x00000001 /* mii busy */
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#define MIIADDR_WRITE 0x00000002 /* mii write */
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#define MIIADDR_REG_MASK 0x000007C0 /* mii register */
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#define MIIADDR_REG_SHIFT 6
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#define MIIADDR_PHY_MASK 0x0000F800 /* mii phy */
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#define MIIADDR_PHY_SHIFT 11
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#define MIIADDR_GETREG(x) (((x) & MIIADDR_REG) >> 6)
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#define MIIADDR_PUTREG(x) (((x) << 6) & MIIADR_REG)
|
||||
#define MIIADDR_GETPHY(x) (((x) & MIIADDR_PHY) >> 11)
|
||||
#define MIIADDR_PUTPHY(x) (((x) << 6) & MIIADR_PHY)
|
||||
|
||||
/* CSR_FLOWC - Flow Control */
|
||||
#define FLOWC_FCB 0x00000001 /* flow control busy */
|
||||
#define FLOWC_FCE 0x00000002 /* flow control enable */
|
||||
#define FLOWC_PCF 0x00000004 /* pass control frames */
|
||||
#define FLOWC_PT 0xffff0000 /* pause time */
|
||||
|
||||
/* CSR_BUSMODE - Bus Mode */
|
||||
#define BUSMODE_SWR 0x00000001 /* software reset */
|
||||
#define BUSMODE_BAR 0x00000002 /* bus arbitration */
|
||||
#define BUSMODE_DSL 0x0000007c /* descriptor skip length */
|
||||
#define BUSMODE_BLE 0x00000080 /* data buf endian */
|
||||
/* programmable burst length */
|
||||
#define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */
|
||||
#define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */
|
||||
#define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */
|
||||
#define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */
|
||||
#define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */
|
||||
#define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */
|
||||
#define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */
|
||||
#define BUSMODE_TAP_SHIFT 17 /* Transmit Automatic Polling */
|
||||
#define BUSMODE_DBO 0x00100000 /* descriptor endian */
|
||||
#define BUSMODE_ALIGN_16B 0x01000000 /* force oddhw rx buf align */
|
||||
|
||||
/* CSR_TXPOLL - Transmit Poll Demand */
|
||||
#define TXPOLL_TPD 0x00000001 /* transmit poll demand */
|
||||
|
||||
|
||||
/* CSR_RXPOLL - Receive Poll Demand */
|
||||
#define RXPOLL_RPD 0x00000001 /* receive poll demand */
|
||||
|
||||
/* CSR_STATUS - Status */
|
||||
#define STATUS_TI 0x00000001 /* transmit interrupt */
|
||||
#define STATUS_TPS 0x00000002 /* transmit process stopped */
|
||||
#define STATUS_TU 0x00000004 /* transmit buffer unavail */
|
||||
#define STATUS_TJT 0x00000008 /* transmit jabber timeout */
|
||||
#define STATUS_UNF 0x00000020 /* transmit underflow */
|
||||
#define STATUS_RI 0x00000040 /* receive interrupt */
|
||||
#define STATUS_RU 0x00000080 /* receive buffer unavail */
|
||||
#define STATUS_RPS 0x00000100 /* receive process stopped */
|
||||
#define STATUS_ETI 0x00000400 /* early transmit interrupt */
|
||||
#define STATUS_SE 0x00002000 /* system error */
|
||||
#define STATUS_ER 0x00004000 /* early receive (21041) */
|
||||
#define STATUS_AIS 0x00008000 /* abnormal intr summary */
|
||||
#define STATUS_NIS 0x00010000 /* normal interrupt summary */
|
||||
#define STATUS_RS 0x000e0000 /* receive process state */
|
||||
#define STATUS_RS_STOPPED 0x00000000 /* Stopped */
|
||||
#define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive
|
||||
descriptor */
|
||||
#define STATUS_RS_CHECK 0x00040000 /* Running - check for end
|
||||
of receive */
|
||||
#define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */
|
||||
#define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */
|
||||
#define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive
|
||||
descriptor */
|
||||
#define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current
|
||||
frame from FIFO */
|
||||
#define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current
|
||||
frame from FIFO into
|
||||
buffer */
|
||||
#define STATUS_TS 0x00700000 /* transmit process state */
|
||||
#define STATUS_TS_STOPPED 0x00000000 /* Stopped */
|
||||
#define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit
|
||||
descriptor */
|
||||
#define STATUS_TS_WAIT 0x00200000 /* Running - wait for end
|
||||
of transmission */
|
||||
#define STATUS_TS_READING 0x00300000 /* Running - read buffer from
|
||||
memory and queue into
|
||||
FIFO */
|
||||
#define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */
|
||||
#define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit
|
||||
descriptor */
|
||||
#define STATUS_TX_ABORT 0x00800000 /* Transmit bus abort */
|
||||
#define STATUS_RX_ABORT 0x01000000 /* Transmit bus abort */
|
||||
|
||||
/* CSR_OPMODE - Operation Mode */
|
||||
#define OPMODE_SR 0x00000002 /* start receive */
|
||||
#define OPMODE_OSF 0x00000004 /* operate on second frame */
|
||||
#define OPMODE_PR 0x00000040 /* promiscuous mode */
|
||||
#define OPMODE_PM 0x00000080 /* pass all multicast */
|
||||
#define OPMODE_FDX 0x00000200 /* full duplex mode */
|
||||
#define OPMODE_ST 0x00002000 /* start transmitter */
|
||||
#define OPMODE_TR 0x0000c000 /* threshold control */
|
||||
#define OPMODE_TR_32 0x00000000 /* 32 words */
|
||||
#define OPMODE_TR_64 0x00004000 /* 64 words */
|
||||
#define OPMODE_TR_128 0x00008000 /* 128 words */
|
||||
#define OPMODE_TR_256 0x0000c000 /* 256 words */
|
||||
#define OPMODE_SF 0x00200000 /* store and forward mode */
|
||||
#define OPMODE_SPEED 0x80000000 /* speed 100M:1 10M:0 */
|
||||
|
||||
/* CSR_INTEN - Interrupt Enable */
|
||||
/* See bits for CSR_STATUS -- Status */
|
||||
|
||||
|
||||
/* CSR_MISSED - Missed Frames */
|
||||
#define MISSED_MFC 0xffff0000 /* missed packet count */
|
||||
#define MISSED_FOC 0x0000ffff /* fifo overflow counter */
|
||||
|
||||
#define MISSED_GETMFC(x) ((x) & MISSED_MFC)
|
||||
#define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 16)
|
||||
|
||||
/* setup frame code refer dc code */
|
||||
|
||||
#define FV_SFRAME_LEN 192
|
||||
#define FV_MIN_FRAMELEN 60
|
||||
|
||||
/*
|
||||
* MII Definitions for the 21041 and 21140/21140A/21142
|
||||
* copy from if_devar.h
|
||||
*/
|
||||
#define MII_PREAMBLE (~0)
|
||||
#define MII_TEST 0xAAAAAAAA
|
||||
#define MII_RDCMD 0x06
|
||||
#define MII_WRCMD 0x05
|
||||
#define MII_DIN 0x00080000
|
||||
#define MII_RD 0x00040000
|
||||
#define MII_WR 0x00000000
|
||||
#define MII_DOUT 0x00020000
|
||||
#define MII_CLK 0x00010000
|
||||
#define MII_CLKON MII_CLK
|
||||
#define MII_CLKOFF MII_CLK
|
||||
|
||||
#endif /* __IF_FVREG_H__ */
|
@ -1,480 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
|
||||
* Copyright (c) 2015 Hiroki Mori
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPIO on RT1310A consist of 2 ports:
|
||||
* - PortA with 8 input/output pins
|
||||
* - PortB with 4 input/output pins
|
||||
*
|
||||
* Pins are mapped to logical pin number as follows:
|
||||
* [0..7] -> GPI_00..GPI_07 (port A)
|
||||
* [8..11] -> GPI_08..GPI_11 (port B)
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bio.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/endian.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/kthread.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/queue.h>
|
||||
#include <sys/resource.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/timetc.h>
|
||||
#include <sys/watchdog.h>
|
||||
#include <sys/gpio.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/cpufunc.h>
|
||||
#include <machine/resource.h>
|
||||
#include <machine/intr.h>
|
||||
#include <machine/fdt.h>
|
||||
|
||||
#include <dev/gpio/gpiobusvar.h>
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include <arm/ralink/rt1310reg.h>
|
||||
#include <arm/ralink/rt1310var.h>
|
||||
|
||||
#include "gpio_if.h"
|
||||
|
||||
struct rt1310_gpio_softc
|
||||
{
|
||||
device_t lg_dev;
|
||||
device_t lg_busdev;
|
||||
struct resource * lg_res;
|
||||
bus_space_tag_t lg_bst;
|
||||
bus_space_handle_t lg_bsh;
|
||||
};
|
||||
|
||||
struct rt1310_gpio_pinmap
|
||||
{
|
||||
int lp_start_idx;
|
||||
int lp_pin_count;
|
||||
int lp_port;
|
||||
int lp_start_bit;
|
||||
int lp_flags;
|
||||
};
|
||||
|
||||
static const struct rt1310_gpio_pinmap rt1310_gpio_pins[] = {
|
||||
{ 0, 8, RT_GPIO_PORTA, 0, GPIO_PIN_INPUT | GPIO_PIN_OUTPUT },
|
||||
{ 8, 4, RT_GPIO_PORTB, 0, GPIO_PIN_INPUT | GPIO_PIN_OUTPUT },
|
||||
{ -1, -1, -1, -1, -1 },
|
||||
};
|
||||
|
||||
#define RT_GPIO_NPINS 12
|
||||
|
||||
#define RT_GPIO_PIN_IDX(_map, _idx) \
|
||||
(_idx - _map->lp_start_idx)
|
||||
|
||||
#define RT_GPIO_PIN_BIT(_map, _idx) \
|
||||
(_map->lp_start_bit + RT_GPIO_PIN_IDX(_map, _idx))
|
||||
|
||||
static int rt1310_gpio_probe(device_t);
|
||||
static int rt1310_gpio_attach(device_t);
|
||||
static int rt1310_gpio_detach(device_t);
|
||||
|
||||
static device_t rt1310_gpio_get_bus(device_t);
|
||||
static int rt1310_gpio_pin_max(device_t, int *);
|
||||
static int rt1310_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
|
||||
static int rt1310_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
|
||||
static int rt1310_gpio_pin_setflags(device_t, uint32_t, uint32_t);
|
||||
static int rt1310_gpio_pin_getname(device_t, uint32_t, char *);
|
||||
static int rt1310_gpio_pin_get(device_t, uint32_t, uint32_t *);
|
||||
static int rt1310_gpio_pin_set(device_t, uint32_t, uint32_t);
|
||||
static int rt1310_gpio_pin_toggle(device_t, uint32_t);
|
||||
|
||||
static const struct rt1310_gpio_pinmap *rt1310_gpio_get_pinmap(int);
|
||||
|
||||
static struct rt1310_gpio_softc *rt1310_gpio_sc = NULL;
|
||||
|
||||
#define rt1310_gpio_read_4(_sc, _reg) \
|
||||
bus_space_read_4(_sc->lg_bst, _sc->lg_bsh, _reg)
|
||||
#define rt1310_gpio_write_4(_sc, _reg, _val) \
|
||||
bus_space_write_4(_sc->lg_bst, _sc->lg_bsh, _reg, _val)
|
||||
|
||||
static int
|
||||
rt1310_gpio_probe(device_t dev)
|
||||
{
|
||||
phandle_t node;
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (!ofw_bus_is_compatible(dev, "ralink,rt1310-gpio"))
|
||||
return (ENXIO);
|
||||
|
||||
node = ofw_bus_get_node(dev);
|
||||
if (!OF_hasprop(node, "gpio-controller"))
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "RT1310 GPIO");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_attach(device_t dev)
|
||||
{
|
||||
struct rt1310_gpio_softc *sc = device_get_softc(dev);
|
||||
int rid;
|
||||
|
||||
sc->lg_dev = dev;
|
||||
|
||||
rid = 0;
|
||||
sc->lg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
||||
RF_ACTIVE);
|
||||
if (!sc->lg_res) {
|
||||
device_printf(dev, "cannot allocate memory window\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
sc->lg_bst = rman_get_bustag(sc->lg_res);
|
||||
sc->lg_bsh = rman_get_bushandle(sc->lg_res);
|
||||
|
||||
rt1310_gpio_sc = sc;
|
||||
|
||||
sc->lg_busdev = gpiobus_attach_bus(dev);
|
||||
if (sc->lg_busdev == NULL) {
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->lg_res);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_detach(device_t dev)
|
||||
{
|
||||
return (EBUSY);
|
||||
}
|
||||
|
||||
static device_t
|
||||
rt1310_gpio_get_bus(device_t dev)
|
||||
{
|
||||
struct rt1310_gpio_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
return (sc->lg_busdev);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_max(device_t dev, int *npins)
|
||||
{
|
||||
*npins = RT_GPIO_NPINS - 1;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
|
||||
{
|
||||
const struct rt1310_gpio_pinmap *map;
|
||||
|
||||
if (pin > RT_GPIO_NPINS)
|
||||
return (ENODEV);
|
||||
|
||||
map = rt1310_gpio_get_pinmap(pin);
|
||||
|
||||
*caps = map->lp_flags;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
|
||||
{
|
||||
struct rt1310_gpio_softc *sc = device_get_softc(dev);
|
||||
const struct rt1310_gpio_pinmap *map;
|
||||
uint32_t state;
|
||||
int dir;
|
||||
|
||||
if (pin > RT_GPIO_NPINS)
|
||||
return (ENODEV);
|
||||
|
||||
map = rt1310_gpio_get_pinmap(pin);
|
||||
|
||||
/* Check whether it's bidirectional pin */
|
||||
if ((map->lp_flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) !=
|
||||
(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
|
||||
*flags = map->lp_flags;
|
||||
return (0);
|
||||
}
|
||||
|
||||
switch (map->lp_port) {
|
||||
case RT_GPIO_PORTA:
|
||||
state = rt1310_gpio_read_4(sc, RT_GPIO_OFF_PADIR);
|
||||
dir = (state & (1 << RT_GPIO_PIN_BIT(map, pin)));
|
||||
break;
|
||||
case RT_GPIO_PORTB:
|
||||
state = rt1310_gpio_read_4(sc, RT_GPIO_OFF_PBDIR);
|
||||
dir = (state & (1 << RT_GPIO_PIN_BIT(map, pin)));
|
||||
break;
|
||||
default:
|
||||
panic("unknown GPIO port");
|
||||
}
|
||||
|
||||
*flags = dir ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
|
||||
{
|
||||
struct rt1310_gpio_softc *sc = device_get_softc(dev);
|
||||
const struct rt1310_gpio_pinmap *map;
|
||||
uint32_t dir, state;
|
||||
uint32_t port;
|
||||
|
||||
if (pin > RT_GPIO_NPINS)
|
||||
return (ENODEV);
|
||||
|
||||
map = rt1310_gpio_get_pinmap(pin);
|
||||
|
||||
/* Check whether it's bidirectional pin */
|
||||
if ((map->lp_flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) !=
|
||||
(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
|
||||
return (ENOTSUP);
|
||||
|
||||
if (flags & GPIO_PIN_INPUT)
|
||||
dir = 0;
|
||||
|
||||
if (flags & GPIO_PIN_OUTPUT)
|
||||
dir = 1;
|
||||
|
||||
switch (map->lp_port) {
|
||||
case RT_GPIO_PORTA:
|
||||
port = RT_GPIO_OFF_PADIR;
|
||||
break;
|
||||
case RT_GPIO_PORTB:
|
||||
port = RT_GPIO_OFF_PBDIR;
|
||||
break;
|
||||
}
|
||||
|
||||
state = rt1310_gpio_read_4(sc, port);
|
||||
if (flags & GPIO_PIN_INPUT) {
|
||||
state &= ~(1 << RT_GPIO_PIN_IDX(map, pin));
|
||||
} else {
|
||||
state |= (1 << RT_GPIO_PIN_IDX(map, pin));
|
||||
}
|
||||
rt1310_gpio_write_4(sc, port, state);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
|
||||
{
|
||||
snprintf(name, GPIOMAXNAME - 1, "GPIO_%02d", pin);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_get(device_t dev, uint32_t pin, uint32_t *value)
|
||||
{
|
||||
struct rt1310_gpio_softc *sc = device_get_softc(dev);
|
||||
const struct rt1310_gpio_pinmap *map;
|
||||
uint32_t state, flags;
|
||||
int dir;
|
||||
|
||||
map = rt1310_gpio_get_pinmap(pin);
|
||||
|
||||
if (rt1310_gpio_pin_getflags(dev, pin, &flags))
|
||||
return (ENXIO);
|
||||
|
||||
if (flags & GPIO_PIN_OUTPUT)
|
||||
dir = 1;
|
||||
|
||||
if (flags & GPIO_PIN_INPUT)
|
||||
dir = 0;
|
||||
|
||||
switch (map->lp_port) {
|
||||
case RT_GPIO_PORTA:
|
||||
state = rt1310_gpio_read_4(sc, RT_GPIO_OFF_PADR);
|
||||
*value = !!(state & (1 << RT_GPIO_PIN_BIT(map, pin)));
|
||||
break;
|
||||
case RT_GPIO_PORTB:
|
||||
state = rt1310_gpio_read_4(sc, RT_GPIO_OFF_PBDR);
|
||||
*value = !!(state & (1 << RT_GPIO_PIN_BIT(map, pin)));
|
||||
break;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_set(device_t dev, uint32_t pin, uint32_t value)
|
||||
{
|
||||
struct rt1310_gpio_softc *sc = device_get_softc(dev);
|
||||
const struct rt1310_gpio_pinmap *map;
|
||||
uint32_t state, flags;
|
||||
uint32_t port;
|
||||
|
||||
map = rt1310_gpio_get_pinmap(pin);
|
||||
|
||||
if (rt1310_gpio_pin_getflags(dev, pin, &flags))
|
||||
return (ENXIO);
|
||||
|
||||
if ((flags & GPIO_PIN_OUTPUT) == 0)
|
||||
return (EINVAL);
|
||||
|
||||
switch (map->lp_port) {
|
||||
case RT_GPIO_PORTA:
|
||||
port = RT_GPIO_OFF_PADR;
|
||||
break;
|
||||
case RT_GPIO_PORTB:
|
||||
port = RT_GPIO_OFF_PBDR;
|
||||
break;
|
||||
}
|
||||
|
||||
state = rt1310_gpio_read_4(sc, port);
|
||||
if (value == 1) {
|
||||
state |= (1 << RT_GPIO_PIN_BIT(map, pin));
|
||||
} else {
|
||||
state &= ~(1 << RT_GPIO_PIN_BIT(map, pin));
|
||||
}
|
||||
rt1310_gpio_write_4(sc, port, state);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_gpio_pin_toggle(device_t dev, uint32_t pin)
|
||||
{
|
||||
const struct rt1310_gpio_pinmap *map;
|
||||
uint32_t flags;
|
||||
|
||||
map = rt1310_gpio_get_pinmap(pin);
|
||||
|
||||
if (rt1310_gpio_pin_getflags(dev, pin, &flags))
|
||||
return (ENXIO);
|
||||
|
||||
if ((flags & GPIO_PIN_OUTPUT) == 0)
|
||||
return (EINVAL);
|
||||
|
||||
panic("not implemented yet");
|
||||
|
||||
return (0);
|
||||
|
||||
}
|
||||
|
||||
static const struct rt1310_gpio_pinmap *
|
||||
rt1310_gpio_get_pinmap(int pin)
|
||||
{
|
||||
const struct rt1310_gpio_pinmap *map;
|
||||
|
||||
for (map = &rt1310_gpio_pins[0]; map->lp_start_idx != -1; map++) {
|
||||
if (pin >= map->lp_start_idx &&
|
||||
pin < map->lp_start_idx + map->lp_pin_count)
|
||||
return map;
|
||||
}
|
||||
|
||||
panic("pin number %d out of range", pin);
|
||||
}
|
||||
|
||||
int
|
||||
rt1310_gpio_set_flags(device_t dev, int pin, int flags)
|
||||
{
|
||||
if (rt1310_gpio_sc == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
return rt1310_gpio_pin_setflags(rt1310_gpio_sc->lg_dev, pin, flags);
|
||||
}
|
||||
|
||||
int
|
||||
rt1310_gpio_set_state(device_t dev, int pin, int state)
|
||||
{
|
||||
if (rt1310_gpio_sc == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
return rt1310_gpio_pin_set(rt1310_gpio_sc->lg_dev, pin, state);
|
||||
}
|
||||
|
||||
int
|
||||
rt1310_gpio_get_state(device_t dev, int pin, int *state)
|
||||
{
|
||||
if (rt1310_gpio_sc == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
return rt1310_gpio_pin_get(rt1310_gpio_sc->lg_dev, pin, state);
|
||||
}
|
||||
|
||||
static phandle_t
|
||||
rt1310_gpio_get_node(device_t bus, device_t dev)
|
||||
{
|
||||
/* We only have one child, the GPIO bus, which needs our own node. */
|
||||
return (ofw_bus_get_node(bus));
|
||||
}
|
||||
|
||||
static device_method_t rt1310_gpio_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, rt1310_gpio_probe),
|
||||
DEVMETHOD(device_attach, rt1310_gpio_attach),
|
||||
DEVMETHOD(device_detach, rt1310_gpio_detach),
|
||||
|
||||
/* GPIO interface */
|
||||
DEVMETHOD(gpio_get_bus, rt1310_gpio_get_bus),
|
||||
DEVMETHOD(gpio_pin_max, rt1310_gpio_pin_max),
|
||||
DEVMETHOD(gpio_pin_getcaps, rt1310_gpio_pin_getcaps),
|
||||
DEVMETHOD(gpio_pin_getflags, rt1310_gpio_pin_getflags),
|
||||
DEVMETHOD(gpio_pin_setflags, rt1310_gpio_pin_setflags),
|
||||
DEVMETHOD(gpio_pin_getname, rt1310_gpio_pin_getname),
|
||||
DEVMETHOD(gpio_pin_set, rt1310_gpio_pin_set),
|
||||
DEVMETHOD(gpio_pin_get, rt1310_gpio_pin_get),
|
||||
DEVMETHOD(gpio_pin_toggle, rt1310_gpio_pin_toggle),
|
||||
|
||||
/* ofw_bus interface */
|
||||
DEVMETHOD(ofw_bus_get_node, rt1310_gpio_get_node),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t rt1310_gpio_devclass;
|
||||
|
||||
static driver_t rt1310_gpio_driver = {
|
||||
"gpio",
|
||||
rt1310_gpio_methods,
|
||||
sizeof(struct rt1310_gpio_softc),
|
||||
};
|
||||
|
||||
DRIVER_MODULE(rt1310gpio, simplebus, rt1310_gpio_driver, rt1310_gpio_devclass, 0, 0);
|
||||
MODULE_VERSION(rt1310gpio, 1);
|
@ -1,336 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2010 Jakub Wojciech Klama <jceel@FreeBSD.org>
|
||||
* Copyright (c) 2015 Hiroki Mori
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include "opt_platform.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/proc.h>
|
||||
#include <sys/rman.h>
|
||||
#include <vm/vm.h>
|
||||
#include <vm/vm_kern.h>
|
||||
#include <vm/pmap.h>
|
||||
#include <vm/vm_page.h>
|
||||
#include <vm/vm_extern.h>
|
||||
|
||||
#define _ARM32_BUS_DMA_PRIVATE
|
||||
#include <machine/bus.h>
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <dev/fdt/fdt_common.h>
|
||||
#include <dev/ofw/openfirm.h>
|
||||
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include <arm/ralink/rt1310reg.h>
|
||||
|
||||
#define INTC_NIRQS 32
|
||||
|
||||
#include "pic_if.h"
|
||||
|
||||
struct rt1310_irqsrc {
|
||||
struct intr_irqsrc ri_isrc;
|
||||
u_int ri_irq;
|
||||
};
|
||||
|
||||
struct rt1310_intc_softc {
|
||||
device_t dev;
|
||||
struct resource * ri_res;
|
||||
bus_space_tag_t ri_bst;
|
||||
bus_space_handle_t ri_bsh;
|
||||
struct rt1310_irqsrc ri_isrcs[INTC_NIRQS];
|
||||
};
|
||||
|
||||
static int rt1310_intc_probe(device_t);
|
||||
static int rt1310_intc_attach(device_t);
|
||||
static int rt1310_pic_attach(struct rt1310_intc_softc *sc);
|
||||
|
||||
static struct rt1310_intc_softc *intc_softc = NULL;
|
||||
|
||||
#define intc_read_4(_sc, _reg) \
|
||||
bus_space_read_4((_sc)->ri_bst, (_sc)->ri_bsh, (_reg))
|
||||
#define intc_write_4(_sc, _reg, _val) \
|
||||
bus_space_write_4((_sc)->ri_bst, (_sc)->ri_bsh, (_reg), (_val))
|
||||
|
||||
struct rt1310_irqdef {
|
||||
u_int ri_trig;
|
||||
u_int ri_prio;
|
||||
};
|
||||
|
||||
struct rt1310_irqdef irqdef[INTC_NIRQS] = {
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2}, /* 0 */
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 1},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 1},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 1},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 1},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 1}, /* 8 */
|
||||
{RT_INTC_TRIG_HIGH_LVL, 1},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_LOW_LVL, 2},
|
||||
{RT_INTC_TRIG_LOW_LVL, 2},
|
||||
{RT_INTC_TRIG_LOW_LVL, 4},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2}, /* 16 */
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_LOW_LVL, 2},
|
||||
{RT_INTC_TRIG_LOW_LVL, 2},
|
||||
{RT_INTC_TRIG_LOW_LVL, 2},
|
||||
{RT_INTC_TRIG_LOW_LVL, 2},
|
||||
{RT_INTC_TRIG_NEG_EDGE, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 3},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2}, /* 24 */
|
||||
{RT_INTC_TRIG_POS_EDGE, 2},
|
||||
{RT_INTC_TRIG_POS_EDGE, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_HIGH_LVL, 2},
|
||||
{RT_INTC_TRIG_POS_EDGE, 2},
|
||||
{RT_INTC_TRIG_POS_EDGE, 3},
|
||||
{RT_INTC_TRIG_POS_EDGE, 3},
|
||||
};
|
||||
|
||||
static int
|
||||
rt1310_intc_probe(device_t dev)
|
||||
{
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (!ofw_bus_is_compatible_strict(dev, "rt,pic"))
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "RT1310 Interrupt Controller");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_intc_attach(device_t dev)
|
||||
{
|
||||
struct rt1310_intc_softc *sc = device_get_softc(dev);
|
||||
int rid = 0;
|
||||
int i;
|
||||
|
||||
if (intc_softc)
|
||||
return (ENXIO);
|
||||
|
||||
sc->dev = dev;
|
||||
|
||||
sc->ri_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
||||
RF_ACTIVE);
|
||||
if (!sc->ri_res) {
|
||||
device_printf(dev, "could not alloc resources\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
sc->ri_bst = rman_get_bustag(sc->ri_res);
|
||||
sc->ri_bsh = rman_get_bushandle(sc->ri_res);
|
||||
intc_softc = sc;
|
||||
rt1310_pic_attach(sc);
|
||||
|
||||
intc_write_4(sc, RT_INTC_IECR, 0);
|
||||
intc_write_4(sc, RT_INTC_ICCR, ~0);
|
||||
|
||||
for (i = 0; i <= INTC_NIRQS; ++i) {
|
||||
intc_write_4(sc, RT_INTC_SCR0+i*4,
|
||||
(irqdef[i].ri_trig << RT_INTC_TRIG_SHIF) |
|
||||
irqdef[i].ri_prio);
|
||||
intc_write_4(sc, RT_INTC_SVR0+i*4, i);
|
||||
}
|
||||
|
||||
/* Clear interrupt status registers and disable all interrupts */
|
||||
intc_write_4(sc, RT_INTC_ICCR, ~0);
|
||||
intc_write_4(sc, RT_INTC_IMR, 0);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
rt1310_enable_intr(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
u_int irq;
|
||||
unsigned int value;
|
||||
struct rt1310_intc_softc *sc;
|
||||
|
||||
sc = intc_softc;
|
||||
irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
|
||||
|
||||
value = intc_read_4(sc, RT_INTC_IECR);
|
||||
|
||||
value |= (1 << irq);
|
||||
|
||||
intc_write_4(sc, RT_INTC_IMR, value);
|
||||
intc_write_4(sc, RT_INTC_IECR, value);
|
||||
}
|
||||
|
||||
static void
|
||||
rt1310_disable_intr(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
u_int irq;
|
||||
unsigned int value;
|
||||
struct rt1310_intc_softc *sc;
|
||||
|
||||
sc = intc_softc;
|
||||
irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
|
||||
|
||||
/* Clear bit in ER register */
|
||||
value = intc_read_4(sc, RT_INTC_IECR);
|
||||
value &= ~(1 << irq);
|
||||
intc_write_4(sc, RT_INTC_IECR, value);
|
||||
intc_write_4(sc, RT_INTC_IMR, value);
|
||||
|
||||
intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_map_intr(device_t dev, struct intr_map_data *data,
|
||||
struct intr_irqsrc **isrcp)
|
||||
{
|
||||
struct intr_map_data_fdt *daf;
|
||||
struct rt1310_intc_softc *sc;
|
||||
|
||||
if (data->type != INTR_MAP_DATA_FDT)
|
||||
return (ENOTSUP);
|
||||
|
||||
daf = (struct intr_map_data_fdt *)data;
|
||||
|
||||
if (daf->ncells != 1 || daf->cells[0] >= INTC_NIRQS)
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
*isrcp = &sc->ri_isrcs[daf->cells[0]].ri_isrc;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
rt1310_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
arm_irq_memory_barrier(0);
|
||||
rt1310_disable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
rt1310_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
arm_irq_memory_barrier(0);
|
||||
rt1310_enable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
rt1310_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
u_int irq;
|
||||
struct rt1310_intc_softc *sc;
|
||||
|
||||
arm_irq_memory_barrier(0);
|
||||
sc = intc_softc;
|
||||
irq = ((struct rt1310_irqsrc *)isrc)->ri_irq;
|
||||
|
||||
intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_intr(void *arg)
|
||||
{
|
||||
uint32_t irq;
|
||||
struct rt1310_intc_softc *sc = arg;
|
||||
|
||||
irq = ffs(intc_read_4(sc, RT_INTC_IPR)) - 1;
|
||||
|
||||
if (intr_isrc_dispatch(&sc->ri_isrcs[irq].ri_isrc,
|
||||
curthread->td_intr_frame) != 0) {
|
||||
intc_write_4(sc, RT_INTC_ICCR, 1 << irq);
|
||||
device_printf(sc->dev, "Stray irq %u disabled\n", irq);
|
||||
}
|
||||
|
||||
arm_irq_memory_barrier(0);
|
||||
|
||||
return (FILTER_HANDLED);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_pic_attach(struct rt1310_intc_softc *sc)
|
||||
{
|
||||
struct intr_pic *pic;
|
||||
int error;
|
||||
uint32_t irq;
|
||||
const char *name;
|
||||
intptr_t xref;
|
||||
|
||||
name = device_get_nameunit(sc->dev);
|
||||
for (irq = 0; irq < INTC_NIRQS; irq++) {
|
||||
sc->ri_isrcs[irq].ri_irq = irq;
|
||||
|
||||
error = intr_isrc_register(&sc->ri_isrcs[irq].ri_isrc,
|
||||
sc->dev, 0, "%s,%u", name, irq);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
}
|
||||
|
||||
xref = OF_xref_from_node(ofw_bus_get_node(sc->dev));
|
||||
pic = intr_pic_register(sc->dev, xref);
|
||||
if (pic == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
return (intr_pic_claim_root(sc->dev, xref, rt1310_intr, sc, 0));
|
||||
}
|
||||
|
||||
struct fdt_fixup_entry fdt_fixup_table[] = {
|
||||
{ NULL, NULL }
|
||||
};
|
||||
|
||||
static device_method_t rt1310_intc_methods[] = {
|
||||
DEVMETHOD(device_probe, rt1310_intc_probe),
|
||||
DEVMETHOD(device_attach, rt1310_intc_attach),
|
||||
DEVMETHOD(pic_disable_intr, rt1310_disable_intr),
|
||||
DEVMETHOD(pic_enable_intr, rt1310_enable_intr),
|
||||
DEVMETHOD(pic_map_intr, rt1310_map_intr),
|
||||
DEVMETHOD(pic_post_filter, rt1310_post_filter),
|
||||
DEVMETHOD(pic_post_ithread, rt1310_post_ithread),
|
||||
DEVMETHOD(pic_pre_ithread, rt1310_pre_ithread),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t rt1310_intc_driver = {
|
||||
"pic",
|
||||
rt1310_intc_methods,
|
||||
sizeof(struct rt1310_intc_softc),
|
||||
};
|
||||
|
||||
static devclass_t rt1310_intc_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(pic, simplebus, rt1310_intc_driver, rt1310_intc_devclass, 0, 0, BUS_PASS_INTERRUPT);
|
@ -1,176 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 1994-1998 Mark Brinicombe.
|
||||
* Copyright (c) 1994 Brini.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software written for Brini by Mark Brinicombe
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Brini.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: FreeBSD: sys/arm/lpc/lpc_machdep.c
|
||||
*/
|
||||
|
||||
#include "opt_ddb.h"
|
||||
#include "opt_platform.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#define _ARM32_BUS_DMA_PRIVATE
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/reboot.h>
|
||||
#include <sys/devmap.h>
|
||||
|
||||
#include <vm/vm.h>
|
||||
#include <vm/pmap.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/fdt.h>
|
||||
#include <machine/machdep.h>
|
||||
#include <machine/platform.h>
|
||||
#include <machine/cpu.h>
|
||||
|
||||
#include <arm/ralink/rt1310reg.h>
|
||||
#include <arm/ralink/rt1310var.h>
|
||||
|
||||
#include <dev/fdt/fdt_common.h>
|
||||
|
||||
#ifdef EARLY_PRINTF
|
||||
early_putc_t *early_putc;
|
||||
#endif
|
||||
|
||||
|
||||
uint32_t rt1310_master_clock;
|
||||
|
||||
vm_offset_t
|
||||
platform_lastaddr(void)
|
||||
{
|
||||
|
||||
return (devmap_lastaddr());
|
||||
}
|
||||
|
||||
void
|
||||
platform_probe_and_attach(void)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
platform_gpio_init(void)
|
||||
{
|
||||
|
||||
/*
|
||||
* Set initial values of GPIO output ports
|
||||
*/
|
||||
}
|
||||
|
||||
void
|
||||
platform_late_init(void)
|
||||
{
|
||||
bootverbose = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Add a single static device mapping.
|
||||
* The values used were taken from the ranges property of the SoC node in the
|
||||
* dts file when this code was converted to arm_devmap_add_entry().
|
||||
*/
|
||||
int
|
||||
platform_devmap_init(void)
|
||||
{
|
||||
devmap_add_entry(0x19C00000, 0xE0000);
|
||||
devmap_add_entry(0x1e800000, 0x800000);
|
||||
devmap_add_entry(0x1f000000, 0x400000);
|
||||
return (0);
|
||||
}
|
||||
|
||||
struct arm32_dma_range *
|
||||
bus_dma_get_range(void)
|
||||
{
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
int
|
||||
bus_dma_get_range_nb(void)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_reset(void)
|
||||
{
|
||||
bus_space_tag_t bst;
|
||||
bus_space_handle_t bsh;
|
||||
|
||||
bst = fdtbus_bs_tag;
|
||||
|
||||
/* Enable WDT */
|
||||
/* Instant assert of RESETOUT_N with pulse length 1ms */
|
||||
bus_space_map(bst, 0x1e8c0000, 0x20000, 0, &bsh);
|
||||
bus_space_write_4(bst, bsh, 0, 13000);
|
||||
bus_space_write_4(bst, bsh, 8, (1<<3) | (1<<4) | 7);
|
||||
bus_space_unmap(bst, bsh, 0x20000);
|
||||
|
||||
for (;;)
|
||||
continue;
|
||||
}
|
||||
|
||||
#ifdef RALINK_BOOT_DEBUG
|
||||
void bootdebug1(int c);
|
||||
void bootdebug1(int c)
|
||||
{
|
||||
/* direct put uart physical address */
|
||||
uint8_t* uart_base_addr=(uint8_t*)0x1e840000;
|
||||
*(uart_base_addr) = c;
|
||||
}
|
||||
|
||||
void bootdebug2(int c);
|
||||
void bootdebug2(int c)
|
||||
{
|
||||
#if defined(SOCDEV_PA) && defined(SOCDEV_VA)
|
||||
/* direct put uart map address at locore-v4.S */
|
||||
uint8_t* uart_base_addr=(uint8_t*)0xce840000;
|
||||
*(uart_base_addr) = c;
|
||||
#endif
|
||||
}
|
||||
|
||||
void bootdebug3(int c);
|
||||
void bootdebug3(int c)
|
||||
{
|
||||
bus_space_tag_t bst;
|
||||
bus_space_handle_t bsh;
|
||||
|
||||
bst = fdtbus_bs_tag;
|
||||
bus_space_map(bst, 0x1e840000, 0x20000, 0, &bsh);
|
||||
bus_space_write_1(bst, bsh, 0, c);
|
||||
bus_space_unmap(bst, bsh, 0x20000);
|
||||
}
|
||||
#endif
|
@ -1,343 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
|
||||
* Copyright (c) 2015 Hiroki Mori
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/timetc.h>
|
||||
#include <sys/timeet.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <dev/fdt/fdt_common.h>
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include <arm/ralink/rt1310reg.h>
|
||||
#include <arm/ralink/rt1310var.h>
|
||||
|
||||
struct rt1310_timer_softc {
|
||||
device_t lt_dev;
|
||||
struct eventtimer lt_et;
|
||||
struct resource * lt_res[8];
|
||||
bus_space_tag_t lt_bst0;
|
||||
bus_space_handle_t lt_bsh0;
|
||||
bus_space_tag_t lt_bst1;
|
||||
bus_space_handle_t lt_bsh1;
|
||||
bus_space_tag_t lt_bst2;
|
||||
bus_space_handle_t lt_bsh2;
|
||||
bus_space_tag_t lt_bst3;
|
||||
bus_space_handle_t lt_bsh3;
|
||||
int lt_oneshot;
|
||||
uint32_t lt_period;
|
||||
};
|
||||
|
||||
static struct resource_spec rt1310_timer_spec[] = {
|
||||
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
|
||||
{ SYS_RES_MEMORY, 1, RF_ACTIVE },
|
||||
{ SYS_RES_MEMORY, 2, RF_ACTIVE },
|
||||
{ SYS_RES_MEMORY, 3, RF_ACTIVE },
|
||||
{ SYS_RES_IRQ, 0, RF_ACTIVE },
|
||||
{ SYS_RES_IRQ, 1, RF_ACTIVE },
|
||||
{ SYS_RES_IRQ, 2, RF_ACTIVE },
|
||||
{ -1, 0 }
|
||||
};
|
||||
|
||||
static struct rt1310_timer_softc *timer_softc = NULL;
|
||||
static int rt1310_timer_initialized = 0;
|
||||
static int rt1310_timer_probe(device_t);
|
||||
static int rt1310_timer_attach(device_t);
|
||||
static int rt1310_timer_start(struct eventtimer *,
|
||||
sbintime_t first, sbintime_t period);
|
||||
static int rt1310_timer_stop(struct eventtimer *et);
|
||||
static unsigned rt1310_get_timecount(struct timecounter *);
|
||||
static int rt1310_hardclock(void *);
|
||||
|
||||
#define timer0_read_4(sc, reg) \
|
||||
bus_space_read_4(sc->lt_bst0, sc->lt_bsh0, reg)
|
||||
#define timer0_write_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->lt_bst0, sc->lt_bsh0, reg, val)
|
||||
#define timer0_clear(sc) \
|
||||
do { \
|
||||
timer0_write_4(sc, RT_TIMER_LOAD, 0); \
|
||||
timer0_write_4(sc, RT_TIMER_VALUE, 0); \
|
||||
} while(0)
|
||||
|
||||
#define timer1_read_4(sc, reg) \
|
||||
bus_space_read_4(sc->lt_bst1, sc->lt_bsh1, reg)
|
||||
#define timer1_write_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->lt_bst1, sc->lt_bsh1, reg, val)
|
||||
#define timer1_clear(sc) \
|
||||
do { \
|
||||
timer1_write_4(sc, RT_TIMER_LOAD, 0); \
|
||||
timer1_write_4(sc, RT_TIMER_VALUE, 0); \
|
||||
} while(0)
|
||||
|
||||
#define timer2_read_4(sc, reg) \
|
||||
bus_space_read_4(sc->lt_bst1, sc->lt_bsh2, reg)
|
||||
#define timer2_write_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->lt_bst2, sc->lt_bsh2, reg, val)
|
||||
#define timer3_write_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->lt_bst3, sc->lt_bsh3, reg, val)
|
||||
|
||||
|
||||
static struct timecounter rt1310_timecounter = {
|
||||
.tc_get_timecount = rt1310_get_timecount,
|
||||
.tc_name = "RT1310ATimer1",
|
||||
.tc_frequency = 0, /* will be filled later */
|
||||
.tc_counter_mask = ~0u,
|
||||
.tc_quality = 1000,
|
||||
};
|
||||
|
||||
static int
|
||||
rt1310_timer_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (!ofw_bus_is_compatible(dev, "rt,timer"))
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "RT1310 timer");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_timer_attach(device_t dev)
|
||||
{
|
||||
void *intrcookie;
|
||||
struct rt1310_timer_softc *sc = device_get_softc(dev);
|
||||
phandle_t node;
|
||||
uint32_t freq;
|
||||
|
||||
if (timer_softc)
|
||||
return (ENXIO);
|
||||
|
||||
timer_softc = sc;
|
||||
|
||||
if (bus_alloc_resources(dev, rt1310_timer_spec, sc->lt_res)) {
|
||||
device_printf(dev, "could not allocate resources\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
sc->lt_bst0 = rman_get_bustag(sc->lt_res[0]);
|
||||
sc->lt_bsh0 = rman_get_bushandle(sc->lt_res[0]);
|
||||
sc->lt_bst1 = rman_get_bustag(sc->lt_res[1]);
|
||||
sc->lt_bsh1 = rman_get_bushandle(sc->lt_res[1]);
|
||||
sc->lt_bst2 = rman_get_bustag(sc->lt_res[2]);
|
||||
sc->lt_bsh2 = rman_get_bushandle(sc->lt_res[2]);
|
||||
sc->lt_bst3 = rman_get_bustag(sc->lt_res[3]);
|
||||
sc->lt_bsh3 = rman_get_bushandle(sc->lt_res[3]);
|
||||
|
||||
/* Timer2 interrupt */
|
||||
if (bus_setup_intr(dev, sc->lt_res[6], INTR_TYPE_CLK,
|
||||
rt1310_hardclock, NULL, sc, &intrcookie)) {
|
||||
device_printf(dev, "could not setup interrupt handler\n");
|
||||
bus_release_resources(dev, rt1310_timer_spec, sc->lt_res);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/* Enable timer clock */
|
||||
/*
|
||||
rt1310_pwr_write(dev, LPC_CLKPWR_TIMCLK_CTRL1,
|
||||
LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 |
|
||||
LPC_CLKPWR_TIMCLK_CTRL1_TIMER1);
|
||||
*/
|
||||
|
||||
/* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */
|
||||
|
||||
node = ofw_bus_get_node(dev);
|
||||
if (OF_getprop(OF_parent(node), "bus-frequency", &freq,
|
||||
sizeof(pcell_t)) <= 0) {
|
||||
bus_release_resources(dev, rt1310_timer_spec, sc->lt_res);
|
||||
bus_teardown_intr(dev, sc->lt_res[2], intrcookie);
|
||||
device_printf(dev, "could not obtain base clock frequency\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
freq = fdt32_to_cpu(freq);
|
||||
|
||||
/* Set desired frequency in event timer and timecounter */
|
||||
sc->lt_et.et_frequency = (uint64_t)freq;
|
||||
rt1310_timecounter.tc_frequency = (uint64_t)freq;
|
||||
|
||||
sc->lt_et.et_name = "RT1310ATimer2";
|
||||
sc->lt_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
|
||||
sc->lt_et.et_quality = 1000;
|
||||
sc->lt_et.et_min_period = (0x00000002LLU << 32) / sc->lt_et.et_frequency;
|
||||
sc->lt_et.et_max_period = (0xfffffffeLLU << 32) / sc->lt_et.et_frequency;
|
||||
sc->lt_et.et_start = rt1310_timer_start;
|
||||
sc->lt_et.et_stop = rt1310_timer_stop;
|
||||
sc->lt_et.et_priv = sc;
|
||||
|
||||
et_register(&sc->lt_et);
|
||||
tc_init(&rt1310_timecounter);
|
||||
|
||||
/* Reset and enable timecounter */
|
||||
|
||||
timer0_write_4(sc, RT_TIMER_CONTROL, 0);
|
||||
timer1_write_4(sc, RT_TIMER_CONTROL, 0);
|
||||
timer2_write_4(sc, RT_TIMER_CONTROL, 0);
|
||||
timer3_write_4(sc, RT_TIMER_CONTROL, 0);
|
||||
|
||||
timer1_write_4(sc, RT_TIMER_LOAD, ~0);
|
||||
timer1_write_4(sc, RT_TIMER_VALUE, ~0);
|
||||
timer1_write_4(sc, RT_TIMER_CONTROL,
|
||||
RT_TIMER_CTRL_ENABLE | RT_TIMER_CTRL_PERIODCAL);
|
||||
|
||||
/* DELAY() now can work properly */
|
||||
rt1310_timer_initialized = 1;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
|
||||
{
|
||||
struct rt1310_timer_softc *sc = (struct rt1310_timer_softc *)et->et_priv;
|
||||
uint32_t ticks;
|
||||
|
||||
if (period == 0) {
|
||||
sc->lt_oneshot = 1;
|
||||
sc->lt_period = 0;
|
||||
} else {
|
||||
sc->lt_oneshot = 0;
|
||||
sc->lt_period = ((uint32_t)et->et_frequency * period) >> 32;
|
||||
}
|
||||
|
||||
if (first == 0)
|
||||
ticks = sc->lt_period;
|
||||
else
|
||||
ticks = ((uint32_t)et->et_frequency * first) >> 32;
|
||||
|
||||
/* Reset timer */
|
||||
timer2_write_4(sc, RT_TIMER_CONTROL, 0);
|
||||
|
||||
/* Start timer */
|
||||
timer2_write_4(sc, RT_TIMER_LOAD, ticks);
|
||||
timer2_write_4(sc, RT_TIMER_VALUE, ticks);
|
||||
timer2_write_4(sc, RT_TIMER_CONTROL,
|
||||
RT_TIMER_CTRL_ENABLE | RT_TIMER_CTRL_INTCTL);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
rt1310_timer_stop(struct eventtimer *et)
|
||||
{
|
||||
struct rt1310_timer_softc *sc = (struct rt1310_timer_softc *)et->et_priv;
|
||||
|
||||
timer2_write_4(sc, RT_TIMER_CONTROL, 0);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t rt1310_timer_methods[] = {
|
||||
DEVMETHOD(device_probe, rt1310_timer_probe),
|
||||
DEVMETHOD(device_attach, rt1310_timer_attach),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t rt1310_timer_driver = {
|
||||
"timer",
|
||||
rt1310_timer_methods,
|
||||
sizeof(struct rt1310_timer_softc),
|
||||
};
|
||||
|
||||
static devclass_t rt1310_timer_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(timer, simplebus, rt1310_timer_driver, rt1310_timer_devclass, 0, 0, BUS_PASS_TIMER);
|
||||
|
||||
static int
|
||||
rt1310_hardclock(void *arg)
|
||||
{
|
||||
struct rt1310_timer_softc *sc = (struct rt1310_timer_softc *)arg;
|
||||
|
||||
/* Reset pending interrupt */
|
||||
timer2_write_4(sc, RT_TIMER_CONTROL,
|
||||
timer2_read_4(sc, RT_TIMER_CONTROL) | 0x08);
|
||||
timer2_write_4(sc, RT_TIMER_CONTROL,
|
||||
timer2_read_4(sc, RT_TIMER_CONTROL) & 0x1fb);
|
||||
|
||||
/* Start timer again */
|
||||
if (!sc->lt_oneshot) {
|
||||
timer2_write_4(sc, RT_TIMER_LOAD, sc->lt_period);
|
||||
timer2_write_4(sc, RT_TIMER_VALUE, sc->lt_period);
|
||||
timer2_write_4(sc, RT_TIMER_CONTROL,
|
||||
RT_TIMER_CTRL_ENABLE | RT_TIMER_CTRL_INTCTL);
|
||||
}
|
||||
|
||||
if (sc->lt_et.et_active)
|
||||
sc->lt_et.et_event_cb(&sc->lt_et, sc->lt_et.et_arg);
|
||||
|
||||
return (FILTER_HANDLED);
|
||||
}
|
||||
|
||||
static unsigned
|
||||
rt1310_get_timecount(struct timecounter *tc)
|
||||
{
|
||||
return ~timer1_read_4(timer_softc, RT_TIMER_VALUE);
|
||||
}
|
||||
|
||||
void
|
||||
DELAY(int usec)
|
||||
{
|
||||
uint32_t counter;
|
||||
uint32_t first, last;
|
||||
int val = (rt1310_timecounter.tc_frequency / 1000000 + 1) * usec;
|
||||
|
||||
/* Timer is not initialized yet */
|
||||
if (!rt1310_timer_initialized) {
|
||||
for (; usec > 0; usec--)
|
||||
for (counter = 100; counter > 0; counter--)
|
||||
;
|
||||
return;
|
||||
}
|
||||
TSENTER();
|
||||
|
||||
first = rt1310_get_timecount(&rt1310_timecounter);
|
||||
while (val > 0) {
|
||||
last = rt1310_get_timecount(&rt1310_timecounter);
|
||||
if (last < first) {
|
||||
/* Timer rolled over */
|
||||
last = first;
|
||||
}
|
||||
|
||||
val -= (last - first);
|
||||
first = last;
|
||||
}
|
||||
TSEXIT();
|
||||
}
|
@ -1,82 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
|
||||
* Copyright (c) 2015 Hiroki Mori
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _ARM_RALINK_RT1310REG_H
|
||||
#define _ARM_RALINK_RT1310REG_H
|
||||
|
||||
/*
|
||||
* Interrupt controller
|
||||
*/
|
||||
|
||||
#define RT_INTC_SCR0 0x00
|
||||
#define RT_INTC_SVR0 0x80
|
||||
#define RT_INTC_ISR 0x104
|
||||
#define RT_INTC_IPR 0x108
|
||||
#define RT_INTC_IMR 0x10c
|
||||
#define RT_INTC_IECR 0x114
|
||||
#define RT_INTC_ICCR 0x118
|
||||
|
||||
#define RT_INTC_TRIG_LOW_LVL (0)
|
||||
#define RT_INTC_TRIG_HIGH_LVL (1)
|
||||
#define RT_INTC_TRIG_NEG_EDGE (2)
|
||||
#define RT_INTC_TRIG_POS_EDGE (3)
|
||||
|
||||
#define RT_INTC_TRIG_SHIF 6
|
||||
|
||||
/*
|
||||
* Timer 0|1|2|3.
|
||||
*/
|
||||
|
||||
#define RT_TIMER_LOAD 0x00
|
||||
#define RT_TIMER_VALUE 0x04
|
||||
#define RT_TIMER_CONTROL 0x08
|
||||
|
||||
#define RT_TIMER_CTRL_INTCTL (1 << 1)
|
||||
#define RT_TIMER_CTRL_INTCLR (1 << 2)
|
||||
#define RT_TIMER_CTRL_INTMASK (1 << 3)
|
||||
#define RT_TIMER_CTRL_DIV16 (3 << 4)
|
||||
#define RT_TIMER_CTRL_DIV256 (7 << 4)
|
||||
#define RT_TIMER_CTRL_PERIODCAL (1 << 7)
|
||||
#define RT_TIMER_CTRL_ENABLE (1 << 8)
|
||||
|
||||
#define RT_TIMER_INTERVAL (5000*150)
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
|
||||
#define RT_GPIO_PORTA (0)
|
||||
#define RT_GPIO_PORTB (1)
|
||||
|
||||
#define RT_GPIO_OFF_PADR (0x0)
|
||||
#define RT_GPIO_OFF_PADIR (0x4)
|
||||
#define RT_GPIO_OFF_PBDR (0x8)
|
||||
#define RT_GPIO_OFF_PBDIR (0xC)
|
||||
|
||||
#endif /* _ARM_RALINK_RT1310REG_H */
|
@ -1,44 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _ARM_RT_RTVAR_H
|
||||
#define _ARM_RT_RTVAR_H
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/bus.h>
|
||||
#include <machine/bus.h>
|
||||
|
||||
/* GPIO */
|
||||
void rt1310_gpio_init(void);
|
||||
int rt1310_gpio_set_flags(device_t, int, int);
|
||||
int rt1310_gpio_set_state(device_t, int, int);
|
||||
int rt1310_gpio_get_state(device_t, int, int *);
|
||||
|
||||
extern uint32_t rt1310_master_clock;
|
||||
|
||||
#endif /* _ARM_RT_RTVAR_H */
|
@ -1,9 +0,0 @@
|
||||
# $FreeBSD$
|
||||
files "../ralink/files.ralink"
|
||||
cpu CPU_ARM9E
|
||||
machine arm
|
||||
makeoptions CONF_CFLAGS="-march=armv5te"
|
||||
options INTRNG
|
||||
|
||||
makeoptions KERNVIRTADDR=0xc0000000
|
||||
options KERNVIRTADDR=0xc0000000
|
Loading…
Reference in New Issue
Block a user