Merge commit 2e24219d3 from llvm git (by Hans Wennborg):
[MC][ARM] Resolve some pcrel fixups at assembly time (PR44929) MC currently does not emit these relocation types, and lld does not handle them. Add FKF_Constant as a work-around of some ARM code after D72197. Eventually we probably should implement these relocation types. By Fangrui Song! Differential revision: https://reviews.llvm.org/D72892 This re-enables using the arm 'adr' pseudo instruction on global symbols again. It was broken as a side-effect of upstream commit 2bfee35cb, which lead to "error: unsupported relocation on symbol" when assembling such constructs, which are used in e.g. sys/arm/arm/locore-v[46].S. PR: 244251
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang1000-import/; revision=358396
@ -22,7 +22,12 @@ struct MCFixupKindInfo {
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FKF_IsAlignedDownTo32Bits = (1 << 1),
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FKF_IsAlignedDownTo32Bits = (1 << 1),
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/// Should this fixup be evaluated in a target dependent manner?
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/// Should this fixup be evaluated in a target dependent manner?
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FKF_IsTarget = (1 << 2)
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FKF_IsTarget = (1 << 2),
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/// This fixup kind should be resolved if defined.
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/// FIXME This is a workaround because we don't support certain ARM
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/// relocation types. This flag should eventually be removed.
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FKF_Constant = 1 << 3,
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};
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};
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/// A target specific name for the fixup kind. The names will be unique for
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/// A target specific name for the fixup kind. The names will be unique for
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@ -224,6 +224,7 @@ bool MCAssembler::evaluateFixup(const MCAsmLayout &Layout,
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return getBackend().evaluateTargetFixup(*this, Layout, Fixup, DF, Target,
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return getBackend().evaluateTargetFixup(*this, Layout, Fixup, DF, Target,
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Value, WasForced);
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Value, WasForced);
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unsigned FixupFlags = getBackendPtr()->getFixupKindInfo(Fixup.getKind()).Flags;
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bool IsPCRel = getBackendPtr()->getFixupKindInfo(Fixup.getKind()).Flags &
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bool IsPCRel = getBackendPtr()->getFixupKindInfo(Fixup.getKind()).Flags &
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MCFixupKindInfo::FKF_IsPCRel;
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MCFixupKindInfo::FKF_IsPCRel;
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@ -239,8 +240,9 @@ bool MCAssembler::evaluateFixup(const MCAsmLayout &Layout,
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if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined()) {
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if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined()) {
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IsResolved = false;
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IsResolved = false;
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} else if (auto *Writer = getWriterPtr()) {
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} else if (auto *Writer = getWriterPtr()) {
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IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(
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IsResolved = (FixupFlags & MCFixupKindInfo::FKF_Constant) ||
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*this, SA, *DF, false, true);
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Writer->isSymbolRefDifferenceFullyResolvedImpl(
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*this, SA, *DF, false, true);
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}
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}
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}
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}
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} else {
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} else {
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@ -55,31 +55,29 @@ Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
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}
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}
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const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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unsigned IsPCRelConstant =
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MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant;
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const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
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const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// This table *must* be in the order that the fixup_* kinds are defined in
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// ARMFixupKinds.h.
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// ARMFixupKinds.h.
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//
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//
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// Name Offset (bits) Size (bits) Flags
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// Name Offset (bits) Size (bits) Flags
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{"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
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{"fixup_t2_ldst_pcrel_12", 0, 32,
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{"fixup_t2_ldst_pcrel_12", 0, 32,
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MCFixupKindInfo::FKF_IsPCRel |
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IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
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{"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
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{"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_t2_pcrel_10", 0, 32,
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{"fixup_t2_pcrel_10", 0, 32,
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MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_t2_pcrel_9", 0, 32,
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{"fixup_t2_pcrel_9", 0, 32,
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MCFixupKindInfo::FKF_IsPCRel |
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IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{"fixup_thumb_adr_pcrel_10", 0, 8,
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{"fixup_thumb_adr_pcrel_10", 0, 8,
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MCFixupKindInfo::FKF_IsPCRel |
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IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
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{"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_t2_adr_pcrel_12", 0, 32,
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{"fixup_t2_adr_pcrel_12", 0, 32,
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MCFixupKindInfo::FKF_IsPCRel |
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IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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